A method and computing device to identify a PCIE endpoint device

Abstract

Embodiments of the present application disclose a method for identifying PCIE terminal equipment and a computing device, which are used for efficiently identifying PCIE terminal equipment. The method comprises the following steps: obtaining first in-place information, the first in-place information indicating that a first PCIE slot is physically connected with a first PCIE terminal equipment; obtaining first PCIE slot information based on the first in-place information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port; querying a BUS number range hung by the first root port; and traversing PCIE equipment in the BUS number range to identify all PCIE terminal equipment in the BUS number range. Before traversing PCIE equipment hung by a CPU of the computing device, the first in-place information indicating physical connection of the PCIE equipment is obtained, and the root port hung with the PCIE terminal equipment is traversed, so that the workload of traversal is reduced, and the efficiency of identifying the PCIE terminal equipment is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of servers, and particularly relate to a method for identifying PCIE terminal devices and a computing device. BACKGROUND

[0002] With the continuous development and progress of server technology, the number and types of high-speed serial computer expansion buses (peripheral component interconnect express, PCIE) devices that can be installed on a server are also increasing. As an out-of-band management system of a server, a baseboard management controller (BMC) needs to identify and manage the PCIE devices installed on the server.

[0003] Currently, the BCM cooperates with the basic input / output system (BIOS), and the BIOS initializes and scans all devices in the system startup phase and stores the asset information of all devices in the register of the CPU. The BMC needs to traverse all root ports of the CPU in the server to find the PCIE devices, which is low in efficiency. With the increase in the number and types of PCIE devices that can be installed on a server, how to efficiently and accurately identify PCIE terminal devices has become a problem that needs to be solved by the current technical personnel. SUMMARY

[0004] Embodiments of the present application provide a method for identifying PCIE terminal devices and a computing device, which are used for efficiently identifying PCIE terminal devices.

[0005] A first aspect of the present application provides a method for identifying PCIE terminal devices, comprising: obtaining first in-place information, the first in-place information indicating that a first PCIE slot is physically connected with a first PCIE terminal device; based on the first in-place information, obtaining first PCIE slot information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port; querying a BUS number range hung under the first root port; and traversing PCIE devices in the BUS number range to identify all PCIE terminal devices in the BUS number range.

[0006] In the method, the first in-place information indicating that the first PCIE slot is physically connected with the first PCIE terminal device is acquired, and the first PCIE slot information is acquired based on the first in-place information, and the first slot information indicates that the first PCIE slot corresponds to the first root port; after the BMC queries the BUS number range hung by the first root port from the CPU, PCIE devices in the BUS number range are traversed to identify all PCIE terminal devices in the BUS number range. Before the PCIE devices hung by the CPU of the computing device are traversed, the first in-place information indicating that the PCIE devices are physically connected is acquired, and the root port hung with the PCIE terminal device is traversed, so that the workload of traversal is reduced, and the efficiency of identifying the PCIE terminal device is improved.

[0007] In a possible implementation manner of the first aspect, the first PCIE slot information includes a first mapping relationship, and the first mapping relationship is a mapping relationship between the first PCIE slot and the first root port; and the first mapping relationship is stored in firmware of the BMC.

[0008] In the method, the first PCIE slot information includes a first mapping relationship, and the first mapping relationship is a mapping relationship between the first PCIE slot and the first root port; and the first mapping relationship is stored in firmware of the BMC. The first mapping relationship is stored in the firmware of the BMC, so that the first mapping relationship is avoided to be stored in the BIOS, and the inconvenience caused by the need of the BIOS to re-scan the PCIE device when the PCIE device is updated is avoided.

[0009] In a possible implementation manner of the first aspect, the BUS number range hung by the first root port is queried by sending a first instruction to the CPU.

[0010] In the method, the BMC queries the BUS number range hung by the first root port by sending a first instruction to the CPU, the BUS number range hung by the first root port is queried by using the first link between the BMC and the CPU, and the efficiency of identifying the PCIE terminal device is improved.

[0011] In a possible implementation of the first aspect, the first instruction is CPU PCI Configuration Read. The method sends the CPU PCI Configuration Read to the CPU through the SMLINK bus between the BMC and the CPU to obtain the BUS number range under the first root port. The BUS number range under the first root port is obtained through the CPU PCI Configuration Read instruction, and the index of the first root port to the BUS number under the root port is obtained, thereby reducing the error probability of traversal caused by data errors in obtaining the global BUS number range.

[0012] In a possible implementation of the first aspect, the first instruction is RdPCIConfigLocal. The method sends the RdPCIConfigLocal to the CPU through the PECI link between the BMC and the CPU to obtain the BUS number range under the first root port. The index of the first root port to the BUS number under the root port is obtained, thereby reducing the error probability of traversal caused by data errors in obtaining the global BUS number range.

[0013] In a possible implementation of the first aspect, the first in-place information is obtained in any of the following ways: the BMC obtains the first in-place information through a link between a GPIO interface and a PCIE slot; the BMC obtains the first in-place information through a link between an I2C bus and an IO expansion chip and the PCIE slot; or the BMC obtains the first in-place information through a link between a LOCALBUS bus and a CPLD and the PCIE slot.

[0014] In the method, the first in-place information can be obtained by the BMC through a link between a GPIO interface and a PCIE slot, or through a link between an I2C bus and an IO expansion chip and the PCIE slot, or through a link between a LOCALBUS bus and a CPLD and the PCIE slot. The BMC can obtain the first in-place information through different links, thereby improving the stability of obtaining the first in-place information.

[0015] In a possible implementation of the first aspect, the method further includes: traversing the PCIE devices in the BUS number range, identifying all PCIE terminal devices in the BUS number range, including: traversing the PCIE devices in the BUS number range, obtaining a first PCIE device, the first PCIE device being any PCIE device in the BUS number range; obtaining a base class of the first PCIE device, and if the base class is a preset value, the first PCIE device is a terminal device.

[0016] In the method, the first PCIE device is obtained by traversing the PCIE devices in the BUS number range, the first PCIE device being any PCIE device in the BUS number range, and the base class of the first PCIE device is obtained, and if the base class is a preset value, the first PCIE device is a terminal device. The base class of the first PCIE device is used to determine whether the first PCIE device is a terminal device, and the efficiency of identifying whether the first PCIE device is a terminal device is improved.

[0017] In a possible implementation of the first aspect, the method further includes: if there is no terminal device in the PCIE devices in the BUS number range, generating PCIE device exception information. In the method, if there is no terminal device in the PCIE devices in the BUS number range, it indicates that the first PCIE terminal device has failed, and the PCIE device exception information is generated. While quickly identifying the PCIE terminal device, it is also possible to determine whether there is a failure of the PCIE terminal device, and the working efficiency of the computing device is further improved.

[0018] In a possible implementation of the first aspect, the method further includes: obtaining a first identifier of the PCIE terminal device from the first PCIE terminal device; searching for a PCIE configuration file corresponding to the first identifier in the BMC firmware according to the first identifier; and managing the PCIE device according to the PCIE configuration file.

[0019] In the method, the first identifier of the first PCIE terminal device is obtained from the first PCIE terminal device, and the PCIE configuration file corresponding to the first identifier is searched for in the BMC firmware according to the first identifier, and the first PCIE terminal device is managed according to the PCIE configuration file. The configuration file corresponding to the first identifier is obtained from the BMC firmware through the first identifier, and the specific content of the configuration file corresponding to the first identifier can be adjusted by the staff at any time according to the demand, and the convenience of updating the configuration file is improved.

[0020] In a possible implementation of the first aspect, the first identifier includes a Vender ID, a Device ID, a Subsystem Vendor ID, and a Subsystem ID. In the method, the first identifier can be a vendor ID, a Device ID, a Subsystem Vendor ID, and a Subsystem ID set for different batches of PCIE devices of different manufacturers. The method saves the work of the user to pre-set the first identifier, and improves the work efficiency.

[0021] In a possible implementation of the first aspect, the PCIE configuration file includes at least one or more of asset information of the PCIE terminal device, I2C topology and device address on the PCIE terminal device, and speed regulation strategy of the PCIE terminal device. In the method, the PCIE configuration file includes at least one or more of asset information of the PCIE terminal device, I2C topology and device address on the PCIE terminal device, and speed regulation strategy of the PCIE terminal device. The method improves the efficiency of obtaining the configuration file of the PCIE terminal device by preparing multiple PCIE configuration files for the PCIE terminal device, thereby improving the work efficiency of the computing device.

[0022] The second aspect of the application provides a computing device, including: a circuit board, the circuit board being provided with a CPU, a BMC chip, and at least one PCIE slot; the CPU being electrically connected with the at least one PCIE slot and being used for processing instructions; the BMC chip being electrically connected with the CPU through a first link and being electrically connected with the at least one PCIE slot through a second link, the BMC chip being used for obtaining first in-place information through the second link, the first in-place information indicating that a first PCIE device is physically connected with a first PCIE slot, the first PCIE slot being any one of the at least one PCIE slot; the BMC chip obtaining first PCIE slot information through the first link based on the first in-place information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port; the BMC chip querying a BUS number range hung under the first root port from the CPU; and all PCIE terminal devices in the BUS number range are identified by traversing the PCIE devices in the BUS number range.

[0023] In a possible implementation of the second aspect, the first link includes an SMLINK bus between the BMC and the CPU, or a PECI link between the BMC and the CPU.

[0024] In a possible implementation of the second aspect, the second link includes any one or more of a link through which the BMC is connected to the PCIE slot via a GPIO, a link through which the BMC is connected to the PCIE slot via an I2C bus and a PCA9555, and a link through which the BMC is connected to the PCIE slot via a LOCALBUS bus and a CPLD.

[0025] The third aspect of the present application provides a computing device, comprising: a PCIE device in place detection module configured to obtain first in place information, the first in place information indicating that the first PCIE slot is physically connected to a first PCIE terminal device; a root port information obtaining module configured to obtain first PCIE slot information based on the first in place information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port; the root port information obtaining module is further configured to query a BUS number range hung by the first root port based on the determined first root port; and a PCIE device judging module configured to traverse PCIE devices in the BUS number range to identify all PCIE terminal devices in the BUS number range.

[0026] In a possible implementation of the third aspect, the first PCIE slot information includes a first mapping relationship, and the first mapping relationship is a mapping relationship between the first PCIE slot and the first root port; and the first mapping relationship is stored in firmware of the BMC.

[0027] In a possible implementation of the third aspect, the root port information obtaining module is specifically configured to send a first instruction to a CPU to query a BUS number range hung by the first root port.

[0028] In a possible implementation of the third aspect, the first instruction is a CPU PCI Configuration Read.

[0029] In a possible implementation of the third aspect, the first instruction is RdPCIConfigLocal.

[0030] In a possible implementation of the third aspect, the PCIE device in place detection module is specifically configured to obtain the first in place information in any one or more of the following manners: obtaining the first in place information through a link through which a GPIO interface is connected to the PCIE slot; obtaining the first in place information through a link through which an expansion chip is connected to the PCIE slot; and obtaining the first in place information through a link through which a CPLD is connected to the PCIE slot.

[0031] In a possible implementation manner of the third aspect, the PCIE device judging module is specifically configured to: traverse PCIE devices in the BUS number range to obtain a first PCIE device, the first PCIE device being any PCIE device in the BUS number range; and obtain a base class of the first PCIE device, and if the base class is a preset value, the first PCIE device is a terminal device.

[0032] In a possible implementation manner of the third aspect, the computing device further includes a PCIE device exception processing module configured to generate PCIE device exception information if there is no terminal device in the PCIE devices in the BUS number range.

[0033] In a possible implementation manner of the third aspect, the computing device further includes a PCIE device configuration file matching module configured to: obtain a first identifier of the PCIE terminal device from the first PCIE terminal device; search for a PCIE configuration file corresponding to the first identifier in a BMC firmware according to the first identifier; and manage the first PCIE terminal device according to the PCIE configuration file.

[0034] In a possible implementation manner of the third aspect, the first identifier includes a Vender ID, a Device ID, a Subsystem Vendor ID, and a Subsystem ID.

[0035] In a possible implementation manner of the third aspect, the PCIE configuration file includes at least one or more of asset information of the PCIE terminal device, an I2C topology and device address on the PCIE terminal device, and a speed regulation strategy of the PCIE terminal device.

[0036] The fourth aspect of the present application provides a computing device, including a processor and a memory, the memory being configured to store computer execution instructions, and the processor being configured to execute the computer execution instructions stored in the memory to enable the electronic device to execute the method described in any one of the preceding first aspect and possible implementation manners of the first aspect.

[0037] The fifth aspect of the present application provides a computer readable storage medium, including a program, when the program is executed on a computer, enabling the computer to execute the method described in any one of the preceding first aspect and possible implementation manners of the first aspect.

[0038] The sixth aspect of the present application provides a computer program product including instructions, when the instructions are executed on a computer, enabling the computer to execute the method described in any one of the preceding first aspect and possible implementation manners of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A structural schematic diagram of a computing device provided by an embodiment of the present application is shown in FIG. 1.

[0040] Figure 2 A structural schematic diagram of a PCIE bus provided by an embodiment of the present application is shown in FIG. 2.

[0041] Figure 3 Another structural schematic diagram of a computing device provided by an embodiment of the present application is shown in FIG. 3.

[0042] Figure 4 A flowchart of a data processing method provided by an embodiment of the present application is shown in FIG. 4.

[0043] Figure 5 Another structural schematic diagram of a computing device provided by an embodiment of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0044] The embodiments of the present application will be described below in conjunction with the drawings, obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Those skilled in the art can know that with the development of technology and the appearance of new scenes, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0045] The terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0046] For the convenience of understanding, first, the application scenario of the scheme proposed by the present application is briefly introduced, please refer to Figure 1 , Figure 1 A structural schematic diagram of a computing device provided by an embodiment of the present application is shown in FIG. 1. The computing device includes a processor 101, a memory 102, an internal memory 103, a communication interface 104, and a bus system 105.

[0047] The bus system 105 is used to couple various hardware components of the computing device together. The bus system 105 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 105 can be divided into an address bus, a data bus, a control bus, etc.

[0048] The communication interface 104 is used to implement a communication connection between the computing device and other devices. It can be a wired interface (such as an Ethernet interface), an internal interface (such as a high-speed serial computer expansion bus (PCIe) bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless local area network interface).

[0049] The memory 103 is used to temporarily store the calculation data in the processor and the data exchanged with the external memory such as the hard disk.

[0050] Memory 102, used to store program instructions and data, may include volatile memory, such as random access memory (RAM); memory 102 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD) or solid-state drive (SSD); memory 102 may also include a combination of the above types.

[0051] Processor 101 is used to read instructions and data stored in memory 102 and can be composed of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a general array logic (GAL), or any combination thereof.

[0052] Taking the CPU as an example, the CPU can be connected to the PCIE bus. PCIE is a tree-like interface bus that provides a bus interface for the CPD to access peripheral devices. Figure 2 , Figure 2 A structural diagram of the PCIE bus provided in an embodiment of the present application.

[0053] Depend on Figure 2 It can be seen that the CPU is equipped with a root port, and a CPU can have multiple root ports. Here we take one of the root ports as an example. The PCI bus directly connected to the root port is called bus0. Bus0 can connect to endpoints and / or switches. Figure 2 In the structure shown, rootport connects endpoint1 and switch1 via bus0, and switch1 connects endpoint2 and switch2 via bus1. Furthermore, switch2 connects endpoint3 and endpoint4 via bus2.

[0054] In Figure 2 In the PCIE topology shown, the PCIE protocol supports 256 buses, each bus supports up to 32 devices, and each device supports up to 8 functions, and the bus, device and function constitute the identity of each PCIE device node.

[0055] It should be noted that Figure 2 The structural diagram of the PCIE bus is only an example, and in actual application, the CPU can connect any number of endpoints and / or switches through bus0, which is not limited here.

[0056] After the BMC is started, it needs to obtain the information of all PCIE devices connected to the CPU through the bus and initialize these devices.

[0057] With the continuous updating of hardware and software, how to further improve the efficiency of obtaining PCIE asset information has become a problem that current technical personnel have to face. In the related technology, the BIOS completely depends on the initialization and scanning of all devices in the device startup stage to obtain the asset information of the PCIE device, and writes these information into the register of the corresponding CPU for subsequent use. When the PCIE devices connected to the computer increase or decrease, the newly added or reduced asset information needs to be updated, and the BIOS can only update the BIOS firmware in the computer startup stage to update the asset information of the PCIE device, so that the asset information of the PCIE device can only be updated in the computer startup stage. How to eliminate this limitation and make the asset information of the PCIE device update not limited to the computer running stage.

[0058] Based on the foregoing Figure 1 The computing device architecture introduced and Figure 2 The architecture of the PCIE bus introduced, the following will be combined Figure 3 The specific application scenarios of the present application are exemplified, Figure 3 Another structural diagram of the computing device provided by the embodiment of the present application.

[0059] The computing device includes a circuit board 30, the circuit board 30 is provided with a CPU 301, a BMC chip 302 and at least one PCIE slot 303.

[0060] Among them, any root port of the CPU 301 is electrically connected with the PCIE slot 303, for transmitting PCIE signals in the passageway between the root port and the PCIE slot.

[0061] The BMC chip 302 is electrically connected with the at least one PCIE slot 303 through a second link, and is configured to acquire first in-place information, the first in-place information indicating that a first PCIE terminal device is physically connected with a first PCIE slot, and the first PCIE slot is any one of the at least one PCIE slot.

[0062] Specifically, the second link can be that the BMC chip 302 is electrically connected with the at least one PCIE slot 303 through a GPIO link.

[0063] Optionally, the second link can also be that the BMC chip 302 is electrically connected with an IO expansion chip through an I2C bus, and the IO expansion chip is electrically connected with the at least one PCIE slot 303, where the IO expansion chip can be a PCA9555.

[0064] Optionally, the second link can also be that the BMC chip 302 is electrically connected with a CPLD through a LOCALBUS bus, and the CPLD is electrically connected with the at least one PCIE slot 303.

[0065] The BMC chip 302 is electrically connected with the CPU 301 through a first link, and is configured to acquire first PCIE slot information out of band, where the first PCIE slot information indicates that the first PCIE slot corresponds to a first root port.

[0066] Specifically, the first link can be that the CPU 301 is electrically connected with the BMC chip 302 through a PECI bus.

[0067] Optionally, the circuit board 30 can also be provided with a PCH (Platform Controller Hub, South Bridge) 304, and the first link can also be that the CPU 301 is electrically connected with the PCH 304 through a DMI, where the PCH 304 is electrically connected with the BMC chip 302 through an SMLINK bus.

[0068] The BMC chip 302 is also configured to send a first instruction to the CPU 301 through the first link to query a BUS number range under the first root port, and to traverse PCIE devices in the BUS number range to identify all PCIE terminal devices in the BUS number range.

[0069] In combination with the foregoing Figure 3 The computing device described above, the scheme proposed in the present application is introduced below, please refer to Figure 4 , Figure 4 A flowchart of a data processing method provided by an embodiment of the present application.

[0070] 401、acquire first in-place information;

[0071] Here, the BMC chip can obtain first in-place information from the first PCIE slot through the second link, and the first in-place information indicates that the first PCIE terminal device is physically connected with the first PCIE slot.

[0072] For example, the BMC chip can obtain the in-place information of the first PCIE slot in a way of active polling at a certain time interval, so as to learn the change of the in-place condition of the PCIE device on the first PCIE slot. In addition, the BMC chip can trigger the obtaining of the in-place information of the first PCIE slot once the in-place signal of the first PCIE slot changes, so as to learn the change of the in-place condition of the first PCIE slot.

[0073] In another example, the BMC chip obtains the in-place information of each PCIE slot on the motherboard in a way of active polling at a certain time interval, and the PCIE slot with the in-place information is referred to as the first PCIE slot. It should be understood that there can be one or more first PCIE slots at the same time. It should be noted that the way of obtaining the in-place information of the first PCIE slot proposed in the embodiments of the present application is only an example, and the way of obtaining the in-place information of the first PCIE slot is not limited in actual application.

[0074] In this method, the BMC chip can obtain the first in-place information through different links, thereby improving the stability of obtaining the first in-place information.

[0075] 402、obtaining first PCIE slot information based on the first in-place information;

[0076] After the BMC chip obtains the first in-place information, the BMC chip obtains the first PCIE slot information from the BMC firmware, and the first PCIE slot information indicates that the first PCIE slot corresponds to the first root port. The correspondence between the first PCIE slot and the first root port can be stored in the BMC firmware in the form of a first mapping relationship.

[0077] 403、querying the BUS number range hung by the first root port based on the determined first root port;

[0078] The BMC chip queries the bus interval hung by the first root port from the CPU through the first link.

[0079] According to different first links, there are different ways to obtain the BUS number range hung by the first root port. For details, please refer to the following two cases:

[0080] Case one: when the BMC queries the CPU through the SMLINK bus, the SECBUS information is obtained from the offset address 19H in the register through the CPU PCI configuration read command, and the SUBBUS information is obtained from the offset address 1AH in the register through the SMLINK bus, since the SECBUS represents the next bus number, and the SUBBUS represents the maximum PCIE bus number in the current PCIE sub-tree. Then the bus number range under the first root port is obtained.

[0081] In which, the bus number range under the first root port can also be obtained in the form of the relative offset of the first root port under the CPU by setting bit 6 of byte 4 to 1.

[0082] Optionally, the bus number range under the first root port can also be obtained in the form of the global offset of the BUS number in the computing device by setting bit 6 of byte 4 to 0.

[0083] Case two: the BMC can also query the CPU through the PECI bus, and the SECBUS information is obtained from the offset address 19H in the register through the RdPCIConfigLocal command, and the SUBBUS information is obtained from the offset address 1AH in the register through the PECI bus, since the SECBUS represents the next bus number, and the SUBBUS represents the maximum PCIE bus number in the current PCIE sub-tree. Then the bus number range under the first root port is obtained in the form of the relative offset of the BUS number under the first root port.

[0084] Optionally, the bus number range under the first root port can also be obtained in the form of the global offset of the BUS number in the computing device by the RdPCIConfig command.

[0085] It should be noted that the above description of the BMC chip obtaining the BUS number range under the first root port from the CPU through the first link is only an example, and in actual application, it can be adjusted according to actual conditions, and the present application is not limited.

[0086] In the method, the BUS number range under the first root port is queried through different links between the BMC and the CPU, which improves the efficiency of identifying the PCIE terminal device, and also improves the stability of obtaining the BUS number range under the first root port.

[0087] 404、traverse the PCIE devices in the BUS number range to obtain a first PCIE device;

[0088] After obtaining the BUS number range of the first root port, the BMC chip traverses the identity of the PCIE device in the bus number range, and according to the foregoing Figure 2 description, it can be understood that in the standard, the device parameter of each bus number can be any one of [0, 31], and the function parameter can be any one of [0, 7].

[0089] According to this condition, the bus number of the first root port is sequentially taken as SECBUS, SECBUS+1, SECBUS+2,..., SUBBUS, and device and function are traversed in turn.

[0090] If the bus, device, and function combination does not correspond to a PCIE device, an access failure prompt is received.

[0091] If the bus, device, and function combination corresponds to a PCIE device, the device is the first PCIE device.

[0092] It should be noted that the traversal of BUS, device, and function described herein is only an example and is not specifically limited in actual application.

[0093] 405. Obtain the base class of the first PCIE device, and determine whether the first PCIE device is a terminal device according to the base class.

[0094] The BMC chip obtains the base class from the register offset address 0BH of the first PCIE device, and if the value of the base class is not 06h, the first PCIE device is considered to be a terminal device.

[0095] If the value of the base class is 06h, the first PCIE device is considered to be a switch.

[0096] In this method, the base class of the first PCIE device is used to determine whether the first PCIE device is a terminal device, which improves the efficiency of identifying whether the first PCIE device is a terminal device.

[0097] 406. The BMC chip determines whether there is a PCIE terminal device electrically connected to the first root port.

[0098] After the BMC chip completes the traversal of the bus number corresponding to the first root port, it is determined whether there is a PCIE terminal device electrically connected to the first root port.

[0099] If the PCIE terminal device exists, step 407 is performed.

[0100] If the PCIE terminal device does not exist, step 409 is performed.

[0101] 407. Obtain the first identification of the PCIE terminal device from the first PCIE terminal device.

[0102] If the terminal device connected with the root port exists, the vendor ID, the device ID, the subsystem vendor ID and the subsystem ID, i.e. the first identification, are obtained from the registers of the terminal device with offsets of 0H, 2H, 2CH and 2EH respectively.

[0103] It should be noted that the first identification herein is only an example, and in actual applications, it can be configured according to needs, which is not limited herein.

[0104] In the method, the vendor ID, the device ID, the subsystem vendor ID and the subsystem ID set by the vendor for different batches of PCIE devices can be used. The work of pre-setting the first identification by the user is saved, and the work efficiency is improved.

[0105] 408. According to the first identification, find the PCIE configuration file corresponding to the first identification in the BMC firmware.

[0106] Herein, taking the first PCIE device as the terminal device as an example, after the first identification is obtained, the first identification is found in the BMC firmware, and according to the mapping relationship between the first identification and the first PCIE configuration file, the PCIE configuration file of the first PCIE device is obtained.

[0107] The first PCIE configuration file is information provided by the user through the interface of the BMC through the interactive interface and saved in the BMC firmware, and specifically can include at least one or more of the asset information of the first PCIE device specified in the PCIE device specification, the I2C topology and device address on the first PCIE device and the speed regulation strategy of the first PCIE device.

[0108] It should be noted that the example of the PCIE configuration file here is only illustrative, and is intended to explain that, in the PCIE configuration file mentioned in the present application, in addition to the asset information of the PCIE device specified in the PCIE device specification, information configured by the user according to the needs can also be included as the content of the first configuration file for the BMC to access. In actual application, the specific content of the PCIE configuration file is not limited by the present application.

[0109] In the method, the first configuration file is obtained from the BMC firmware by using the first identifier. In addition to the asset information of the first PCIE device specified in the PCIE device specification, the first configuration file can also include the I2C topology and device address on the first PCIE device and the speed regulation strategy of the first PCIE device, which improves the convenience of the BMC chip in obtaining the first configuration file and improves the working efficiency of the computing device.

[0110] For example, when the first PCIE device is updated or the first configuration file is updated, the BMC developer determines the first configuration file according to the first identifier and modifies the first configuration file to obtain an updated first configuration file, or replaces the existing first PCIE configuration file with a new first configuration file with the same name to obtain an updated first configuration file, thereby achieving the purpose of configuring the PCIE configuration file, and generating a new BMC firmware according to the updated first configuration file. The user updates the new BMC firmware into the BMC through the web interface provided by the BMC, the redfish interface or the interactive interface provided by the SNMP, and upgrades the BMC firmware.

[0111] It should be noted that the updating method of the first configuration file here is only an example, and in actual application, different means can be used to update the first configuration file according to the actual situation, which is not limited here.

[0112] In the method, the BMC chip acquires the first configuration file from the BMC firmware by using the first identifier. Compared with the current method of acquiring the configuration file from the BIOS, the BMC firmware upgrade does not need to scan the hardware device to acquire the configuration file corresponding to the PCIE device, and thus does not need to interrupt the service to scan the PCIE device when the PCIE device is updated. The convenience of the BMC firmware upgrade avoids the interruption of the service due to the upgrade of the PCIE terminal device, improves the stability of the work of the computing device, and further improves the stability of the work of the computing device. In addition, in the method of acquiring the configuration file from the BIOS, only the asset information of the PCIE device specified in the PCIE device specification can be acquired from the PCIE device by using the BIOS. In the method of updating the configuration file by using the BMC firmware upgrade, any content other than the asset information of the PCIE device specified in the PCIE device specification can be configured for the PCIE device as the configuration file according to the user demand.

[0113] 409、generating PCIE device exception information.

[0114] If the PCIE terminal device under the first root port is not traversed, the exception information of the case that the first root port is physically connected with the first PCIE terminal device, but the first PCIE terminal device is not found in the traversal is generated, and the first root port is marked as not having any associated terminal, so as to be checked by the user.

[0115] And the terminal device exception of the first root port is pushed through the interactive interface to prompt the user to check.

[0116] Or, a bell is rung to alert the user that the terminal device exception of the root port occurs.

[0117] It should be noted that the operation behavior of the terminal device not existing the electrical connection with the first root port is not limited here, and in actual application, when the terminal device not existing the electrical connection with the first root port exists, the user is reminded and / or backed up to be checked by the user.

[0118] Compared with the current technical means, the method can distinguish the case that the first root port is not connected with the PCIE terminal device and the case that the first root port is connected with the PCIE terminal device but the PCIE terminal device cannot be recognized. In addition, after learning that the terminal device of the first root port is abnormal, the user can be reminded in different ways, and the efficiency of the computing device in managing the PCIE terminal device is improved.

[0119] In the embodiment of the application, the mapping relationship between the PCIE slot and the CPU root port and the configuration file of the PCIE device are saved in the BMC firmware. When the BMC firmware detects that the first PCIE slot has a PCIE device in place, the first root port is found through the mapping relationship between the first PCIE slot and the first root port saved in the BMC firmware, and the SECBUS and SUBBUS information of the first root port is queried. According to the SECBUS and SUBBUS interval of the first root port and all possible values of device and function, it is determined whether the identity composed of bus, device and function exists corresponding PCIE device. If it exists, the base class is obtained to know that the PCIE device is a terminal device or a switch. The embodiment of the application does not need to traverse all root ports of the CPU, greatly reduces the calculation amount, and improves the efficiency of identifying the PCIE terminal device.

[0120] The following will be described in combination with Figure 5 A possible structure of the computing device proposed in the application is introduced, Figure 5 Another structure diagram of the computing device provided in the embodiment of the application is provided.

[0121] The computing device comprises:

[0122] The PCIE device in place detection module 501 is configured to acquire first in-place information, the first in-place information indicating that the first PCIE slot is physically connected with a first PCIE terminal device;

[0123] The root port information acquisition module 502 is configured to acquire first PCIE slot information based on the first in-place information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port;

[0124] The root port information acquisition module 502 is further configured to query a BUS number range under the first root port based on the determined first root port.

[0125] The PCIE device judgment module 503 is configured to traverse PCIE devices in the BUS number range to identify all PCIE terminal devices in the BUS number range.

[0126] Optionally, the first PCIE slot information includes a first mapping relationship, and the first mapping relationship is a mapping relationship between the first PCIE slot and the first root port.

[0127] The first mapping relationship is stored in firmware of the BMC.

[0128] Optionally, the root port information acquisition module 502 is specifically configured to send a first instruction to a CPU to query a BUS number range under the first root port.

[0129] Optionally, the first instruction is CPU PCI Configuration Read.

[0130] Optionally, the first instruction is RdPCIConfigLocal.

[0131] Optionally, the PCIE device in-place detection module 501 is specifically configured to acquire first in-place information in any one or more of the following manners:

[0132] The first in-place information is acquired through a link connected between a GPIO interface and a PCIE slot.

[0133] The first in-place information is acquired through a link connected between an extension chip and a PCIE slot.

[0134] The first in-place information is acquired through a link connected between a CPLD and a PCIE slot.

[0135] Optionally, the PCIE device judgment module 503 is specifically configured to:

[0136] Traverse PCIE devices in the BUS number range to obtain a first PCIE device, and the first PCIE device is any PCIE device in the BUS number range.

[0137] Obtain a base class of the first PCIE device, and if the base class is a preset value, the first PCIE device is a terminal device.

[0138] Optionally, the computing device further comprises a PCIE device exception processing module 504 configured to generate PCIE device exception information if there is no terminal device in the PCIE device within the BUS number range.

[0139] Optionally, the PCIE device configuration file matching module 505 is configured to:

[0140] obtain a first identifier of the PCIE terminal device from the first PCIE terminal device;

[0141] search for a PCIE configuration file corresponding to the first identifier in a BMC firmware according to the first identifier;

[0142] manage the first PCIE terminal device according to the PCIE configuration file.

[0143] Optionally, the first identifier comprises a Vender ID, a Device ID, a Subsystem Vendor ID and a Subsystem ID.

[0144] Optionally, the PCIE configuration file comprises at least one or more of asset information of the PCIE terminal device, an I2C topology and device address on the PCIE terminal device, and a speed regulation strategy of the PCIE terminal device.

[0145] Embodiments of the present application further provide a computer readable storage medium comprising computer readable instructions, which, when executed on a computer, cause the computer to perform any of the implementation manners of the foregoing method embodiments.

[0146] Embodiments of the present application further provide a computer program product comprising computer programs or instructions, which, when executed on a computer, cause the computer to perform any of the implementation manners of the foregoing method embodiments.

[0147] The present application further provides a chip or a chip system. The chip can comprise a processor. The chip can further comprise a memory (or a storage module) and / or a transceiver (or a communication module), or the chip is coupled with the memory (or the storage module) and / or the transceiver (or the communication module). The transceiver (or the communication module) can be used to support wired and / or wireless communication of the chip, and the memory (or the storage module) can be used to store a program or a set of instructions. The processor invoking the program or the set of instructions can be used to implement the operations performed by the terminal or the network device in the method embodiments, any of the possible implementation manners of the method embodiments. The chip system can comprise the above chip, or can comprise the above chip and other discrete devices, such as the memory (or the storage module) and / or the transceiver (or the communication module).

[0148] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0149] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic, and the division of the units is merely a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0150] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0151] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of a software functional unit.

[0152] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that makes a contribution to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program codes that can be stored in the medium.

Claims

1. A method for identifying a PCIE end device for a BMC, characterized in that, The method comprises the following steps: obtaining first in-place information, the first in-place information indicating that a first PCIE slot is physically connected with a first PCIE terminal device; based on the first in-place information, obtaining first PCIE slot information, the first PCIE slot information indicating that the first PCIE slot corresponds to a first root port; based on the determined first root port, querying a BUS number range hung by the first root port; traversing PCIE devices in the BUS number range to obtain a first PCIE device, the first PCIE device being any PCIE device in the BUS number range; obtaining a base class of the first PCIE device, if the base class is a preset value, the first PCIE device is a terminal device.

2. The method of claim 1, wherein, The first PCIE slot information comprises a first mapping relationship, the first mapping relationship being a mapping relationship between the first PCIE slot and the first root port. The first mapping relationship is saved in firmware of a BMC.

3. The method of claim 1, wherein, The querying of the BUS number range hung by the first root port comprises: sending a first instruction to a CPU to query the BUS number range hung by the first root port.

4. The method of claim 2, wherein, The querying of the BUS number range hung by the first root port comprises: sending a first instruction to a CPU to query the BUS number range hung by the first root port.

5. The method of claim 3, wherein, The first instruction is CPU PCI ConfigurationRead.

6. The method of claim 4, wherein, The first instruction is CPU PCI ConfigurationRead.

7. The method of claim 3, wherein, The first instruction is RdPCIConfigLocal.

8. The method of claim 4, wherein, The first instruction is RdPCIConfigLocal.

9. The method of claim 1, wherein, The obtaining of the first in-place information comprises any one or more of the following manners: the BMC obtains the first in-place information through a link between a GPIO interface and a PCIE slot; the BMC obtains the first in-place information through a link between an extension chip and a PCIE slot; the BMC obtains the first in-place information through a link between a CPLD and a PCIE slot.

10. The method according to any one of claims 1 to 9, characterized in that, The method further comprises: if there is no terminal device in the PCIE devices in the BUS number range, generating PCIE device exception information.

11. The method according to any one of claims 1 to 9, characterized in that, The method further comprises: obtaining a first identifier of the PCIE terminal device from the first PCIE terminal device; according to the first identifier, searching for a PCIE configuration file corresponding to the first identifier in firmware of a BMC; managing the first PCIE terminal device according to the PCIE configuration file.

12. The method of claim 11, wherein, The first identifier comprises a Vender ID, a DeviceID, a Subsystem Vendor ID and a Subsystem ID.

13. The method of claim 12, wherein, The PCIE configuration file includes at least one or more of asset information of the PCIE terminal device, I2C topology and device address on the PCIE terminal device, and speed regulation strategy of the PCIE terminal device.

14. A computing device, comprising: Comprise: A circuit board, wherein the circuit board is provided with a CPU, a BMC chip and at least one PCIE slot; The CPU is electrically connected with the at least one PCIE slot and is used for processing instructions; The BMC chip is electrically connected with the CPU through a first link and is electrically connected with the at least one PCIE slot through a second link, the BMC chip is used for acquiring first in-place information through the second link, the first in-place information indicates that a first PCIE device is physically connected with a first PCIE slot, and the first PCIE slot is any one of the at least one PCIE slot; The BMC chip acquires first PCIE slot information through the first link based on the first in-place information, the first PCIE slot information indicates that the first PCIE slot corresponds to a first root port; The BMC chip queries a BUS number range hung under the first root port from the CPU; PCIE devices in the BUS number range are traversed to obtain a first PCIE device, and the first PCIE device is any one of the PCIE devices in the BUS number range; A base class of the first PCIE device is acquired, and if the base class is a preset value, the first PCIE device is a terminal device.

15. The computing device of claim 14, wherein, The first link includes an SMLINK bus between the BMC and the CPU or a PECI link between the BMC and the CPU.

16. The computing device of claim 14 or 15, wherein, The second link includes any one or more of a link between the BMC and the PCIE slot through a GPIO, a link between the BMC and the PCIE slot through an I2C bus and a PCA9555, and a link between the BMC and the PCIE slot through a LOCALBUS bus and a CPLD.

17. A computing device, comprising: Comprise: A processor and a memory; The memory is used for storing computer execution instructions; The processor is used for executing the computer execution instructions stored in the memory, so that the electronic device executes the method in any one of claims 1 to 13.

18. A computer readable storage medium comprising a program which, when executed on a computer, causes the computer to perform the method of any one of claims 1 to 13.

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