Cloud service oriented performance and isolation customized hardware virtualization method and device

Abstract

The present application relates to the field of cloud computing, in particular to a kind of performance and isolation customized hardware virtualization method and device for cloud service.The present application selects to use FPGA for virtualization, simultaneously selects PCIe bus in succession on the selection of equipment to carry out the communication interaction of hardware, uses general interface chip as PCIe interface controller, the reconfigurable module on FPGA board is redesigned, based on dynamic reconfigurable technology for the module on FPGA, a new method is used to virtualize FPGA hardware resources, reconstruct its function, and does not waste additional resources and will not make data center become bloated and complicated, and meets the high performance requirement of cloud service while guaranteeing the isolation between each hardware, achieves the purpose of improving resource management efficiency.

Description

Technical Field

[0001] The present invention relates to the field of cloud computing, and in particular to a method and device for customizing hardware virtualization for cloud service performance and isolation. Background Art

[0002] With the continuous development of internet technology, cloud services have become a new model, penetrating into various industries. Their utilization is becoming increasingly widespread, and they are receiving widespread attention and recognition. Cloud service application scenarios have three distinct characteristics: multiple users, high concurrency, and dynamic loads. These three characteristics present two pressing challenges for cloud service data centers. On the one hand, current data centers suffer from spatial and temporal imbalances. On the other hand, the high development costs and poor usability of heterogeneous platforms limit the potential number of users. As heterogeneous hardware platforms (such as GPUs, FPGAs, and ASICs) are increasingly deployed in cloud service data centers, while they offer higher performance and energy efficiency than general-purpose processors (such as CPUs), their high development difficulty and cost have deterred cloud application developers.

[0003] To address the aforementioned challenges, virtualization, a fundamental technology, was introduced into the cloud service sector. Virtualization is essentially a resource optimization and management technology that first abstracts the various physical resources of a computer (such as CPU, memory, disk, I / O devices, etc.), and then converts the abstracted resources into one or more computer configuration environments that can be arbitrarily divided and integrated. Therefore, the core of virtualization technology lies in breaking the physical boundary structure of computer entities, allowing users to use virtual resources that are not constrained by geography or physical architecture, thereby optimizing tasks such as computing processing or information storage with better resource management. Virtualization technology was first applied to general-purpose CPU processors, and in recent years has gradually expanded to heterogeneous hardware platforms such as GPUs, FPGAs (Field Programmable Gate Arrays), and ASICs.

[0004] Existing technologies have shown that hardware virtualization can improve hardware resource utilization by 18% to 53%. Furthermore, hardware virtualization can reduce the total cost of ownership (TCO) for CPU and GPU data centers by up to 31% and 80%, respectively, with significant room for improvement. However, FPGAs, as reconfigurable computing resources, are incompatible with existing virtualization frameworks. Unlike GPUs (graphics processing units) and CPUs (central processing units), FPGA usage scenarios tend to be specialized. Different users may use different access interfaces, making it difficult to maintain a unified instruction set. Furthermore, even with a unified interface specification, user switching requires time-consuming re-flashing and complex state preservation, resulting in significant system time and space overhead. Currently, FPGA devices are tightly coupled with their respective development ecosystems (toolchains, libraries, etc.). Specific FPGA models require specialized software support to generate binary files for flashing, and there is no unified binary interface specification.

[0005] Currently, the method of providing partial reconfigurable areas between multiple FPGAs as cloud computing resources requires a large amount of additional resources to provide reconfigurable areas when the number of FPGAs is extremely large, and this method is difficult to manage. Integrating FPGAs into data centers is relatively complex and cumbersome, and can easily make data centers quite bloated. At the same time, the high development difficulty and cost deviate from the original intention of cloud services to pursue efficiency.

[0006] Therefore, the prior art still has defects and needs further development. Summary of the Invention

[0007] The embodiments of the present invention provide a method and apparatus for customizing hardware virtualization for cloud service performance and isolation, so as to at least solve the technical problem that existing cloud computing resource data centers are bloated and complex, resulting in low resource management efficiency.

[0008] According to an embodiment of the present invention, a method for customizing hardware virtualization for cloud service performance and isolation is provided, comprising the following steps:

[0009] Select virtualized hardware objects and determine the communication method required for inter-hardware communication; among them, select FPGA as the hardware object, choose to use the PCIe bus for interaction between hardware devices, and set up a PCIe interface controller to interconnect the PCIe bus with the input data terminal of the FPGA;

[0010] Complete the design of the related interfaces during the PCIe bus and FPGA data transmission process; connect the various hardware components and design the PCIe interface timing circuit and timing controller interface timing circuit;

[0011] FPGA virtualization based on dynamic reconfigurable technology.

[0012] Optionally, a virtualized hardware object is selected and a communication method required for communication between the hardware is determined. Specifically, an FPGA is selected as the hardware object, a PCIe bus is selected for interaction between hardware devices, and a PCIe interface controller is set. The PCIe bus is interconnected with the input data terminal of the FPGA as follows:

[0013] First, select the hardware object; among them, select FPGA as the hardware virtualization material;

[0014] Choose to use the PCIe bus for interaction between selected hardware devices;

[0015] Design a PCIe interface controller; among them, choose to use a universal interface chip as the implementation of the PCIe interface controller;

[0016] Interconnect the PCIe bus with the input data port of the FPGA.

[0017] Optionally, after selecting to use the PCIe bus for interaction between selected hardware devices, the following steps are also included:

[0018] Use FPGA or CPLD for functional design and code writing to implement the PCIe interface controller.

[0019] Optionally, complete the design of the relevant interfaces during the PCIe bus and FPGA data transmission process; in which, connect the various hardware components and design the PCIe interface timing circuit and timing controller interface timing circuit specifically as follows:

[0020] Connect the various hardware components, including the PCIe bus, universal interface chip, timing controller, and FPGA.

[0021] Design PCIe interface timing circuit;

[0022] Design the timing controller interface timing circuit.

[0023] Optionally, the timing controller interface timing circuit is designed as follows:

[0024] A configuration command register and a configuration status register are set in the timing controller. The configuration command register is used to receive the startup configuration command issued by the host, and the configuration status register is used to store the current status of the configuration process.

[0025] Optionally, the timing controller control flow is as follows:

[0026] The host sends a command to the universal interface chip to start accessing the PCIe bus, and the timing controller starts data configuration;

[0027] The state machine in the select map control program of the timing controller continuously detects the value in the configuration command status register in the idle state. When it receives the start configuration command from the host, the state machine starts the configuration timing.

[0028] When the Select Map control program of the timing controller sets PROG_B to 0 and keeps it for a preset time, it detects INIT_B. If INIT_B is high, it means that the FPGA configuration register is cleared. At this time, CS_B is set to 0, RDWR_B is set to 0, and the configuration status register is updated to notify the host that it can start downloading data.

[0029] The host cyclically detects the value of the configuration status register of the timing controller to determine when to start downloading configuration data. When data downloading can begin, the host reads the configuration file of a local area of ​​the FPGA and sends it to the PCIe bus.

[0030] The timing controller receives configuration data from the universal interface chip, then makes timing adjustments and loads the data into the corresponding area inside the FPGA using the SlaveSelect Map timing. At the same time, the control program in the timing controller detects the INIT_B and DONE signals. If the DONE signal is high, it indicates that the FPGA configuration is successful. At this time, the configuration status register can be updated and an interrupt signal can be sent to the host. If the INIT_B signal is low, it indicates that the CRC check has failed. At this time, the configuration status register must also be updated and an interrupt signal must be sent to the host. Otherwise, the CPLD will continue to receive data from the PCI9054 and send it to the FPGA.

[0031] Optionally, after completing the design of the relevant interfaces during the PCIe bus and FPGA data transmission process, the steps of connecting the hardware and designing the PCIe interface timing circuit and the timing controller interface timing circuit may also include:

[0032] FPGA is virtualized based on reconfigurable module combination; wherein, the reconfigurable module combination includes dynamic reconfigurable technology and reconfigurable engineering technology.

[0033] A performance and isolation-customized hardware virtualization device for cloud services, comprising:

[0034] The object selection module is used to select the virtualized hardware object and determine the communication method required for communication between the hardware. Among them, the FPGA is selected as the hardware object, the PCIe bus is selected to interact with the hardware devices, and the PCIe interface controller is set to interconnect the PCIe bus with the input data terminal of the FPGA.

[0035] The interface design module is used to complete the design of related interfaces in the PCIe bus and FPGA data transmission process; it connects various hardware and designs the PCIe interface timing circuit and the timing controller interface timing circuit;

[0036] The virtualization module virtualizes FPGA based on dynamic reconfigurable technology.

[0037] A computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in any of the above-mentioned performance and isolation customized hardware virtualization methods for cloud services.

[0038] A terminal device comprises: a processor, a memory and a communication bus; the memory stores a computer-readable program that can be executed by the processor;

[0039] The communication bus realizes the connection and communication between the processor and the memory;

[0040] When the processor executes the computer-readable program, the processor implements the steps of any one of the above-mentioned methods for customized hardware virtualization of performance and isolation for cloud services.

[0041] In the performance and isolation customized hardware virtualization method and device for cloud services in the embodiments of the present invention, the present invention chooses to use FPGA for virtualization. At the same time, in terms of equipment selection, the PCIe bus is selected for hardware communication interaction, and a universal interface chip is used as a PCIe interface controller. The reconfigurable module on the FPGA board is redesigned. Based on dynamic reconfigurable technology, a new method is used for virtualizing the FPGA hardware resources for the modules on the FPGA, and functionally reconstructing them. This does not waste extra resources and does not make the data center bloated and complicated. It meets the high performance requirements of cloud services while ensuring the isolation between each hardware, thereby achieving the purpose of improving resource management efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] Figure 1 A flowchart of the hardware virtualization method for customizing performance and isolation of cloud services according to the present invention;

[0044] Figure 2 A specific flow chart of an embodiment of the method for customizing hardware virtualization for performance and isolation of cloud services according to the present invention;

[0045] Figure 3 This is a schematic diagram of the hardware connections of the present invention;

[0046] Figure 4 This is the reconfigurable module workflow of the present invention;

[0047] Figure 5 A schematic diagram of a hardware virtualization device customized for performance and isolation of cloud services according to the present invention;

[0048] Figure 6 A diagram of a terminal device of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] Example 1

[0052] The purpose of this invention is to address the current situation where unified reception and management of hardware resources is difficult to achieve, and propose a performance and isolation customized hardware resource virtualization method for cloud services to abstract hardware resources in order to improve resource management efficiency.

[0053] See also Figures 1 to 3A performance and isolation customized hardware virtualization method for cloud services includes the following steps:

[0054] S100: Select a virtualized hardware object and determine the communication method required for communication between hardware; among them, select FPGA as the hardware object, choose to use the PCIe bus for interaction between hardware devices and set the PCIe interface controller to interconnect the PCIe bus with the input data terminal of the FPGA.

[0055] First, we need to determine the experimental subjects of this invention. Hardware virtualization technology was first applied to general-purpose CPU processors and gradually expanded to heterogeneous hardware platforms such as GPUs, FPGAs, and ASICs. Existing technologies can improve hardware resource utilization by 18% to 53%, and there is still considerable room for optimization. With the widespread deployment of FPGAs in cloud data centers (such as Alibaba Cloud F1 instances and AWS F1 instances), virtualization technology for cloud-based FPGAs has gradually become an important technology.

[0056] The present invention uses FPGA as the hardware object and determines the communication method required for communication between hardware. The once popular bus standards include ISA bus, EISA bus, and IBM's MCA bus. The PCIe bus provides many new features that are superior to other bus standards. Therefore, the present invention chooses to use the PCIe bus for communication and solves the problem of selecting a PCIe bus interface controller.

[0057] Step S100 specifically includes:

[0058] S101: First, a hardware object is selected; wherein, FPGA is selected as the hardware virtualization material.

[0059] First, we selected the experimental subjects. FPGAs are programmable devices developed from complex programmable logic devices (CPLDs). They address both the limitations of fully customized ASIC circuits, which lack programmability and versatility, and the limited gate count of existing programmable devices. They offer a good compromise between performance, power consumption, versatility, and development cycle. Therefore, we chose FPGAs as the material for hardware virtualization.

[0060] S102: Selecting to use the PCIe bus for interaction between selected hardware devices.

[0061] A bus is a common communication trunk line that transmits information between various computer components. It is a transmission line composed of wires. Compared with other buses, the PCIe bus offers advantages such as high performance, minimal access latency, and freedom from processor limitations. Therefore, this invention chooses to use the PCIe bus for communication between hardware devices.

[0062] S103: Design a PCIe interface controller; wherein, a universal interface chip is selected to implement the PCIe interface controller.

[0063] In step S102, the PCIe bus is selected for interaction between hardware devices, so a PCIe bus interface controller needs to be designed. First, an FPGA or CPLD can be used for functional design and code development; second, a universal interface chip can be used. The advantage of using a universal interface chip is that the design process can be independent of PCIe bus operations, focusing solely on the local bus interface. This simplifies the design process, saves time, and reduces the likelihood of errors. Therefore, the present invention uses a universal interface chip as the PCIe interface controller.

[0064] Regarding chip selection, PLX, one of the most mature interface chip design companies, offers several dedicated general-purpose PCIe bus controller chips. Therefore, this invention uses a general-purpose chip from PLX as the interface chip to implement the PCIe bus interface controller. The general-purpose chip's operating mode is also modified to adopt a non-multiplexed 32-bit mode to match the data bus of the SelectMAP configuration mode.

[0065] S104: interconnecting the PCIe bus and the input data terminal of the FPGA.

[0066] The PCIe bus is interconnected with the input data terminal of the FPGA. Considering that the timing of downloading data through the PCIe bus does not meet the synchronization requirements with the timing of loading into the target FPGA, the data is first imported into the output register of the local logic controller, and then the timing is adjusted to generate the timing synchronized with the FPGA. Then, the configuration data and the control signals generated by the controller are gradually imported into the FPGA according to the FPGA timing requirements.

[0067] S200: Complete the design of related interfaces in the PCIe bus and FPGA data transmission process; among them, connect the various hardwares and design the PCIe interface timing circuit and the timing controller interface timing circuit.

[0068] After the various devices involved in step S100 are connected to each other, the design issues related to the interface between the PCIe bus and the FPGA data transmission process need to be solved. Step S200 details the design and process of the PCIe interface timing circuit and the timing controller interface timing circuit design.

[0069] Step S200 is specifically as follows:

[0070] S201: Connecting various hardware components; wherein, the PCIe bus, universal interface chip, timing controller and FPGA are connected.

[0071] Hardware circuit link. Link the PCIe bus, universal interface chip, timing controller and FPGA together. The hardware link diagram is as follows: Figure 2 As shown, the arrows in each direction represent that the data flow between the interfaces is mutual, not unidirectional.

[0072] S202: Design a PCIe interface timing circuit.

[0073] First, the universal interface chip sets the LHOLD signal to active high, requesting access to the local bus. After receiving the access request from the universal interface chip, the timing controller sets the LHOLDA signal to active high, allowing the universal interface chip access to the local bus. The universal interface chip then prepares to transfer data on the local bus. Based on its internal register configuration, the universal interface chip maps the local address space to the PCIe memory space and initiates a write cycle on the local DMA bus, allowing data transfer to begin. When the ADS_B signal transitions low for one cycle, indicating that the address signal LA has become a valid address, the timing controller asserts the read / write signals LWR_B and READY_B, and the universal interface chip begins transferring data to the timing controller. When the BLAST_B signal transitions low, indicating that the data to be transmitted in the next cycle is valid data from the last cycle, subsequent data transmissions are invalid. The timing controller deasserts the enable signal READY# after one clock cycle. When the input signal READY_B deasserts, data transfer ceases, thus completing the transfer process.

[0074] S203: Design the timing controller interface timing circuit.

[0075] The present invention connects the select map port of the FPGA to the timing controller, and the FPGA configuration mode is Slave Select Map. The logic controller timing controller of the present invention adjusts the various types of data transmitted from the universal interface chip and sends them to the output port, and then loads the adjusted data into the FPGA according to the Slave Select Map timing. To facilitate the host control configuration process, a configuration command register and a configuration status register are set in the timing controller. The configuration command register is used to receive the startup configuration command issued by the host, and the configuration status register is used to store the current status of the configuration process. Control of the configuration process requires the host application and the timing controller control program to be completed in coordination.

[0076] The control flow of the timing controller is as follows:

[0077] Step 1: The host sends a command to the universal interface chip to start accessing the PCIe bus, and the timing controller starts data configuration.

[0078] Step 2: The state machine in the select map control program of the timing controller continuously detects the value in the configuration command status register in the idle state. When the start configuration command sent by the host is received, the state machine starts the configuration timing.

[0079] Step 3: When the Select Map control program of the timing controller sets PROG_B to 0 and maintains it for a period of time, it then detects INIT_B. If INIT_B is high, it indicates that the FPGA configuration register is cleared. At this time, CS_B is set to 0, RDWR_B is set to 0, and the configuration status register is updated to notify the host that it can start downloading data.

[0080] Step 4: The host cyclically checks the value of the timing controller configuration status register to determine when to start downloading configuration data. Once it knows that data downloading can begin, the host reads the configuration file from a local area of ​​the FPGA and sends it to the PCIe bus.

[0081] Step 5: The timing controller receives configuration data from the universal interface chip, performs timing adjustments, and loads the data into the corresponding area within the FPGA using the Slave Select Map timing. Simultaneously, the control program in the timing controller checks the INIT_B and DONE signals. If DONE is high, the FPGA configuration is successful. At this point, the configuration status register is updated and an interrupt is sent to the host. If INIT_B is low, a CRC check error occurs. Again, the configuration status register is updated and an interrupt is sent to the host. Otherwise, the CPLD continues to receive data from the PCI9054 and sends it to the FPGA.

[0082] S300: Virtualize FPGA based on dynamic reconfiguration technology.

[0083] Please refer to Figure 4 ,Dynamic reconfigurable technology is the basis of FPGA virtualization. ,In step S300, the design of the reconfigurable module is ,completed with the help of Xilinx’s Vivado software and its ,workflow is introduced.

[0084] Generally speaking, in a dedicated reconfigurable circuit, a reconfigurable module only needs to run a few services, and the sizes of the reconfigurable modules are usually different. This solution improves the utilization of FPGA resources, but reduces the flexibility of the entire reconfigurable project. On a general-purpose platform, it is usually necessary to divide resources into a series of small blocks that can run independently, and when more resources are needed, multiple resources are quickly aggregated. Reconfigurable module combination can increase the logic capacity and interface bandwidth of a single reconfigurable module, which has a significant impact on the flexibility of the FPGA system. Generally speaking, reconfigurable module combination can be achieved through two solutions: using a hierarchical structure to organize reconfigurable blocks or dynamically adjusting the size of reconfigurable blocks.

[0085] In a reconfigurable project organized hierarchically, reconfigurable modules are organized in a tree format below the top-level module. The implementation of lower-level modules depends on the upper-level modules. During implementation, each module is implemented sequentially, starting from the top-level module. When implementing a lower-level module, the upper-level module must be routed and the layout locked before it is implemented. This ensures that the implementation of the lower-level module does not affect the upper-level circuit, ensuring the correctness of the dependencies.

[0086] Dynamically adjusting a reconfigurable module only requires the area required for the reconfigurable module interface during module definition, and declares the area reserved for the reconfigurable module as a no-place-and-route region. During service circuit implementation, logic resources in the no-place-and-route region can be allocated to the reconfigurable module using TCL commands, achieving dynamic changes to the reconfigurable module.

[0087] In the embodiment, the FPGA may be virtualized by using dynamic reconfigurable technology or by using a reconfigurable module combination; wherein the reconfigurable module combination includes dynamic reconfigurable technology and reconfigurable engineering technology.

[0088] The present invention proposes to adopt a combination of two schemes to design a reconfigurable module combination, that is, while setting a prohibited layout and routing area, two adjacent reconfigurable modules are placed under one reconfigurable module for management, overcoming the problem of reduced feasible range of tree structure and the problem that the interface rate of the dynamic adjustment method cannot be improved, making the layout of the reconfigurable module more flexible.

[0089] In this invention, the PS (Programmable System) in the FPGA acts as a reconfigurable controller; the PS downloads the bitstream to the FPGA, and the AXI interface between the PS and the programmable logic part can be used to control the controller in the static part. Figure 3 shown.

[0090] The key point of this invention is that, unlike other hardware virtualization experimental subjects, this invention uses a relatively difficult FPGA for virtualization. Furthermore, the device selection prioritizes the PCIe bus for hardware communication and interaction, selects a universal interface chip from PLX as the PCIe interface controller, reconfigures the PCIe interface timing circuit and the timing controller interface timing circuit, and finally redesigns the reconfigurable modules on the FPGA board. This novel approach virtualizes and functionally reconfigures the FPGA hardware resources within the modules, without wasting resources or increasing the complexity of the data center. It also meets the high-performance requirements of cloud services while ensuring isolation between hardware components, ultimately improving resource management efficiency.

[0091] Example 2

[0092] See also Figure 5 According to another embodiment of the present invention, a performance and isolation customized hardware virtualization device for cloud services is provided, comprising:

[0093] The object selection module 100 is used to select a virtualized hardware object and determine the communication method required for communication between the hardware. Specifically, the FPGA is selected as the hardware object, the PCIe bus is selected to interact with the hardware devices, and a PCIe interface controller is set to interconnect the PCIe bus with the input data port of the FPGA.

[0094] The interface design module 200 is used to complete the design of the relevant interfaces in the PCIe bus and FPGA data transmission process; among them, it connects various hardware and designs the PCIe interface timing circuit and the timing controller interface timing circuit;

[0095] The virtualization module 300 virtualizes the FPGA based on the dynamic reconfigurable technology.

[0096] The present invention uses FPGA for virtualization and selects PCIe bus for hardware communication and interaction in equipment selection. A universal interface chip is used as the PCIe interface controller, and the reconfigurable module on the FPGA board is redesigned. Based on dynamic reconfiguration technology, a new method is used for the modules on the FPGA to virtualize the FPGA hardware resources and perform functional reconstruction. This method does not waste extra resources and does not make the data center bloated and complicated. It meets the high performance requirements of cloud services while ensuring the isolation between various hardware components, thereby achieving the purpose of improving resource management efficiency.

[0097] The key point of this invention is that, unlike other hardware virtualization experimental subjects, this invention uses a relatively difficult FPGA for virtualization. Furthermore, the device selection includes the PCIe bus for hardware communication and interaction, a universal interface chip from PLX as the PCIe interface controller, and the reconstruction of the PCIe interface timing circuit and the timing controller interface timing circuit. Finally, the reconfigurable modules on the FPGA board are redesigned. A novel method is used to virtualize the FPGA hardware resources and reconfigure their functionality.

[0098] Example 3

[0099] Based on the above-mentioned performance and isolation customized hardware virtualization method for cloud services, this embodiment provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement the steps in the performance and isolation customized hardware virtualization method for cloud services as in the above-mentioned embodiment.

[0100] Example 4

[0101] A terminal device includes: a processor, a memory, and a communication bus; the memory stores a computer-readable program that can be executed by the processor; the communication bus realizes connection and communication between the processor and the memory; when the processor executes the computer-readable program, it implements the steps of the above-mentioned performance and isolation customized hardware virtualization method for cloud services.

[0102] Based on the above-mentioned performance and isolation customized hardware virtualization method for cloud services, this application provides a terminal device, such as Figure 6 As shown, it includes at least one processor 20; a display screen 21; and a memory 22. It may also include a communications interface 23 and a bus 24. The processor 20, display screen 21, memory 22, and communications interface 23 can communicate with each other via bus 24. The display screen 21 is configured to display a preset user guidance interface in the initial setup mode. The communications interface 23 can transmit information. The processor 20 can call the logic instructions in the memory 22 to execute the method in the above embodiment.

[0103] In addition, the logic instructions in the memory 22 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0104] The memory 22, as a computer-readable storage medium, can be configured to store software programs or computer-executable programs, such as program instructions or modules corresponding to the methods in the embodiments of the present disclosure. The processor 20 executes the software programs, instructions, or modules stored in the memory 22 to perform functional applications and data processing, thereby implementing the methods in the above embodiments.

[0105] The memory 22 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data created based on the use of the terminal device. In addition, the memory 22 may include high-speed random access memory and non-volatile memory. For example, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, may also be transient storage media.

[0106] In addition, the specific process of loading and executing the multiple instructions in the storage medium and the processor in the terminal device has been described in detail in the above method and will not be described here one by one.

[0107] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A performance and isolation customized hardware virtualization method for cloud services, characterized by: The following steps are involved: Selecting a virtualized hardware object and determining a communication method to be used for inter-hardware communication; wherein, an FPGA is selected as the hardware object, a PCIe bus is selected to interact with the hardware devices, and a PCIe interface controller is set to interconnect the PCIe bus with an input data terminal of the FPGA; Complete the design of the PCIe bus and related interfaces during the FPGA data transmission process; connect the various hardware components, and design the PCIe interface timing circuit and the timing controller interface timing circuit; The FPGA is virtualized based on dynamic reconfigurable technology; wherein: The design of the related interfaces in the data transmission process of the PCIe bus and the FPGA is completed; wherein, the hardware is connected and the PCIe interface timing circuit and the timing controller interface timing circuit are designed specifically as follows: Connecting the various hardware components; wherein the PCIe bus, universal interface chip, timing controller and FPGA are connected; Design PCIe interface timing circuit; Design timing controller interface timing circuit; The design of the timing controller interface timing circuit is specifically as follows: A configuration command register and a configuration status register are set in the timing controller, the configuration command register is used to receive a startup configuration command issued by a host, and the configuration status register is used to store a current status of the configuration process; The control flow of the timing controller is as follows: The host issues an instruction to the universal interface chip to start accessing the PCIe bus, and the timing controller starts data configuration; The state machine in the Select Map control program of the timing controller continuously detects the value in the configuration command status register in an idle state, and starts the configuration timing after receiving the start configuration command sent by the host; When the Select Map control program of the timing controller sets PROG_B to 0 and keeps it for a preset time, it detects INIT_B. If INIT_B is high, it indicates that the configuration register of the FPGA has been cleared. At this time, CS_B is set to 0, RDWR_B is set to 0, and the configuration status register is updated to notify the host that it can start downloading data. The host cyclically detects the value of the configuration status register of the timing controller to determine when to start downloading configuration data; when data downloading can begin, the host reads the configuration file of a local area of ​​the FPGA and sends it to the PCIe bus; The timing controller receives configuration data from the universal interface chip, then performs timing adjustment and loads the data into the corresponding area inside the FPGA with the Slave Select Map timing. At the same time, the control program in the timing controller detects the INIT_B and DONE signals. If the DONE signal is high, it indicates that the FPGA configuration is successful. At this time, the configuration status register can be updated and an interrupt signal can be sent to the host. If the INIT_B signal is low, it indicates that the CRC check error occurs. At this time, the configuration status register must also be updated and an interrupt signal must be sent to the host. Otherwise, the CPLD will continue to receive data from PCI9054 and send it to the FPGA.

2. The performance and isolation customized hardware virtualization method for cloud services according to claim 1, characterized in that: The method of selecting a virtualized hardware object and determining a communication method required for communication between hardware devices includes selecting an FPGA as the hardware object, selecting a PCIe bus for interaction between hardware devices, and setting a PCIe interface controller to interconnect the PCIe bus with the input data terminal of the FPGA. Specifically, First, a hardware object is selected; wherein the FPGA is selected as the hardware virtualization material; Selecting to use the PCIe bus to interact with selected hardware devices; Design the PCIe interface controller; wherein, a universal interface chip is selected to implement the PCIe interface controller; The PCIe bus is interconnected with the input data terminal of the FPGA.

3. The performance and isolation customized hardware virtualization method for cloud services according to claim 2, characterized in that: After selecting the interaction between the hardware devices selected using the PCIe bus, the method further includes: The FPGA or CPLD is selected for functional design and code writing to implement the PCIe interface controller.

4. The performance and isolation customized hardware virtualization method for cloud services according to claim 1, characterized in that: After completing the design of the relevant interfaces in the PCIe bus and the FPGA data transmission process; wherein, after connecting the various hardware and designing the PCIe interface timing circuit and the timing controller interface timing circuit, it also includes: The FPGA is virtualized based on a reconfigurable module combination; wherein the reconfigurable module combination includes dynamic reconfigurable technology and reconfigurable engineering technology.

5. A performance and isolation customized hardware virtualization device for cloud services using the performance and isolation customized hardware virtualization method for cloud services according to claim 1, characterized in that: include: An object selection module is used to select a virtualized hardware object and determine the communication method required for communication between hardware devices; wherein, an FPGA is selected as the hardware object, a PCIe bus is selected to interact with the hardware devices, and a PCIe interface controller is set to interconnect the PCIe bus with the input data terminal of the FPGA; An interface design module is used to complete the design of the relevant interfaces in the PCIe bus and the FPGA data transmission process; wherein, the various hardware components are connected and the PCIe interface timing circuit and the timing controller interface timing circuit are designed; The virtualization module virtualizes the FPGA based on dynamic reconfigurable technology.

6. A computer-readable medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps in the performance and isolation customized hardware virtualization method for cloud services as described in any one of claims 1-4.

7. A terminal device, characterized in that: include: processor, memory, and communication bus; The memory stores a computer-readable program executable by the processor; The communication bus realizes the connection and communication between the processor and the memory; When the processor executes the computer-readable program, the processor implements the steps of the performance and isolation customized hardware virtualization method for cloud services as described in any one of claims 1 to 4.

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