Method for manufacturing semiconductor ultra-thin stacked structure

Abstract

A method for manufacturing a semiconductor ultra-thin stacked structure includes forming a stop layer structure in a semiconductor substrate by ion implantation, and then setting electrical components and an interconnect layer on the active surface of the semiconductor substrate to form a semiconductor wafer; the interconnect layers of two semiconductor wafers are opposite and joined together vertically; a portion of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer are removed from the back of the upper semiconductor wafer by back grinding and thinning processes, so that the upper semiconductor wafer forms a thinned semiconductor wafer, and then another semiconductor wafer is joined, back ground and thinned one by one on the thinned semiconductor wafer, and another thinned semiconductor wafer is stacked one by one, and finally the bottom semiconductor wafer is back ground and thinned. This manufacturing method can stack multiple layers of thinned semiconductor wafers to meet high integration requirements.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a semiconductor structure, and in particular to a method for manufacturing an ultra-thin semiconductor stacking structure. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually entering the research and development direction of multi-function and high performance. Semiconductor technology has been widely used in the manufacture of memory, central processing unit and other chipsets. In order to achieve high integration and high speed, the size of semiconductor integrated circuits continues to shrink. At present, a variety of different materials and technologies have been developed to achieve the above-mentioned integration and speed requirements. Stacked structures including multiple substrates have also been developed to improve the operating speed of the circuit. When the semiconductor planar packaging related technology reaches its limit, the demand for miniaturization can be met through integration. The technology of stacking wafers will greatly help future technology and has become a goal that needs to be improved in the current related fields. Summary of the invention

[0003] The invention provides a method for manufacturing a semiconductor ultra-thin stacking structure, so that the semiconductor ultra-thin stacking structure can meet the requirements of high integration and speed, and has better electrical characteristics and efficiency.

[0004] The manufacturing method of the semiconductor ultra-thin stacking structure provided by the present invention includes: manufacturing multiple semiconductor wafers, selecting one of the semiconductor wafers as the first semiconductor wafer of the bottom layer, and some of the semiconductor wafers as the second semiconductor wafer and the third semiconductor wafer to be stacked, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate with a relative active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is located between the stop layer structure and the active surface, and the second substrate part is located between the stop layer structure and the back surface, and the stop layer structure at least includes a silicon nitride layer. The manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high-temperature treatment process to form a silicon nitride layer in the nitrogen ion implanted area; and arranging multiple electrical components and an internal connection layer on the active surface, the internal connection layer includes multiple interconnection points, and arranging multiple conductive structures on the first substrate part to connect the internal connection layer and the stop layer structure. The second semiconductor wafer is flipped relative to the first semiconductor wafer so that the interconnect layer of the first semiconductor wafer and the interconnect layer of the second semiconductor wafer are opposite and bonded together using a hybrid bonding technology; a first back grinding process is performed to grind from the back side of the second semiconductor wafer to remove a portion of the second portion of the substrate of the second semiconductor wafer; a first thinning process is performed to form a thinned second semiconductor wafer; a second back grinding process is performed to grind from the back side of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and a second thinning process is performed to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step, wherein the substrate removal step removes the remaining second portion of the substrate to reveal the stop layer structure; and the stop layer removal step removes the stop layer structure to reveal the first portion of the substrate and the conductive structure.

[0005] In one embodiment of the present invention, before performing the above-mentioned second back grinding process, a plurality of thinned third semiconductor wafers may be stacked sequentially on the thinned second semiconductor wafer, wherein each stacking step of the thinned third semiconductor wafer includes: flipping the third semiconductor wafer relative to the first semiconductor wafer so that the interconnect layer of the third semiconductor wafer and the first portion of the substrate of the thinned second semiconductor wafer are opposite and bonded together; performing a third back grinding process to grind from the back side of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; and performing a third thinning process, including a substrate removal step and a stop layer removal step.

[0006] In one embodiment of the present invention, the stop layer structure further includes a silicon dioxide layer, and the silicon dioxide layer is disposed on the silicon nitride layer to be between the silicon nitride layer and the active surface.

[0007] In one embodiment of the present invention, the steps of forming the above-mentioned silicon dioxide layer include: after the nitrogen ion implantation process, firstly performing an oxygen ion implantation process at a second depth of the semiconductor substrate, wherein the second depth is smaller than the first depth, and then performing a high temperature treatment process to form a silicon dioxide layer in the oxygen ion implanted area.

[0008] In one embodiment of the present invention, the step of removing the stop layer includes: first removing the silicon nitride layer, and then removing the silicon dioxide layer.

[0009] In one embodiment of the present invention, the substrate removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity of silicon to silicon nitride is between 20 and 80.

[0010] In one embodiment of the present invention, the removal method of the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selectivity of silicon nitride to silicon dioxide is between 10 and 20, and the selectivity of silicon dioxide to silicon is about 5.

[0011] In one embodiment of the present invention, the distance between the stop layer structure and the active surface is between 1 micrometer and 5 micrometers, and the thickness of the thinned second semiconductor wafer is no more than 12 micrometers.

[0012] In one embodiment of the present invention, after forming the thinned first semiconductor wafer, the following steps are further included: disposing a plurality of solder balls on a side of the thinned first semiconductor wafer away from the thinned second semiconductor wafer to electrically connect the conductive structures respectively; and performing electrical testing and singulation.

[0013] The manufacturing method of the semiconductor ultra-thin stacking structure provided by the present invention includes manufacturing multiple semiconductor wafers, and the manufacturing steps of each semiconductor wafer include: providing a semiconductor substrate having a relative active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is located between the stop layer structure and the active surface, and the second substrate part is located between the stop layer structure and the back surface, the stop layer structure at least includes a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high-temperature treatment process to form a silicon nitride layer in the nitrogen ion implanted area; and arranging multiple electrical components and an internal connection layer on the active surface, the internal connection layer includes multiple interconnection points, and arranging multiple conductive structures on the first substrate part to connect the internal connection layer and the stop layer structure. One of the semiconductor wafers is selected as the first semiconductor wafer as the bottom layer, and part of the semiconductor wafer is singulated to form a first batch of semiconductor chips and at least one second batch of semiconductor chips to be stacked; the first batch of semiconductor chips is flipped relative to the first semiconductor wafer, so that the interconnection layer of the first batch of semiconductor chips and the interconnection layer of the first semiconductor wafer are opposite and bonded together by hybrid bonding technology; a first molding process is performed to form a first encapsulation colloid on the first semiconductor wafer to cover the first batch of semiconductor chips; a first back grinding process is performed to remove part of the first encapsulation colloid from a side of the first encapsulation colloid away from the first semiconductor wafer and A portion of the second portion of the substrate of the first batch of semiconductor chips is removed; a first thinning process is performed to form a first semiconductor chip layer; a second back grinding process is performed to grind from the back side of the first semiconductor wafer to remove a portion of the second portion of the substrate of the first semiconductor wafer; and a second thinning process is performed to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include a substrate removal step and a stop layer removal step, wherein the substrate removal step removes the remaining second portion of the substrate to reveal the stop layer structure, and the stop layer removal step removes the stop layer structure to reveal the first portion of the substrate and the conductive structure.

[0014] In one embodiment of the present invention, before performing the above-mentioned second back grinding process, at least one second semiconductor chip layer can be stacked sequentially on the first semiconductor chip layer, wherein the stacking step of each second semiconductor chip layer includes: flipping the second batch of semiconductor chips relative to the first semiconductor wafer so that the interconnect layer of the second batch of semiconductor chips and the first portion of the substrate of the first semiconductor chip layer are opposite and bonded together; performing a second molding process to form a second packaging colloid on the first semiconductor chip layer to cover the second batch of semiconductor chips; performing a third back grinding process to remove a portion of the second packaging colloid from a side of the second packaging colloid away from the first semiconductor chip layer and a portion of the second portion of the substrate of the second batch of semiconductor chips; and performing a third thinning process, including a substrate removal step and a stop layer removal step.

[0015] The manufacturing method of the semiconductor ultra-thin stacking structure provided by the present invention comprises: providing a carrier plate, and forming a plurality of first conductive pillars on the carrier plate. A plurality of semiconductor chips are provided, and the manufacturing steps of each semiconductor chip include: providing a semiconductor substrate having a relative active surface and a back surface; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate part and a second substrate part, wherein the first substrate part is located between the stop layer structure and the active surface, and the second substrate part is located between the stop layer structure and the back surface, and the stop layer structure at least includes a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high temperature treatment process to form a silicon nitride layer in the nitrogen ion implanted area; arranging a plurality of electrical components and an internal connection layer on the active surface, the internal connection layer includes a plurality of interconnection points, and arranging a plurality of conductive structures connecting the internal connection layer and the stop layer structure on the first substrate part; and performing singulation. A first batch of semiconductor chips and at least one second batch of semiconductor chips are selected from the semiconductor chips, the first batch of semiconductor chips includes a plurality of first semiconductor chips, and the second batch of semiconductor chips includes a plurality of second semiconductor chips. A first batch of semiconductor chips are flip-chip mounted on a carrier board, and a first conductive column is disposed between adjacent first semiconductor chips, wherein the interconnection layer of the first batch of semiconductor chips is adjacent to the carrier board and the semiconductor substrate is away from the carrier board. A first molding process is performed to form a first encapsulation colloid on the carrier board to cover the first batch of semiconductor chips and the first conductive column. A first back grinding process is performed to remove a portion of the first encapsulation colloid from the side of the first encapsulation colloid away from the carrier board and a portion of the second portion of the substrate of the first batch of semiconductor chips. A first thinning process is performed to form a first semiconductor chip layer, and the first thinning process includes sequentially removing the remaining second portion of the substrate of the first batch of semiconductor chips and the stop layer structure to expose the first portion of the substrate, the conductive structure and the first conductive column. A plurality of second conductive columns are disposed to electrically connect the partial conductive structure of the first semiconductor chip layer. A second batch of semiconductor chips are flip-chip mounted on the first semiconductor chip layer, wherein the second semiconductor chips are respectively connected across the adjacent first semiconductor chips, so that the interconnection layer of the second semiconductor chip is electrically connected to the exposed first conductive column and the partial conductive structure of the first semiconductor chip layer, and a portion of the second conductive column is disposed between the adjacent second semiconductor chips. A second molding process is performed to form a second encapsulation colloid on the first semiconductor chip layer to cover the second batch of semiconductor chips and the second conductive pillars. A second back grinding process is performed to remove a portion of the second encapsulation colloid from a side of the second encapsulation colloid away from the first semiconductor chip layer and a portion of the second portion of the substrate of the second batch of semiconductor chips. A second thinning process is performed to form a second semiconductor chip layer, the second thinning process includes sequentially removing the remaining second portion of the substrate of the second batch of semiconductor chips and the stop layer structure to expose the first portion of the substrate, the conductive structure and the second conductive pillars. The carrier is removed to expose the interconnect layer and the first conductive pillars of the first semiconductor chip layer.

[0016] In one embodiment of the present invention, after removing the above-mentioned carrier board, the following steps are further included: disposing a plurality of solder balls on a side of the first semiconductor chip layer away from the second semiconductor chip layer to electrically connect the interconnect layer and the first conductive pillar respectively; and performing singulation.

[0017] In an embodiment of the present invention, the first semiconductor chips of the first batch of semiconductor chips have different electrical functions.

[0018] In one embodiment of the present invention, the second semiconductor chips of the second batch of semiconductor chips have different electrical functions.

[0019] When manufacturing semiconductor wafers, the present invention first forms a stop layer structure in a semiconductor substrate by an ion implantation process, and then sets electrical components and an interconnect layer on the active surface of the semiconductor substrate; then, two semiconductor wafers are bonded up and down, or after the semiconductor wafer is singulated to form a plurality of semiconductor chips, the batch of semiconductor chips is combined with the bottom semiconductor wafer. After each semiconductor wafer / chip bonding (and molding packaging colloid) is performed, a portion of the semiconductor substrate and the stop layer structure of the upper semiconductor wafer / chip are removed from the back of the upper semiconductor wafer / chip by a back grinding and thinning process, so that the upper semiconductor wafer / chip forms a thinned semiconductor wafer / semiconductor chip layer, and then another semiconductor wafer / chip bonding (and molding packaging colloid), back grinding and thinning process are performed one by one on the thinned semiconductor wafer / chip, and another thinned semiconductor wafer / semiconductor chip layer is stacked upward, and finally the bottom semiconductor wafer is back ground and thinned. Since the thickness of each thinned semiconductor wafer / semiconductor chip layer is no more than 12 microns, under the limitation that the total chip thickness is 700 microns, 57 chip layers can be stacked to meet the requirements of high integration density and speed.

[0020] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1S FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing a semiconductor ultra-thin stacked structure according to a first embodiment of the present invention.

[0022] Figures 2A to 2K FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing a semiconductor ultra-thin stacked structure according to a second embodiment of the present invention.

[0023] FIG. 3A to FIG. 3LFIG. 4 is a cross-sectional schematic diagram of a method for manufacturing a semiconductor ultra-thin stacked structure according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0024] Figures 1A to 1S FIG. 1 is a cross-sectional view of a method for manufacturing a semiconductor ultra-thin stacked structure according to a first embodiment of the present invention. First, a plurality of semiconductor wafers 10 (indicated at Figure 1E ), select one of the semiconductor wafers 10 as the first semiconductor wafer 10a (indicated at Figure 1F ), the other semiconductor wafer 10 is used as the second semiconductor wafer 10b to be stacked (indicated at Figure 1F ) and the third semiconductor wafer 10c (indicated at Figure 1L ), the manufacturing processes of the plurality of semiconductor wafers 10 are the same or similar, Figures 1A to 1E FIG. 1 is a cross-sectional schematic diagram of manufacturing a semiconductor wafer 10. Figure 1A As shown, a semiconductor substrate 12 is provided. The semiconductor substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon on insulation (SOI) substrate. In one embodiment, the thickness of the semiconductor substrate is, for example, 700 to 800 microns (um), preferably 775 microns. The semiconductor substrate 12 has an active surface 121 and a back surface 122 that are opposite to each other.

[0025] Next, a stop layer structure is formed in the semiconductor substrate 12. In one embodiment, the manufacturing of the stop layer structure includes performing at least one ion implantation process and a high temperature treatment process. In one embodiment, the ion implantation process includes first performing nitrogen ion implantation and then performing oxygen ion implantation. Figure 1B and Figure 1C As shown, a nitrogen ion implantation process 14 is first performed at a first depth D1 of the semiconductor substrate 12, and then an oxygen ion implantation process 16 is performed at a second depth D2 of the semiconductor substrate 12. In one embodiment, the first depth D1 of the nitrogen ion implantation region 14' is a depth of, for example, about 1 to 5 microns from the active surface 121, and the second depth D2 of the oxygen ion implantation region 16' is smaller than the first depth D1 of the nitrogen ion implantation region 14, that is, the oxygen ion implantation region 16' is closer to the active surface 121.

[0026] Then high temperature treatment is performed, such as Figure 1D As shown, silicon nitride (Si 3 N 4) layer 14a, forming silicon dioxide (SiO 2 ) layer 16a, wherein the silicon dioxide layer 16a is closer to the active surface 121, and the silicon nitride layer 14a is closer to the back surface 122. In this embodiment, the silicon nitride layer 14a and the silicon dioxide layer 16a constitute the above-mentioned stop layer structure 18, wherein the silicon dioxide layer 16a is located on the silicon nitride layer 14 and between the silicon nitride layer 14a and the active surface 121. In one embodiment, the thickness of the silicon nitride layer 14a and the silicon dioxide layer 16a is, for example, 500 nanometers (nm). For the convenience of explanation, the semiconductor substrate 12 between the silicon dioxide layer 16a and the active surface 121 of the stop layer structure 18 is called the first substrate portion 123, and the semiconductor substrate 12 between the silicon nitride layer 14a and the back surface 122 of the stop layer structure 18 is called the second substrate portion 124. In one embodiment, when the semiconductor wafer 10 is subsequently used in the manufacture of a metal oxide semiconductor field effect transistor (MOSFET), in order to match the depth of a general N-type well (N well) of about 2 microns, the thickness of the first portion 123 of the substrate should be maintained at no less than 2 microns, that is, when performing the above-mentioned nitrogen ion implantation process 14 and oxygen ion implantation process 16, the first depth D1 of the nitrogen ion implantation region 14' and the second depth D1 of the oxygen ion implantation region 16' should both be slightly greater than 2 microns.

[0027] Continuing with the above description, if Figure 1E As shown, a plurality of electrical components 20 and an interconnection layer 22 having interconnection points 221 are disposed on the active surface 121, wherein the electrical components 20 include, for example, metal oxide semiconductors (MOS), and a plurality of conductive structures are disposed on the first portion 123 of the substrate. In one embodiment, the conductive structures include, for example, through silicon vias (TSVs) 24, wherein the TSVs 24 vertically connect the interconnection layer 22 and the silicon dioxide layer 16a of the stop layer structure 18. The manufacturing process of the electrical components 20, the interconnection layer 22, and the TSVs 24 includes the front-end-of-line (FEOL) and back-end-of-line (BEOL) of a general semiconductor process, wherein the front-end-of-line process includes, for example, making components such as resistors, capacitors, diodes, and transistors on the semiconductor substrate 12, and the back-end-of-line process includes, for example, making metal wiring and interconnection points 221 for connection between the components; in one embodiment, the interconnection points 221 are, for example, copper contacts. Figure 1EThe figure is a schematic diagram of a semiconductor wafer 10 according to an embodiment of the present invention. The first semiconductor wafer 10a, the second semiconductor wafer 10b and the third semiconductor wafer 10c described below use the same element symbols as those used in the description of the semiconductor wafer 10. The position of the through silicon via 24 of the first semiconductor wafer 10a corresponds to the installation position of the solder ball in the subsequent process, and the position of the through silicon via 24 of the second semiconductor wafer 10b corresponds to the interconnection point 221 of the interconnect layer 22 of the third semiconductor wafer 10c.

[0028] like Figure 1F As shown, the second semiconductor wafer 10b is flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the first semiconductor wafer 10a and the second semiconductor wafer 10b are opposite and the interconnection points 221 correspond to each other; then, a hybrid bonding technology is used, such as Figure 1G As shown, the first semiconductor wafer 10a and the second semiconductor wafer 10b are stacked up and down, wherein the hybrid bonding technology includes copper-to-copper bonding and tempering processes.

[0029] Next, a first backside grinding process is used to grind the backside 122 of the second semiconductor wafer 10b to remove a portion of the second substrate portion 124 of the second semiconductor wafer 10b. Figure 1H As shown, the remaining second portion 124 of the substrate has a very thin thickness. In one embodiment, the remaining second portion 124 of the substrate has a thickness of about 20.

[0030] Then, a first thinning process is performed to form a thinned second semiconductor wafer, wherein the first thinning process includes a substrate removal step and a stop layer removal step. Figures 1I to 1K The substrate removal step is used to remove the remaining second substrate portion 124, such as Fig. 1I As shown, the stop layer structure 18 is exposed, for example, the silicon nitride layer 14a is exposed. In one embodiment, the substrate removal step is a first chemical mechanical polishing (CMP) process, wherein the selectivity of silicon and silicon nitride is, for example, 20, that is, Si / Si 3 N 4 20; the stop layer removal step is used to remove the stop layer structure 18, that is, sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a to expose the first portion of the substrate 123 and the silicon through-hole 24; in one embodiment, the silicon nitride layer 14a is first removed by a second chemical mechanical polishing process, such as Figure 1J As shown, the silicon dioxide layer 16a is exposed, wherein the selection ratio of silicon nitride to silicon dioxide is, for example, 10, that is, Si 3 N 4 / SiO 210; and then removing the silicon dioxide layer 16a by a third chemical mechanical polishing process, such as Figure 1K As shown, the first portion 123 of the substrate and the silicon through hole 24 are exposed, wherein the selection ratio of silicon dioxide to silicon is, for example, 5, that is, SiO 2 / Si is 5. By exposing the first substrate portion 123 and the TSV 24 , a thinned second semiconductor wafer 10 b ′ is formed.

[0031] Continuing with the above description, the stacking of the first semiconductor wafer 10a and the thinned second semiconductor wafer 10b' has been completed; then, Figure 1L As shown, the third semiconductor wafer 10c is flipped relative to the first semiconductor wafer 10a, so that the interconnect layer 22 of the third semiconductor wafer 10c faces the first substrate portion 123 of the thinned second semiconductor wafer 10b'. In one embodiment, the interconnection points 221 of the interconnect layer 22 of the third semiconductor wafer 10c correspond to the through silicon vias 24 of the thinned second semiconductor wafer 10b'. Afterwards, the above-mentioned first back grinding process and the first thinning process are repeated to complete the stacking of the thinned third semiconductor wafer 10c' and the thinned second semiconductor wafer 10b'. In one embodiment, the thickness of the thinned second semiconductor wafer 10b' or the thinned third semiconductor wafer 10c' is, for example, 12 microns. In this way, under the premise of having a plurality of semiconductor wafers 10, the above-mentioned bonding process, the first back grinding process and the first thinning process of the semiconductor wafers 10 are repeated one by one to complete the stacking of the multi-layer thinned semiconductor wafers 10' and the first semiconductor wafer 10a, as shown in FIG. Figure 1M As shown, in one embodiment, as the thinned semiconductor wafer 10 ′ stacked on the top, the first substrate portion 123 thereof may not need to be formed with a TSV 24 .

[0032] After a predetermined number of thinned semiconductor wafers 10' are stacked, a second backside grinding process is used to grind the backside 122 of the first semiconductor wafer 10a. Figure 1N As shown, a portion of the second substrate portion 124 of the first semiconductor wafer 10a is removed, and a second substrate portion 124 with a very thin thickness remains; then, a second thinning process is performed, such as Figure 1O to Figure 1Q As shown, the above-mentioned substrate removal step and stop layer removal step are utilized to sequentially remove the remaining second substrate portion 124, silicon nitride layer 14a and silicon dioxide layer 16a of the first semiconductor wafer 10a, thereby exposing the first substrate portion 123 and silicon vias 24 of the thinned first semiconductor wafer 10a', thereby completing the stacking of multiple thinned semiconductor wafers 10' such as the thinned first semiconductor wafer 10a', the thinned second semiconductor wafer 10b', the thinned third semiconductor wafer 10c'...

[0033] Afterwards, if Figure 1RAs shown, a plurality of solder balls 26 are disposed on a side of the thinned first semiconductor wafer 10a' away from the thinned second semiconductor wafer 10b' to electrically connect the exposed silicon through-holes 24 respectively; and after performing chip probing (CP) to perform electrical function testing (Test), die sawing is performed to complete the following steps. Figure 1S The semiconductor ultra-thin stacking structure 28 shown, in which each layer of thinned semiconductor wafer 10' is cut into pieces as a semiconductor chip layer 10", since the thickness of each thinned semiconductor wafer 10' can be, for example, 12 microns, under the limitation that the total chip thickness is limited to 700 microns, the semiconductor ultra-thin stacking structure 28 of the embodiment of the present invention can be stacked up to 57 layers of thinned semiconductor chip layers 10", which can meet high integration and speed requirements and have better electrical characteristics and efficiency.

[0034] In the above-mentioned first thinning process and the second thinning process, the substrate removal step and the stop layer removal step include three chemical mechanical polishing processes as an example for explanation, but it is not limited to this. In another embodiment, the first / second thinning process includes a wet etching process and two chemical mechanical polishing processes, that is, in the substrate removal step, the wet etching process replaces the above-mentioned first chemical mechanical polishing process. The cross-sectional schematic diagram of the thinning process can still be referred to. Figures 1H to 1K or Figure 1N to Figure 1Q As shown, the remaining second portion 124 of the substrate is first removed by a wet etching process to expose the silicon nitride layer 14a. The selectivity of silicon and silicon nitride in the wet etching process is, for example, 40, that is, Si / Si 3 N 4 and then sequentially performing a second chemical mechanical polishing process and a third chemical mechanical polishing process to sequentially remove the silicon nitride layer 14a and the silicon dioxide layer 16a.

[0035] In another embodiment, the first / second thinning process may also be replaced by three plasma dry etching processes to replace the three chemical mechanical polishing processes. The cross-sectional schematic diagram of the thinning process can still be found in Figures 1H to 1K or Figure 1N to Figure 1Q As shown, the remaining second portion 124 of the substrate is first removed by a first plasma dry etching process to expose the silicon nitride layer 14a. In one embodiment, the selectivity of silicon and silicon nitride in the first plasma dry etching is, for example, 80, that is, Si / Si 3 N 4 Then, the silicon nitride layer 14a is removed by a second plasma dry etching process to expose the silicon dioxide layer 16a. In one embodiment, the selectivity of silicon nitride and silicon dioxide in the second plasma dry etching process is, for example, 20, ie, Si 3 N 4 / SiO 2Then, the silicon dioxide layer 16a is removed by a third plasma dry etching process to expose the first portion 123 of the substrate and the silicon through hole 24. In one embodiment, the selectivity of silicon dioxide and silicon in the third plasma dry etching process is, for example, 5, that is, SiO 2 / Si is 5.

[0036] In the first embodiment, the wafer is stacked on wafer (WoW), but the present invention is not limited thereto. Figures 2A to 2K FIG. 1 is a cross-sectional view of a method for manufacturing a semiconductor ultra-thin stacked structure according to a second embodiment of the present invention. In this second embodiment, a plurality of semiconductor wafers 10 are first provided, and the manufacturing steps thereof have been disclosed in the above Figures 1A to 1E Next, a portion of the semiconductor wafer 10 is selected as the first semiconductor wafer 10a (marked at Figure 2B ), another part of the semiconductor wafer 10 is subjected to electrical function test, and the die with good electrical function are selected for singulation, such as Figure 2A As shown, a plurality of semiconductor chips 30 are obtained, each semiconductor chip 30 still includes an electrical element 20, an interconnect layer 22 and a semiconductor substrate 12. A stop layer structure 18 is formed in the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first substrate portion 123 and a second substrate portion 124. The first substrate portion 123 is also formed with a through silicon via 24 to connect the stop layer structure 18 and the interconnect layer 22. For ease of explanation, the plurality of semiconductor chips 30 are divided into a first batch of semiconductor chips 30a and a second batch of semiconductor chips 30b according to the order of subsequent processes, and each batch includes a plurality of semiconductor chips 30.

[0037] like Figure 2B As shown, the first batch of semiconductor chips 30a are flipped relative to the first semiconductor wafer 10a, so that the interconnection layer 22 of the first batch of semiconductor chips 30a and the interconnection layer 22 of the first semiconductor wafer 10a are opposite and the interconnection points 221 correspond to each other; then, a hybrid bonding technology is used, such as Figure 2C As shown, the first semiconductor wafer 10 a and the first batch of semiconductor chips 30 a are bonded together top and bottom.

[0038] Next, a first molding process is performed, such as Figure 2D As shown, a first molding compound 32a is formed on the first semiconductor wafer 10a to cover the first batch of semiconductor chips 30a; then, a first back grinding process is used to remove a portion of the first molding compound 32a and a portion of the second substrate portion 124 of the first batch of semiconductor chips 30a from the side of the first molding compound 32a away from the first semiconductor wafer 10a, as shown in FIG. Figure 2EAs shown, the first batch of semiconductor chips 30 a have a second substrate portion 124 with a very thin thickness and a first encapsulant 32 a flush with the second substrate portion 124 .

[0039] Afterwards, a first thinning process is performed, including the substrate removal step and the stop layer removal step described in the first embodiment, so as to remove the remaining substrate second portion 124, the stop layer structure 18 and part of the encapsulation glue 32 of the first batch of semiconductor chips 30a. Figure 2F As shown, the substrate first portion 123 and the TSV 24 of the first batch of semiconductor chips 30 a are exposed, thereby forming a thinned first semiconductor chip layer 30 a ′, which is stacked on the first semiconductor wafer 10 a .

[0040] Next, the second batch of semiconductor chips 30b are still flipped relative to the first semiconductor wafer 10a, so that the interconnection layers 22 of the second batch of semiconductor chips 30b correspond to the first substrate portions 123 of the first semiconductor chip layer 30a', and the second batch of semiconductor chips 30b are bonded to the first semiconductor chip layer 30a'; a second molding process is performed to form a second encapsulation colloid 32b on the first semiconductor chip layer 30a' to cover the second batch of semiconductor chips 30b; a back grinding process and a thinning process are performed to remove a portion of the second encapsulation colloid 32b, the second substrate portion (not shown) of the second batch of semiconductor chips 30b, and a stop layer structure (not shown) from a side of the second encapsulation colloid 32b away from the first semiconductor chip layer 30a', as shown in FIG. Figure 2G As shown, the first substrate portion 123 and the silicon through-hole via 24 of the second batch of semiconductor chips 30b are exposed to form a thinned second semiconductor chip layer 30b'. In this way, the bonding process, molding process, back grinding process and first thinning process of the above batches of semiconductor chips 30 are repeated batch by batch, and the first semiconductor chip layer 30a' and the multi-layer second semiconductor chip layer 30b' can be stacked with the first semiconductor wafer 10a, as shown in FIG. Figure 2H As shown, in one embodiment, as the second semiconductor chip layer 30 b ′ stacked on the top, the first substrate portion 123 thereof may not need to be formed with a TSV 24 .

[0041] Next, similar to the first embodiment, after a predetermined number of second semiconductor chip layers 30b' are stacked, the second substrate portion 124 and the stop layer structure 18 of the first semiconductor wafer 10a are removed from the back side 122 of the first semiconductor wafer 10a in sequence by a second back grinding process and a second thinning process. Fig.2I As shown, the first substrate portion 123 and the TSV 24 are exposed, thereby completing the stacking of the thinned first semiconductor wafer 10 a ′ and the plurality of semiconductor chips 30 .

[0042] The first and second thinning processes include the substrate removal step and the stop layer removal step described in the first embodiment, wherein the process selection for the substrate removal step and the stop layer removal step, such as three chemical mechanical polishing processes, or a wet etching process combined with a chemical mechanical polishing process, or both plasma dry etching processes, and the selection ratio between materials such as silicon, silicon nitride and silicon dioxide have been described in the first embodiment and will not be repeated here.

[0043] Afterwards, if Figure 2J As shown, solder balls are set on the exposed TSVs 24 of the thinned first semiconductor wafer 10a', and after electrical function tests are performed, singulation is performed along the dicing lines 321 of the first encapsulant 32a and the second encapsulant 32b to complete the following steps: Figure 2K The semiconductor ultra-thin stacked structure 34 is shown. In this embodiment of the semiconductor ultra-thin stacked structure 34, since the stacked semiconductor chips 30 have been tested and selected for electrical functions, the yield of the semiconductor ultra-thin stacked structure 34 is higher.

[0044] FIG. 3A to FIG. 3L FIG. 2 is a cross-sectional view of a method for manufacturing a semiconductor ultra-thin stack structure according to a third embodiment of the present invention. In the third embodiment, first, a carrier plate 40 is provided, and a plurality of first conductive pillars 42 are formed on the carrier plate 40. Figure 3A As shown, the carrier plate 40 is, for example, glass with a thickness of 500 micrometers and a length of 301 millimeters (mm), and the first conductive pillar 42 is, for example, a copper pillar.

[0045] Next, a plurality of semiconductor chips 44 (indicated by Figure 3B ), the semiconductor chips 44 may have the same or different electrical functions, and the various semiconductor chips 44 are obtained by singulating the various semiconductor wafers 10, and the manufacturing steps of each semiconductor wafer 10 are disclosed in the above Figures 1A to 1E Each semiconductor chip 44 still includes an electrical element 20, an interconnect layer 22 and a semiconductor substrate 12. A stop layer structure 18 is formed in the semiconductor substrate 12. The stop layer structure 18 divides the semiconductor substrate 12 into a first substrate portion 123 and a second substrate portion 124. The first substrate portion 123 is also formed with a through silicon via 24 to connect the stop layer structure 18 and the interconnect layer 22. In one embodiment, the thickness of the semiconductor substrate 12 is, for example, 775 microns, and the thickness of the interconnect layer 22 is, for example, 10 microns.

[0046] The first batch of semiconductor chips selected are flip-chip bonded to the carrier board 40. Figure 3BAs shown, taking the first batch of semiconductor chips 44 including three first semiconductor chips 44a as an example, the three first semiconductor chips 44a may have the same or different electrical functions, and the first conductive column 42 is located between adjacent first semiconductor chips 44a. In one embodiment, when performing flip-chip bonding of the first semiconductor chips 44a, the bonding is performed in a flip-chip manner in which the interconnect layer 22 is adjacent to the carrier board 40 and the semiconductor substrate 12 is away from the carrier board 10.

[0047] Afterwards, a first molding process is performed, such as Figure 3C As shown in FIG. 1 , a first encapsulant 46a is formed on the carrier board 40 to cover the three first semiconductor chips 44a and the first conductive pillars 42. Next, a portion of the first encapsulant 46a, the second substrate portion 124 of the first semiconductor chip 44a, and the stop layer structure 18 are removed from the side of the first encapsulant 46a away from the carrier board 40 by the first back grinding process and the first thinning process. Figure 3D As shown, the first substrate portion 123 , the TSV 24 , and the first conductive pillar 44 are exposed, thereby forming a thinned first semiconductor chip layer 44 a ′.

[0048] Afterwards, the second conductive pillar 48 is disposed. The second conductive pillar 48 is, for example, vertically disposed on a portion of the TSV 24. Figure 3E As shown, at least one through silicon via 24 of each thinned first semiconductor chip 44a is provided with a second conductive pillar 48, and the second conductive pillar 48 is, for example, a copper pillar. Then, the selected second batch of semiconductor chips are flip-chip connected between two adjacent thinned first semiconductor chips 44a, as shown in FIG. Figure 3F As shown, taking the second batch of semiconductor chips including two second semiconductor chips 44b as an example, the two semiconductor chips 44b may have the same or different electrical functions. In one embodiment, the interconnect layer 22 of the second semiconductor chip 44b is opposite to the first portion 123 of the substrate of the first semiconductor chip layer 44a', the interconnection point 221 of the second semiconductor chip 44b is electrically connected to a portion of the silicon through-via 24 and the first conductive column 42, and a portion of the second conductive column 48 is located between adjacent second semiconductor chips 44b.

[0049] Next, a second molding process, a second back grinding process, and a second thinning process are sequentially performed to form a second encapsulant 46b on the first semiconductor chip layer 44a' to cover the second semiconductor chip 44b and the second conductive pillar 48, and then a second back grinding process and a second thinning process are performed to remove the second substrate portion 124 of the second semiconductor chip 44b, the stop structure layer 18, and a portion of the second encapsulant 46b. Figure 3G As shown, the first substrate portion 123 and the TSV 124 , as well as the second conductive pillar 48 are exposed, thereby forming a thinned second semiconductor chip layer 44 b ′.

[0050] In this way, the third conductive pillar 50 is disposed, the third semiconductor chip 44c is flip-chip disposed on the second semiconductor chip layer 44b', the encapsulation molding process, the back grinding process and the thinning process are repeatedly performed to complete the stacking of the third semiconductor chip layer 44c'. Figure 3H As shown, and successively more layers of semiconductor chip layers are stacked, such as Fig. 3I shown.

[0051] Afterwards, the carrier plate 40 is removed, as shown in FIG. Figure 3J As shown, the interconnect layer 22 and the first conductive pillar 42 of the first semiconductor chip layer are exposed, and solder balls 26 are set on the circuit contacts (not shown) preset in the interconnect layer 22 and the first conductive pillar. Figure 3K As shown, and cut into pieces to complete Figure 3L The semiconductor ultra-thin stack structure 52 is shown.

[0052] In the above-mentioned first / second / third embodiment of the manufacturing method of the semiconductor ultra-thin stacking structure, the manufacturing of the stop layer structure is explained by taking the example of successively performing nitrogen ion and oxygen ion implantation and performing high-temperature treatment to form a silicon nitride layer and a silicon dioxide layer, but is not limited to this. In one embodiment, the stop layer structure may only include a silicon nitride layer, that is, a high-temperature treatment process is performed after a nitrogen ion implantation process is performed in the semiconductor substrate, so as to form a silicon nitride layer at a depth of 1 to 5 microns from the active surface; correspondingly, the stop layer removal step of the subsequent first / second thinning process only needs to remove the silicon nitride layer, and other subsequent processes are the same and will not be repeated here.

[0053] In an embodiment of the present invention, by forming a stop layer structure at a depth of the semiconductor substrate, and gradually removing the substrate and the stop layer structure in the subsequent thinning process, the semiconductor substrate can be actually ground or etched until only the first portion of the substrate is retained, that is, only a substrate thickness of 1 to 5 microns is retained, so that the overall thickness of each semiconductor chip layer is not greater than 12 microns. Under the limitation that the total chip thickness is limited to 700 microns, the semiconductor ultra-thin stacking structure 28 of the embodiment of the present invention can stack more than 50 thinned semiconductor chip layers, which can meet high integration and speed requirements and have better electrical characteristics and efficiency.

[0054] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor ultra-thin stacked structure, It is characterized in that Include: A plurality of semiconductor wafers are manufactured, one of the semiconductor wafers is selected as a first semiconductor wafer as a bottom layer, and the other semiconductor wafers are selected as a second semiconductor wafer and at least a third semiconductor wafer to be stacked, and the manufacturing steps of each of the semiconductor wafers include: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface, and the stop layer structure at least includes a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high temperature treatment process, so that the silicon nitride layer is formed in the nitrogen ion implanted region; and disposing a plurality of electrical components and an interconnect layer on the active surface, wherein the interconnect layer comprises a plurality of interconnection points, and disposing a plurality of conductive structures on the first portion of the substrate to connect the interconnect layer and the stop layer structure; Flipping the second semiconductor wafer relative to the first semiconductor wafer so that the interconnect layer of the first semiconductor wafer and the interconnect layer of the second semiconductor wafer are opposite to each other and bonded together using a hybrid bonding technology; Performing a first backside grinding process to grind from the backside of the second semiconductor wafer to remove a portion of the second substrate portion of the second semiconductor wafer; Performing a first thinning process to form a thinned second semiconductor wafer; Performing a second backside grinding process to grind from the backside of the first semiconductor wafer to remove a portion of the second substrate portion of the first semiconductor wafer; as well as A second thinning process is performed to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include: a substrate removal step to remove the remaining second portion of the substrate to reveal the stop layer structure; and a stop layer removal step to remove the stop layer structure to reveal the first portion of the substrate and the conductive structures.

2. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1, It is characterized in that Before performing the second backside grinding process, a plurality of thinned third semiconductor wafers may be stacked sequentially on the thinned second semiconductor wafer, wherein each stacking step of the thinned third semiconductor wafers includes: Flipping the third semiconductor wafer relative to the first semiconductor wafer so that the interconnect layer of the third semiconductor wafer and the first portion of the substrate of the thinned second semiconductor wafer are opposite to and bonded together; Performing a third backside grinding process to grind from the backside of the third semiconductor wafer to remove a portion of the second portion of the substrate of the third semiconductor wafer; as well as A third thinning process is performed, including the substrate removal step and the stop layer removal step.

3. The method for manufacturing the semiconductor ultra-thin stacked structure according to claim 1, It is characterized in that The stop layer structure further comprises a silicon dioxide layer, which is disposed on the silicon nitride layer to be between the silicon nitride layer and the active surface.

4. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 3, It is characterized in that The step of forming the silicon dioxide layer includes: after the nitrogen ion implantation process, firstly performing an oxygen ion implantation process at a second depth of the semiconductor substrate, wherein the second depth is smaller than the first depth, and then performing the high temperature treatment process to form the silicon dioxide layer in the oxygen ion implantation area.

5. The method for manufacturing the semiconductor ultra-thin stacked structure according to claim 4, It is characterized in that The step of removing the stop layer includes: first removing the silicon nitride layer, and then removing the silicon dioxide layer.

6. The method for manufacturing the semiconductor ultra-thin stacked structure according to claim 5, It is characterized in that The substrate removal step is selected from one of chemical mechanical polishing, wet etching and plasma dry etching, wherein the selectivity of silicon to silicon nitride is between 20 and 80.

7. The method for manufacturing the semiconductor ultra-thin stacked structure according to claim 5, It is characterized in that The removal method of the silicon nitride layer and the silicon dioxide layer is selected from one of chemical mechanical polishing and plasma dry etching, wherein the selectivity of silicon nitride to silicon dioxide is between 10 and 20, and the selectivity of silicon dioxide to silicon is 5.

8. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1, It is characterized in that The distance between the stop layer structure and the active surface is between 1 micron and 5 microns, and the thickness of the thinned second semiconductor wafer is not greater than 12 microns.

9. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 1, It is characterized in that After forming the thinned first semiconductor wafer, the method further includes the following steps: Disposing a plurality of solder balls on a side of the thinned first semiconductor wafer away from the thinned second semiconductor wafer to electrically connect the conductive structures respectively; and Conduct electrical testing and cut-off.

10. A method for manufacturing a semiconductor ultra-thin stacked structure, It is characterized in that Include: A plurality of semiconductor wafers are manufactured, and the manufacturing steps of each of the semiconductor wafers include: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface, the stop layer structure at least includes a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high temperature treatment process, so that the nitrogen ion implantation region forms the silicon nitride layer; and disposing a plurality of electrical components and an interconnect layer on the active surface, wherein the interconnect layer comprises a plurality of interconnection points, and disposing a plurality of conductive structures on the first portion of the substrate to connect the interconnect layer and the stop layer structure; Select one of the semiconductor wafers as a first semiconductor wafer at the bottom, and singulate the other semiconductor wafers to form a first batch of semiconductor chips and at least one second batch of semiconductor chips to be stacked; Flipping the first batch of semiconductor chips relative to the first semiconductor wafer so that the interconnect layer of the first batch of semiconductor chips and the interconnect layer of the first semiconductor wafer are opposite to each other and bonded together using a hybrid bonding technology; Performing a first molding process to form a first encapsulation colloid on the first semiconductor wafer to encapsulate the first batch of semiconductor chips; Performing a first backside grinding process to remove a portion of the first encapsulant from a side of the first encapsulant away from the first semiconductor wafer and a portion of the second portion of the substrate of the first batch of semiconductor chips; Performing a first thinning process to form a first semiconductor chip layer; Performing a second backside grinding process to grind from the backside of the first semiconductor wafer to remove a portion of the second substrate portion of the first semiconductor wafer; as well as A second thinning process is performed to form a thinned first semiconductor wafer, wherein the first thinning process and the second thinning process include: a substrate removal step to remove the remaining second portion of the substrate to reveal the stop layer structure; and a stop layer removal step to remove the stop layer structure to reveal the first portion of the substrate and the conductive structures.

11. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 10, It is characterized in that Before performing the second backside grinding process, at least one second semiconductor chip layer may be stacked sequentially on the first semiconductor chip layer, wherein the stacking steps of each of the second semiconductor chip layers include: Flipping the at least one second batch of semiconductor chips relative to the first semiconductor wafer so that the interconnect layer of the at least one second batch of semiconductor chips and the first portion of the substrate of the first semiconductor chip layer are opposite to and bonded together; Performing a second molding process to form a second encapsulation colloid on the first semiconductor chip layer to encapsulate the second batch of semiconductor chips; Performing a third back grinding process to remove a portion of the second encapsulant from a side of the second encapsulant away from the first semiconductor chip layer and a portion of the second portion of the substrate of the second batch of semiconductor chips; and A third thinning process is performed, including the substrate removal step and the stop layer removal step.

12. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 10, It is characterized in that After forming the thinned first semiconductor wafer, the method further includes the following steps: A plurality of solder balls are arranged on a side of the thinned first semiconductor wafer away from the first semiconductor chip layer to electrically connect the conductive structures respectively; and electrical testing and singulation are performed.

13. A method for manufacturing a semiconductor ultra-thin stacked structure, It is characterized in that Include: Providing a carrier plate, and forming a plurality of first conductive pillars on the carrier plate; A plurality of semiconductor chips are provided, and the manufacturing steps of each of the semiconductor chips include: providing a semiconductor substrate having an active surface and a back surface opposite to each other; forming a stop layer structure in the semiconductor substrate, dividing the semiconductor substrate into a first substrate portion and a second substrate portion, wherein the first substrate portion is located between the stop layer structure and the active surface, and the second substrate portion is located between the stop layer structure and the back surface, the stop layer structure at least includes a silicon nitride layer, and the manufacturing of the silicon nitride layer includes first performing a nitrogen ion implantation process at a first depth of the semiconductor substrate, and then performing a high temperature treatment process to form the silicon nitride layer in the nitrogen ion implanted region; arranging a plurality of electrical components and an interconnection layer on the active surface, the interconnection layer including a plurality of interconnection points, and arranging a plurality of conductive structures on the first substrate portion to connect the interconnection layer and the stop layer structure; and performing singulation; Selecting a first batch of semiconductor chips and at least one second batch of semiconductor chips from the semiconductor chips, wherein the first batch of semiconductor chips includes a plurality of first semiconductor chips, and the at least one second batch of semiconductor chips includes a plurality of second semiconductor chips; The first batch of semiconductor chips are flip-chip mounted on the carrier, and the first conductive pillars are located between adjacent first semiconductor chips, wherein the interconnect layer of the first batch of semiconductor chips is adjacent to the carrier and the semiconductor substrate is away from the carrier; Performing a first molding process to form a first packaging colloid on the carrier board to cover the first batch of semiconductor chips and the first conductive pillars; Performing a first back grinding process to remove a portion of the first encapsulant from a side of the first encapsulant away from the carrier plate and a portion of the second portion of the substrate of the first batch of semiconductor chips; Performing a first thinning process to form a first semiconductor chip layer, the first thinning process comprising sequentially removing the remaining second portion of the substrate and the stop layer structure of the first batch of semiconductor chips to expose the first portion of the substrate, the conductive structures and the first conductive pillars; Disposing a plurality of second conductive pillars to electrically connect some of the conductive structures of the first semiconductor chip layer; The second batch of semiconductor chips are flip-chip mounted on the first semiconductor chip layer, wherein the second semiconductor chips are respectively connected between adjacent first semiconductor chips, so that the interconnection layers of the second semiconductor chips are electrically connected to the exposed first conductive pillars and part of the conductive structures of the first semiconductor chip layer, and part of the second conductive pillars are located between the adjacent second semiconductor chips; Performing a second molding process to form a second encapsulation colloid on the first semiconductor chip layer to encapsulate the second batch of semiconductor chips and the second conductive pillars; Performing a second back grinding process to remove a portion of the second encapsulant from a side of the second encapsulant away from the first semiconductor chip layer and a portion of the second portion of the substrate of the second batch of semiconductor chips; Performing a second thinning process to form a second semiconductor chip layer, the second thinning process comprising sequentially removing the remaining second portion of the substrate and the stop layer structure of the second batch of semiconductor chips to expose the first portion of the substrate, the conductive structures and the second conductive pillars; as well as The carrier plate is removed to expose the interconnect layer and the first conductive pillars of the first semiconductor chip layer.

14. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 13, It is characterized in that After removing the carrier plate, the method further comprises the following steps: A plurality of solder balls are arranged on a side of the first semiconductor chip layer away from the second semiconductor chip layer to electrically connect the interconnect layer and the first conductive column respectively; and singulation is performed.

15. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 13, It is characterized in that The first semiconductor chips of the first batch of semiconductor chips have different electrical functions.

16. The method for manufacturing a semiconductor ultra-thin stacked structure according to claim 13, It is characterized in that The second semiconductor chips of the second batch of semiconductor chips have different electrical functions.

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