Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a substrate including adjacent first and second device regions, a channel structure material layer being formed on the substrate, the channel structure material layer including one or more channel material stacks each including a sacrificial material layer and a channel material layer located on the sacrificial material layer, a mask layer being further formed on the channel structure material layer; forming a spacer wall penetrating through the mask layer and the channel structure material layer at the junction of the first and second device regions, and the top of the spacer wall being higher than the top of the mask layer; forming a sidewall layer on the sidewalls of the spacer wall exposed by the mask layer; using the sidewall layer and the spacer wall as masks to remove the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the spacer wall, and retaining the remaining channel structure material layer as a channel structure; forming an isolation layer on the remaining substrate on the side of the channel structure. This is conducive to controlling the width of the formed channel structure and forming a channel structure with high dimensional uniformity.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and semiconductor process nodes are continuously reduced following Moore's Law. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, with the increase in the element density and integration of semiconductor devices, in order to adapt to the reduction of process nodes, the channel length of transistors has to be continuously shortened.

[0003] To better meet the requirements of proportional reduction of device size, semiconductor processes have gradually started to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors and forksheet transistors. Among them, forksheet transistors can overall reduce the cell area. However, the performance of current forksheet transistors still needs to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] To solve the above problem, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate including an adjacent first device region and second device region, a channel structure material layer is formed on the substrate, the channel structure material layer includes one or more channel material stacks, the channel material stack includes a sacrificial material layer and a channel material layer located on the sacrificial material layer, and a mask layer is further formed on the channel structure material layer; at the junction of the first device region and the second device region, form a spacer that penetrates the mask layer and the channel structure material layer, and the top of the spacer is higher than the top of the mask layer; form a sidewall layer on the sidewall of the spacer exposed by the mask layer; using the sidewall layer and the spacer as a mask, remove the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the spacer, and retain the remaining channel structure material layer as a channel structure, the channel structure includes one or more stacked channel stacks, the channel stack includes a first sacrificial layer and a channel layer located on the first sacrificial layer; form an isolation layer on the remaining substrate on the side of the channel structure, and the isolation layer exposes the sidewall of the channel structure.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] In the formation method provided by the embodiment of the present invention, at the junction of the first device region and the second device region, an isolation wall is formed through the mask layer and the channel structure material layer, and the top of the isolation wall is higher than the top of the mask layer. A sidewall layer is formed on the sidewall of the isolation wall exposed by the mask layer. Using the sidewall layer and the isolation wall as a mask, the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the isolation wall are removed, and the remaining channel structure material layer is retained as the channel structure. As the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer. In this embodiment, at the junction of the first device region and the second device region, an isolation wall is formed through the mask layer and the channel structure material layer. Thus, while better ensuring the isolation effect on adjacent devices, the channel structures of the adjacent first device region and the second device region can be made as close as possible, which is beneficial to reducing the distance between the adjacent channel structures of the first device region and the second device region, thereby forming a more compact and smaller-sized device. Moreover, in the embodiment of the present invention, the top of the isolation wall is higher than the top of the mask layer, which is beneficial to forming a sidewall layer with higher size uniformity on the sidewall of the isolation wall. Thus, in the process of removing the channel structure material layer exposed by the sidewall layer and the isolation wall using the sidewall layer and the isolation wall as a mask, since the width size of the sidewall is easy to control and has high uniformity, it is beneficial to control the width of the formed channel structure and form a channel structure with high size uniformity. In summary, the solution of the embodiment of the present invention is beneficial to improving the performance of the semiconductor structure. Description of the Drawings

[0008] Figures 1 to 4 are schematic structural diagrams corresponding to each step in a formation method of a semiconductor structure;

[0009] Figures 5 to 17 are schematic structural diagrams corresponding to each step in an embodiment of the formation method of the semiconductor structure of the present invention. Detailed Embodiment

[0010] Currently, the performance of semiconductor structures needs to be improved. The reason for the need to improve its performance is analyzed in combination with a formation method of a semiconductor structure.

[0011] Figures 1 to 4 are schematic structural diagrams corresponding to each step in a formation method of a semiconductor structure.

[0012] Refer to Figure 1 , a substrate 10 is provided, including an adjacent first device region 10N and a second device region 10P. A channel structure material layer 20 is formed on the substrate 10. The channel structure material layer 20 includes one or more channel material stacks 21. Among them, the channel material stack 21 includes a sacrificial material layer 22 and a channel material layer 23 located on the sacrificial material layer 22.

[0013] Reference Figure 2 , a first patterning process is performed on the channel structure material layer 20 to remove a part of the channel structure material layer 20, and a part of the channel structure material layer 20 covering the junction of the first device region 10N and the second device region 10P is retained.

[0014] Reference Figure 3 , after the first patterning process, a second patterning process is performed on the remaining channel structure material layer 20 to remove a part of the channel structure material layer 20 located at the junction of the first device region 10N and the second device region 10P, forming a trench 40, and retaining the remaining channel structure material layer 20 as the channel structure 24. The channel structure 24 is respectively located in the first device region 10N and the second device region 10P. The channel structure 24 includes one or more stacked channel stacks 25, and the channel stack 25 includes a sacrificial layer 26 and a channel layer 27 located on the sacrificial layer 26.

[0015] Reference Figure 4 , an isolation wall 41 is formed in the trench 40, and the isolation wall 41 covers the opposite sidewalls of the channel structure 20.

[0016] If the channel structure 24 is formed first and then the isolation wall 41 is formed, it is difficult to accurately position the formation position of the trench 40 when forming the trench 40, resulting in difficulty in controlling the width dimension of the formed channel structure 24. Therefore, the width uniformity of the channel structure 24 formed on both sides of the trench 40 is poor, further affecting the performance of the semiconductor structure.

[0017] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including adjacent first and second device regions, a channel structure material layer is formed on the substrate, the channel structure material layer includes one or more channel material stacks, the channel material stack includes a first sacrificial material layer and a channel material layer located on the first sacrificial material layer, and a mask layer is further formed on the channel structure material layer; at the junction of the first device region and the second device region, an isolation wall is formed penetrating the mask layer and the channel structure material layer, and the top of the isolation wall is higher than the top of the mask layer; a sidewall layer is formed on the sidewall of the isolation wall exposed by the mask layer; using the sidewall layer and the isolation wall as masks, removing the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the isolation wall, and retaining the remaining channel structure material layer as the channel structure. The channel structure includes one or more stacked channel stacks, and the channel stack includes a first sacrificial layer and a channel layer located on the first sacrificial layer; an isolation layer is formed on the remaining substrate on the side of the channel structure, and the isolation layer exposes the sidewall of the channel structure.

[0018] As the feature size of integrated circuits continues to decrease, adjacent devices are getting closer and closer. In this embodiment, at the junction of the first device region and the second device region, an isolation wall is formed that penetrates through the mask layer and the channel structure material layer. Thus, while ensuring a good isolation effect for adjacent devices, the channel structures of the adjacent first device region and second device region can be made as close as possible, which is beneficial to reducing the distance between the adjacent channel structures of the first device region and the second device region, thereby forming a more compact and smaller-sized device. Moreover, in the embodiment of the present invention, the top of the isolation wall is higher than the top of the mask layer, which is beneficial to forming a sidewall layer with high size uniformity on the sidewall of the isolation wall. Therefore, in the process of using the sidewall layer and the isolation wall as a mask to remove the channel structure material layer exposed by the sidewall layer and the isolation wall, since the width size of the sidewall is easy to control and has high uniformity, it is beneficial to control the width of the formed channel structure and form a channel structure with high size uniformity. In summary, the solution of the embodiment of the present invention is beneficial to improving the performance of the semiconductor structure.

[0019] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0020] Figures 5 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0021] Refer to Figure 5 , a substrate 100 is provided, which includes an adjacent first device region 100N and a second device region 100P. A channel structure material layer 200 is formed on the substrate 100. The channel structure material layer 200 includes one or more channel material stacks 210. The channel material stack 210 includes a sacrificial material layer 220 and a channel material layer 230 located on the sacrificial material layer 220. A mask layer 300 is also formed on the channel structure material layer 200.

[0022] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure includes a gate-all-around (GAA) transistor and a Forksheet transistor.

[0023] In this embodiment, the substrate 100 includes a substrate 110 and a fin material layer 120 located on the substrate 110.

[0024] In this embodiment, the material of the substrate 110 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide. The substrate can also be other types of semiconductor substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 110 can be a material suitable for process requirements or easy to integrate.

[0025] The fin material layer 120 is used to form fins subsequently.

[0026] In this embodiment, the fin material layer 120 and the substrate 110 are of an integral structure. The material of the fin material layer 120 is silicon. In other embodiments, the fin material layer 120 can also be a semiconductor layer epitaxially grown on the substrate 110, so as to achieve the purpose of precisely controlling the height of the fin material layer 120.

[0027] In this embodiment, taking the semiconductor structure as a fork-shaped gate transistor as an example, the substrate 100 includes an adjacent first device region 100N and a second device region 100P. The first device region 100N is used to form a first device, and the second device region 100P is used to form a second device. The channel conduction types of the first device and the second device are different. That is to say, when the first device is an NMOS transistor, the second device is a PMOS transistor; when the first device is a PMOS transistor, the second device is an NMOS transistor.

[0028] In this embodiment, the first device region 100N is an NMOS region, and the second device region 100P is a PMOS region. The NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor, thereby forming a fork-shaped gate transistor.

[0029] As the device feature size continues to shrink, by adopting a fork-shaped gate transistor, a smaller pitch between adjacent NMOS transistors and PMOS transistors can be allowed, thereby obtaining better area scalability.

[0030] The channel structure material layer 200 is used to form a channel structure subsequently.

[0031] In this embodiment, the channel structure material layer 200 covers the substrate 100 of the first device region 100N and the second device region 100P, and is used to form multiple channel structures in multiple regions simultaneously, simplifying the process flow, improving the process efficiency, and saving the process cost.

[0032] Among them, the channel material stack 210 is used to form the channel stack subsequently, the sacrificial material layer 210 is used to form the first sacrificial layer in the channel stack subsequently, and the channel material layer 220 is used to form the channel layer in the channel stack subsequently.

[0033] In this embodiment, the material of the channel material layer 230 includes silicon, germanium, silicon germanide, or III-V semiconductor material. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0034] It should be noted that, in this embodiment, the materials of the channel material layer 230 and the substrate 110 are the same. In other embodiments, the materials of the channel layer and the substrate may also be different.

[0035] In this embodiment, the material of the sacrificial material layer 220 includes silicon, germanium, or silicon germanide, and there is an etching selectivity between the materials of the channel material layer 230 and the sacrificial material layer 220, which is beneficial to removing the first sacrificial layer after forming the channel layer and the first sacrificial layer subsequently.

[0036] In this embodiment, the material of the channel material layer 230 is silicon. Therefore, the material of the sacrificial material layer 220 is silicon germanide.

[0037] Silicon germanide and silicon can form a large etching selectivity, which is beneficial to removing the first sacrificial layer subsequently and reducing the damage to the channel layer.

[0038] In other embodiments, according to the material of the channel material layer, a suitable material with an etching selectivity to the channel material layer can be selected, so as to reduce the damage to the channel layer when removing the first sacrificial layer subsequently.

[0039] The mask layer 300 is used as an etching mask for forming the channel structure subsequently, and the mask layer 300 is also used to protect the top of the channel structure material layer 200 during the process.

[0040] In this embodiment, the material of the mask layer 300 includes Si3N4, SiBCN, or SiCN.

[0041] In this embodiment, a second sacrificial layer 310 is further formed on the top of the mask layer 300.

[0042] The second sacrificial layer 310 provides support for forming an isolation wall with a top surface higher than the top surface of the mask layer 300 subsequently, and the second sacrificial layer 310 is also used to occupy a spatial position for forming sidewalls on the sidewalls of the isolation wall subsequently.

[0043] Subsequently, it is also necessary to remove the second sacrificial layer 310. In this embodiment, the second sacrificial layer 310 is selected from a material that has an etching selectivity with respect to the mask layer 300 and the isolation wall formed subsequently.

[0044] In this embodiment, the material of the second sacrificial layer 310 includes silicon oxide or silicon oxynitride.

[0045] The material of the mask layer 300 is silicon nitride. Silicon oxide or silicon oxynitride has a large etching selectivity ratio with respect to silicon nitride, which is beneficial to reducing the damage to the mask layer 300 during the subsequent process of removing the second sacrificial layer 310. Moreover, silicon oxide has a small hardness and is easy to remove.

[0046] Combined with reference to Figure 6 and Figure 7 , at the junction of the first device region 100N and the second device region 100P, an isolation wall 410 is formed that penetrates through the mask layer 300 and the channel structure material layer 200, and the top of the isolation wall 410 is higher than the top of the mask layer 300.

[0047] As the feature size of the integrated circuit continues to decrease, adjacent devices are getting closer and closer. In this embodiment, at the junction of the first device region 100N and the second device region 100P, an isolation wall 410 is formed that penetrates through the mask layer 300 and the channel structure material layer 200. Thus, while ensuring a good isolation effect on adjacent devices, the channel structures of the adjacent first device region 100N and second device region 100P can be made as close as possible, which is beneficial to reducing the distance between the adjacent channel structures of the first device region 100N and the second device region 100P, thereby forming a more compact and smaller-sized device. Moreover, in the embodiment of the present invention, the top of the isolation wall 410 is higher than the top of the mask layer 300, which is beneficial to forming a sidewall layer with a high size uniformity on the sidewall of the isolation wall 410. Thus, during the process of removing the channel structure material layer 200 exposed by the sidewall layer and the isolation wall 410 with the sidewall layer and the isolation wall 410 as a mask, since the width dimension of the sidewall is easy to control and has a high uniformity, it is beneficial to control the width of the formed channel structure and form a channel structure with a high size uniformity. In summary, the solution of the embodiment of the present invention is beneficial to improving the performance of the semiconductor structure.

[0048] The isolation wall 410 provides support for the subsequent formation of the sidewall layer. The isolation wall 410 is also used to isolate the adjacent first device region 100N and the second device region 100P, and after the subsequent formation of adjacent source / drain doping layers, the adjacent source / drain doping layers at the junction of the first device region 100N and the second device region 100P are isolated from each other.

[0049] Therefore, in this embodiment, through the isolation wall 410, the isolation effect on adjacent devices can be well ensured, and the source-drain doping layers of the adjacent first device region 100N and second device region 100P can be made as close as possible, which is beneficial to reducing the distance between the adjacent channel structures of the first device region 100N and the second device region 100P, thereby forming a more compact and smaller-sized device.

[0050] In this embodiment, the top of the isolation wall 410 is higher than the top of the mask layer 300, which can also improve the subsequent isolation effect on adjacent source-drain doping layers.

[0051] It should be noted that in this embodiment, in the step of forming the isolation wall 410, the distance h from the top of the isolation wall 410 to the top of the mask layer 300 cannot be too large or too small. If the distance h from the top of the isolation wall 410 to the top of the mask layer 300 is too large, a second sacrificial layer 310 with too large a thickness needs to be formed, resulting in unnecessary process waste, and increasing the difficulty of removing the second sacrificial layer 310 subsequently. The etching amount for removing the second sacrificial layer 310 needs to be increased, thereby increasing the probability of damaging other film layers when removing the second sacrificial layer 310. If the distance h from the top of the isolation wall 410 to the top of the mask layer 300 is too small, it increases the difficulty of forming a sidewall layer on the exposed sidewalls of the isolation wall 410 subsequently, making it difficult to form a sidewall layer with a height meeting the process requirements, and thus affecting the quality of the channel structure etched with the sidewall layer as a mask. Therefore, in this embodiment, in the step of forming the isolation wall 410, the distance h from the top of the isolation wall 410 to the top of the mask layer 300 is 5 nm to 40 nm.

[0052] In this embodiment, the material of the isolation wall 410 includes silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide.

[0053] The silicon oxide, silicon nitride, silicon oxynitride, or carbon-doped silicon oxide has good insulation, which can make the adjacent source-drain doping layers formed subsequently have a good isolation effect at the junction of the first device region 100N and the second device region 100P.

[0054] Specifically, referring to Figure 6 , the step of forming the isolation wall 410 includes: forming an isolation groove 400 penetrating the second sacrificial layer 310, the mask layer 300, and the channel structure material layer 200 at the junction of the first device region 100N and the second device region 100P.

[0055] The isolation groove 400 provides a spatial position for forming the isolation wall 410.

[0056] In this embodiment, the isolation trench 400 is formed by a dry etching process.

[0057] The dry etching process is an anisotropic dry etching process with the characteristics of anisotropic etching, which is beneficial to reducing the damage to the substrate 100 at the bottom of the isolation trench 400 and the channel structure material layer 200 on the side wall of the isolation trench 400. At the same time, the dry etching has more etching directionality, which is beneficial to improving the side wall morphology quality and dimensional accuracy of the isolation trench 400.

[0058] In this embodiment, an isolation wall material layer (not shown) is filled in the isolation trench 400, and the isolation material layer also covers the top of the second sacrificial layer 310.

[0059] The isolation wall material layer is used to form the isolation wall 410.

[0060] In this embodiment, the isolation wall material layer is formed by a deposition process (for example, chemical vapor deposition process).

[0061] In this embodiment, the material of the isolation wall material layer includes silicon oxide, silicon nitride, silicon oxynitride or carbon-doped silicon oxide, which is used to directly form the isolation wall 410.

[0062] Reference Figure 7 , taking the top of the second sacrificial layer 310 as the stop position, the isolation wall material layer higher than the top of the second sacrificial layer 310 is removed, and the remaining isolation wall material layer in the isolation trench 400 is retained as the isolation wall 410.

[0063] Taking the top of the second sacrificial layer 310 as the stop position, an isolation wall 410 with a top surface higher than the top surface of the mask layer 300 can be formed.

[0064] In this embodiment, a chemical mechanical polishing process is used to remove the isolation wall material layer higher than the top of the second sacrificial layer.

[0065] Reference Figure 8 , after forming the isolation wall 410 and before forming the sidewall layer subsequently, it further includes: removing the second sacrificial layer 310.

[0066] Removing the second sacrificial layer 310 exposes a part of the side wall of the isolation wall 410, providing a spatial position for forming the sidewall layer subsequently.

[0067] In this embodiment, a wet etching process is used to remove the second sacrificial layer 310.

[0068] The wet etching process has an isotropic property, which is beneficial to completely removing the second sacrificial layer 310. Moreover, the wet etching process can have good etching selectivity, so that during the process of removing the second sacrificial layer 310, the damage to the mask layer 300 and the isolation wall 410 can be reduced.

[0069] With reference to Figure 9 and Figure 10 , a sidewall layer 510 is formed on the sidewall of the isolation wall 410 exposed by the mask layer 300.

[0070] The sidewall layer 510 is used as an etching mask for subsequently forming a channel structure.

[0071] In this embodiment, the material of the sidewall layer 510 includes silicon nitride Si3N4, SiBCN or SiCN.

[0072] Si3N4, SiBCN or SiCN has a high hardness, which is beneficial to being used as an etching mask and improving the accuracy of pattern transfer.

[0073] Specifically, with reference to Figure 9 , the steps of forming the sidewall layer 510 include: forming a sidewall material layer 500 that conformally covers the top of the mask layer 300, the top of the isolation wall 510, and the sidewall of the isolation wall 410 exposed by the mask layer 300.

[0074] The sidewall material layer 500 is used to form the sidewall layer 510.

[0075] In this embodiment, the sidewall material layer 500 is formed by an atomic layer deposition process.

[0076] The sidewall material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the sidewall material layer 500 can well conformally cover the top of the mask layer 300, the top of the isolation wall 510, and the sidewall of the isolation wall 410 exposed by the mask layer 300.

[0077] In this embodiment, the material of the sidewall material layer 500 includes Si3N4, SiBCN or SiCN, and is used to directly form the sidewall layer 510.

[0078] With reference to Figure 10 , the sidewall material layer 500 located on the top of the mask layer 300 and the top of the isolation wall 410 is removed, and the sidewall material layer 500 located on the sidewall of the isolation wall 410 exposed by the mask layer 300 is retained as the sidewall layer 510.

[0079] Remove the sidewall material layer 500 located on top of the mask layer 300 and on top of the isolation wall 410, forming the sidewall layer 510 while exposing a portion of the mask layer 300, preparing for subsequent removal of a portion of the mask layer 300.

[0080] In this embodiment, a dry etching process is used to remove the sidewall material layer 500 located on top of the mask layer 300 and on top of the isolation wall 410.

[0081] The dry etching process is an anisotropic dry etching process, having the characteristics of anisotropic etching, which is beneficial to reducing damage to the sidewall layer 510 and the mask layer 300. At the same time, the dry etching has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the sidewall layer 500.

[0082] Therefore, in this embodiment, in the manner of a self-aligned double patterning (SADP) process, a sidewall layer 510 is formed on the sidewalls of the isolation wall 410 exposed by the mask layer 300, thereby improving the width dimension uniformity and position accuracy of the sidewall layer 510.

[0083] Reference Figure 11 , using the sidewall layer 510 and the isolation wall 410 as masks, remove the mask layer 300, the channel structure material layer 200, and a portion of the thickness of the substrate 100 exposed by the sidewall layer 510 and the isolation wall 410, and retain the remaining channel structure material layer 200 as the channel structure 240. The channel structure 240 includes one or more stacked channel stacks 250, and the channel stack 250 includes a first sacrificial layer 260 and a channel layer 270 located on the first sacrificial layer 260.

[0084] The width dimension of the sidewall layer 510 is easy to control and has high uniformity. Then, using the sidewall layer 510 and the isolation wall 410 as masks, a channel structure 240 with an easy-to-control width dimension and high uniformity can be formed.

[0085] In this embodiment, a dry etching process is used to remove the mask layer 300, the channel structure material layer 200, and a portion of the thickness of the substrate 100 exposed by the sidewall layer 510 and the isolation wall 410.

[0086] The dry etching process is an anisotropic dry etching process, having the characteristics of anisotropic etching, which is beneficial to reducing damage to the channel structure 240. At the same time, the dry etching has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the channel structure 240.

[0087] The channel layer 270 in the channel structure 240 is used to provide the channel of the transistor. The first sacrificial layer 260 is used to provide a process basis for the subsequent implementation of the suspended setting of the channel layer 270, and is also used to occupy the spatial position for the subsequently formed gate structure. In the subsequent manufacturing process, the first sacrificial layer 260 is removed, so that the channel layer 270 is suspended, and a gate structure is formed between the channel layer 270 and the substrate 100, and between adjacent channel layers 270, so that the gate structure surrounds and covers the channel layer 270.

[0088] The top and side walls of the channel layer 270 covered by the gate structure are used as the channel. In this embodiment, the top, bottom and side walls of the channel layer 270 can all be used as the channel, increasing the area of the channel layer 270 used as the channel, thereby increasing the working current of the semiconductor structure.

[0089] In this embodiment, the material of the channel layer 270 includes silicon, germanium, silicon germanide or III-V semiconductor material. As an example, the material of the channel layer 270 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0090] In this embodiment, the material of the first sacrificial layer 260 includes silicon, germanium or silicon germanide, and there is an etching selectivity between the material of the channel layer 260 and the first sacrificial layer 270, which is beneficial to the subsequent removal of the first sacrificial layer 260.

[0091] In this embodiment, the material of the channel layer 270 is silicon. Therefore, the material of the first sacrificial layer 260 is silicon germanide.

[0092] The silicon germanide and silicon can form a large etching selectivity, which is beneficial to the subsequent removal of the first sacrificial layer 260 and reduces the damage to the channel layer 270.

[0093] Specifically, using the sidewall layer 510 and the isolation wall 410 as masks, the mask layer 300 exposed by the sidewall layer 510 and the isolation wall 410 is removed, and the remaining mask layer 300 is retained; the sidewall layer 510 is removed; after removing the sidewall layer 510, using the remaining mask layer 300 as an etching mask, the channel structure material layer 200 and a part of the thickness of the substrate 100 are etched, and the remaining channel structure material layer 200 is retained as the channel structure 240.

[0094] Continue to refer to Figure 11In the step of removing the mask layer 300, the channel structure material layer 200, and a part of the thickness of the substrate 100 exposed by the sidewall layer 510 and the isolation wall 410 with the sidewall layer 510 as a mask, the fin material layer 120 exposed by the sidewall layer 510 and the isolation wall 410 is removed, and the remaining fin material layer 120 is reserved as the fin 130.

[0095] Removing the fin material layer 120 exposed by the sidewall layer 510 and the isolation wall 410 provides a space position for forming the isolation layer subsequently.

[0096] In this embodiment, the material of the fin 130 is silicon.

[0097] In this embodiment, a dry etching process is used to etch the channel structure material layer 200 and a part of the thickness of the substrate 100.

[0098] The dry etching process is an anisotropic dry etching process, which has the characteristics of anisotropic etching, is beneficial to reducing the damage to the substrate 110. At the same time, the dry etching has more etching directionality, which is beneficial to improving the sidewall morphology quality and dimensional accuracy of the fin 130.

[0099] Combined with reference to Figures 12 to 13 , an isolation layer 150 is formed on the remaining substrate 100 on the side of the channel structure 240, and the sidewall of the channel structure 240 is exposed by the isolation layer 150.

[0100] The isolation layer 150 is used to achieve insulation between different devices. For example, in the CMOS manufacturing process, an isolation layer 150 is usually formed between the NMOS transistor and the PMOS transistor. The isolation layer 150 exposes the sidewall of the channel structure 240, preparing for the subsequent formation of the gate structure covering the channel layer 270.

[0101] The material of the isolation layer 150 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide.

[0102] In this embodiment, in the step of removing the mask layer 300, the channel structure material layer 200, and a part of the thickness of the substrate 100 exposed by the sidewall layer 510 and the isolation wall 410 with the sidewall layer 510 as a mask, if the fin material layer 120 exposed by the sidewall layer 510 and the isolation wall 410 is removed to expose the substrate 110, then in this embodiment, the step of forming the isolation layer 150 on the remaining substrate 100 on the side of the channel structure 240 includes: forming an isolation layer 150 covering the sidewall of the fin 130 on the substrate 100, thereby isolating adjacent fins 130 from each other.

[0103] Specifically, referring toFigure 12 The steps of forming the isolation layer 150 include: forming an isolation material layer 140 on the remaining substrate 100 on the side of the channel structure 240, covering the sidewalls of the channel structure 240, the sidewalls and the top of the mask layer 300, and the sidewalls of the isolation wall 410.

[0104] The isolation material layer 140 is used to form the isolation layer 150.

[0105] In this embodiment, the isolation material layer 140 is formed by a deposition process, which is beneficial to forming an isolation material layer 140 with high thickness uniformity.

[0106] The material of the isolation material layer 140 includes one or more of silicon oxide, carbon-doped silicon oxide, silicon oxynitride, silicon nitride, boron-doped silicon oxide, and phosphorus-doped silicon oxide, and is used to directly form the isolation layer 150.

[0107] Reference Figure 13 , removing a part of the thickness of the isolation material layer 140 to expose the sidewalls of the channel structure 240, and retaining the remaining isolation material layer 140 covering the top and sidewalls of the remaining substrate 100 as the isolation layer 150.

[0108] By using the method of first forming the isolation material layer 140 and then performing re-etching to form the isolation layer 150, it is easy to control the height dimension of the formed isolation layer 150, which is beneficial to forming an isolation layer 150 with high dimension quality.

[0109] In this embodiment, the dry etching process is used to remove a part of the thickness of the isolation material layer 140, which is easy to control the thickness dimension of the removed part of the thickness of the isolation material layer 140 and form an isolation layer 150 with high quality.

[0110] Reference Figure 14 , after forming the isolation layer 150, it further includes: removing the remaining mask layer 300.

[0111] Removing the remaining mask layer 300 exposes the top surface of the channel layer 270 on the top of the channel structure 240, preparing for the subsequent formation of the gate structure covering the channel layer 270.

[0112] In this embodiment, the wet etching process is used to remove the mask layer 300, which is beneficial to removing the mask layer 300 completely, and the wet etching process has good etching selectivity, which is beneficial to reducing the damage to the channel layer 270 during the process of removing the mask layer 300.

[0113] Continue to refer to Figure 14, after removing the remaining mask layer 300, the forming method further includes: forming a dummy gate structure 600 across the channel structure 240 and the isolation wall 410, where the dummy gate structure 600 covers a part of the sidewalls and a part of the top of the channel structure 240, as well as a part of the top and a part of the sidewalls of the isolation wall 410.

[0114] The dummy gate structure 600 occupies a spatial position for the gate structure formed in subsequent processes.

[0115] In this embodiment, the dummy gate structure 600 can be a single-layer structure or a stacked structure, and the material of the dummy gate structure 610 includes one or both of amorphous silicon and polysilicon. In other embodiments, the material of the dummy gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, or amorphous carbon.

[0116] In this embodiment, the dummy gate structure 600 is a single-layer structure, and the material of the dummy gate structure 600 is amorphous silicon. Amorphous silicon does not have a crystal orientation. Therefore, the etching rate uniformity and etching effect uniformity of amorphous silicon are better, thereby improving the removal effect of the subsequent dummy gate structure 600.

[0117] It should be noted that, according to process requirements, a dummy gate oxide layer (not shown in the figure) can also be formed between the dummy gate structure 600 and the channel structure 240. Among them, the material of the dummy gate oxide layer can be silicon oxide.

[0118] Reference Figure 15 , Figure 15 is a source / drain doping layer cross-section perpendicular to the extending direction of the channel structure 240. Source / drain doping layers 610 are formed on the substrate 100 on both sides of the dummy gate structure 600. The source / drain doping layers 610 are in contact with the ends of the channel structure 240 below the dummy gate structure 600, and at the junction of the first device region 100N and the second device region 100P, adjacent source / drain doping layers 610 are isolated by the isolation wall 410.

[0119] The source / drain doping layer 610 is used as the source region or drain region of the transistor, and the doping type of the source / drain doping layer 610 is the same as the channel conduction type of the corresponding transistor.

[0120] Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doping layer 610 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source / drain doping layer 610 are P-type ions, and the P-type ions include B ions, Ga ions, or In ions.

[0121] The adjacent source / drain doping layers 610 near the junction of the first device region 100N and the second device region 100P are isolated by the isolation wall 410, so as to better ensure the isolation effect between the adjacent source / drain doping layers 610.

[0122] It should be noted that in this embodiment, the source / drain doping layer 610 is formed at the end of the channel structure 240 under the pseudo-gate structure 600 through an epitaxial growth process. Then the source / drain doping layer 610 is in contact with the isolation wall 410. In the direction perpendicular to the extending direction of the channel layer structure 240, the size of the source / drain doping layer 610 can be maximized as much as possible, thereby improving the performance of the semiconductor structure.

[0123] Continue to refer to Figure 15 , an interlayer dielectric layer 620 covering the source / drain doping layer 610 is formed on the substrate 100. The interlayer dielectric layer 620 also covers the sidewalls of the pseudo-gate structure 600 and exposes the top of the pseudo-gate structure 600.

[0124] The interlayer dielectric layer 620 is used to isolate adjacent devices. The interlayer dielectric layer 620 is also used to provide a process basis for subsequent removal of the pseudo-gate structure 600 to form a gate opening. The interlayer dielectric layer 620 exposes the top of the pseudo-gate structure 600 to prepare for subsequent removal of the pseudo-gate structure 600.

[0125] In this embodiment, the interlayer dielectric layer 620 is formed by a chemical vapor deposition process. The interlayer dielectric layer 620 covers the source / drain doping layer 610 and the pseudo-gate structure 600. Then, a chemical mechanical polishing process is used to planarize the interlayer dielectric layer 620, removing a part of the thickness of the interlayer dielectric layer 620 to expose the top of the pseudo-gate structure 600.

[0126] The material of the interlayer dielectric layer 620 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon silicon oxynitride.

[0127] Refer to Figure 16 , the pseudo-gate structure 600 is removed, and a gate opening (not shown in the figure) is formed in the interlayer dielectric layer 620. The gate opening exposes the first sacrificial layer 260.

[0128] Specifically, the pseudo-gate structure 600 and the pseudo-gate oxide layer are removed in sequence.

[0129] The gate opening provides a spatial position for subsequent formation of a gate structure. At the same time, the gate opening exposes the first sacrificial layer 260 to prepare for subsequent removal of the first sacrificial layer 260.

[0130] Continue to refer toFigure 16 , remove the first sacrificial layer 260 exposed by the gate opening, exposing the channel layer 270.

[0131] The top, bottom, and one side wall of the channel layer 270 are exposed by the gate opening, such that the subsequently formed gate structure surrounds and covers the top, bottom, and one side wall of the channel layer 270.

[0132] In this embodiment, a wet etching process is used to remove the first sacrificial layer 260. The wet etching process has relatively low cost, simple operation steps, and can also achieve a large etching selectivity ratio, which is beneficial to reducing the damage to the channel layer 270 during the process of removing the first sacrificial layer 260.

[0133] It should be noted that the end of the channel layer 270 is in contact with the source / drain doping layer 610. Then, after removing the first sacrificial layer 260, the channel layer 270 is suspended above the substrate 110 at intervals.

[0134] Refer to Figure 17 , after removing the first sacrificial layer 260 exposed by the gate opening, a gate structure 700 spanning the channel layer 270 is formed in the gate opening. The gate structure 700 includes a gate dielectric layer 710 that surrounds and covers the channel layer 270 and the isolation wall 410, and a gate electrode layer 720 that surrounds and covers the gate dielectric layer 710.

[0135] The gate structure 700 is used to control the opening or closing of the channel of the transistor.

[0136] In this embodiment, the gate structure 700 includes a metal gate structure.

[0137] The gate dielectric layer 710 is used to isolate the gate electrode layer 720 from the channel layer 270 and the fin 130.

[0138] The material of the gate dielectric layer 710 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer 710 includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes high-k dielectric materials. Among them, the high-k dielectric material refers to a dielectric material whose relative dielectric constant is greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0139] It should be noted that the gate dielectric layer 710 may further include a gate oxide layer located between the channel layer 270 and the high-k gate dielectric layer. As an example, the material of the gate oxide layer may be SiO2.

[0140] In this embodiment, the gate electrode layer 720 includes a work function layer (not labeled) and an electrode layer (not labeled) located on the work function layer. Among them, the work function layer is used to adjust the threshold voltage of the formed transistor, and the electrode layer is used to lead out the electrical property of the gate electrode layer 720.

[0141] In this embodiment, the material of the gate electrode layer 720 is one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.

[0142] In other embodiments, according to process requirements, the gate structure may also be a polysilicon gate structure.

[0143] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate including an adjacent first device region and second device region, a channel structure material layer being formed on the substrate, the channel structure material layer including one or more channel material stacks, the channel material stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer, and a mask layer being further formed on the channel structure material layer; At the junction of the first device region and the second device region, forming a spacer that penetrates through the mask layer and the channel structure material layer, and the top of the spacer being higher than the top of the mask layer; Forming a sidewall layer on the sidewall of the spacer exposed by the mask layer; Using the sidewall layer and the spacer as a mask, removing the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the spacer, and retaining the remaining channel structure material layer as a channel structure, the channel structure including one or more stacked channel stacks, the channel stack including a first sacrificial layer and a channel layer located on the first sacrificial layer; Forming an isolation layer on the remaining substrate on the side of the channel structure, the isolation layer exposing the sidewall of the channel structure.

2. The method for forming a semiconductor structure according to claim 1, wherein, In the step of providing the substrate, a second sacrificial layer is further formed on the top of the mask layer; The step of forming the spacer includes: at the junction of the first device region and the second device region, forming a spacer groove that penetrates through the second sacrificial layer, the mask layer, and the channel structure material layer; filling a spacer material layer in the spacer groove, the spacer material layer further covering the top of the second sacrificial layer; using the top of the second sacrificial layer as a stop position, removing the spacer material layer higher than the top of the second sacrificial layer, and retaining the remaining spacer material layer in the spacer groove as the spacer; After forming the spacer and before forming the sidewall layer, further including: removing the second sacrificial layer.

3. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the sidewall layer includes: forming a conformal sidewall material layer covering the top of the mask layer, the top of the spacer, and the sidewall of the spacer exposed by the mask layer; Removing the sidewall material layer located on the top of the mask layer and the top of the spacer, and retaining the sidewall material layer located on the sidewall of the spacer exposed by the mask layer as the sidewall layer.

4. The method for forming a semiconductor structure according to claim 2, wherein, Using a chemical vapor deposition process to fill the spacer groove with a spacer material layer.

5. The method for forming a semiconductor structure according to claim 2, wherein Using a chemical mechanical polishing process to remove the spacer material layer higher than the top of the second sacrificial layer.

6. The method for forming a semiconductor structure according to claim 2, wherein, Using a wet etching process to remove the second sacrificial layer.

7. The method for forming a semiconductor structure according to claim 1, wherein, Using a dry etching process to remove the mask layer, the channel structure material layer, and a part of the thickness of the substrate exposed by the sidewall layer and the spacer.

8. The method for forming a semiconductor structure according to claim 3, wherein, Using an atomic layer deposition process to form the sidewall material layer.

9. The method for forming a semiconductor structure according to claim 3, wherein Using a dry etching process to remove the sidewall material layer located on the top of the mask layer and the top of the spacer.

10. The method for forming a semiconductor structure according to claim 1, wherein, In the step of providing the substrate, the material of the channel material layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material, the material of the sacrificial material layer includes silicon, germanium, or silicon germanide, and there is an etching selectivity between the material of the channel material layer and the sacrificial material layer.

11. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the spacer, the material of the spacer includes carbon-doped silicon nitride, boron-doped silicon nitride, or carbon- and boron-doped silicon nitride.

12. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the isolation wall, the distance from the top of the isolation wall to the top of the mask layer is 5 nm to 40 nm.

13. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the sidewall layer, the material of the sidewall layer includes Si3N4, SiBCN or SiCN.

14. The method for forming a semiconductor structure according to claim 2, wherein, In the step of forming the second sacrificial layer, the material of the second sacrificial layer includes silicon oxide or silicon oxynitride.

15. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the mask layer, the material of the mask layer includes Si3N4, SiBCN or SiCN.

16. The method for forming a semiconductor structure according to claim 7, wherein, The first device region is used to form a first device, the second device region is used to form a second device, and the channel conduction types of the first device and the second device are different.

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