Integrated circuit comprising at least one bipolar transistor and corresponding manufacturing method

Abstract

Integrated circuits including at least one bipolar transistor and corresponding methods of manufacture are disclosed. The bipolar transistor includes a common collector region including a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and bounded by the buried semiconductor layer. A first base region and a second base region are formed from the well region and separated from one another by a vertical gate structure. A first emitter region is implanted in the first base region and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington device. The structure of the bipolar transistor can be co-integrated with non-volatile memory cells.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the priority benefit of French Patent Application No. 21 05334, filed May 21, 2021, the entire contents of which are incorporated herein by reference to the maximum extent legally permissible. TECHNICAL FIELD

[0003] Embodiments and implementations relate to integrated circuits, in particular bipolar transistors, and methods for manufacturing bipolar transistors. BACKGROUND

[0004] A bipolar transistor generally comprises a base region of a first type of doped semiconductor, for example p-type, a collector region of a second type of doped semiconductor, for example n-type, adjacent to the base region, and an emitter region of the second type of doped semiconductor, adjacent to the base region.

[0005] When the first type is doped in a semiconductor substrate forming the bipolar transistor, the second type of doped well forming the collector region generally surrounds the base region, which makes it possible to electrically insulate the base region and the substrate with two opposite PN junctions.

[0006] Integrated circuits mainly comprising “digital” electronic devices, for example logic circuits in the complementary technology CMOS (Complementary Metal Oxide Semiconductor) and non-volatile memory circuits for storing digital data, can comprise bipolar transistors, for example found in generator circuits with temperature-independent reference voltage, such as bandgap circuits.

[0007] The steps for manufacturing bipolar transistors in this type of integrated circuit are generally co-integrated with the manufacturing steps of the digital electronic devices, i.e. steps performed simultaneously with the steps provided for other digital elements, and not dedicated to bipolar transistors.

[0008] For example, the formation of the collector region can be co-integrated as part of a three-well type structure, in a step of forming an insulating region buried at a depth of the semiconductor substrate.

[0009] The formation of the base region can be co-integrated in a step of forming a logic circuit transistor well.

[0010] The formation of the emitter region can be co-integrated in a step of forming source and drain regions of CMOS transistors.

[0011] Gathering manufacturing steps can reduce manufacturing costs, but the resulting bipolar transistors are usually poorly optimized. The bipolar transistors thus perform poorly, in particular in the case where the "beta" current gain β can be less than 10, whereas a comparable bipolar transistor made by dedicated and optimized steps can have a current gain β of between 100 and 200.

[0012] A "Darlington" transistor configuration, i.e. a common collector configuration of at least two bipolar transistors, in which the emitter of the upstream bipolar transistor is connected to the base of the downstream bipolar transistor, so that an equivalent bipolar transistor with a greater current gain β can be formed. The equivalent current gain β of the Darlington configuration is given by the "n"th polynomial of the current gain β values of the individual bipolar transistors, "n" being the number of bipolar transistors in the Darlington configuration.

[0013] However, this type of configuration has the drawback, compared to a single bipolar transistor, of the space occupied by the Darlington configuration multiplied by "n" and the activation voltage (base-emitter voltage) multiplied by "n" with respect to a single bipolar transistor. This becomes particularly problematic when "n" is greater than or equal to 3 (n > 3).

[0014] There is therefore a need for an embodiment of a bipolar transistor that performs well, in particular with a high current gain β, without increasing the space occupied by the bipolar transistor and limiting the value of the activation voltage. SUMMARY

[0015] In this respect, according to one aspect, an integrated circuit is proposed comprising at least one bipolar transistor arranged in and / or on a doped semiconductor substrate of a first type. The bipolar transistor comprises: a common collector region comprising a buried semiconductor layer of a second type opposite to the first type located in a depth of the doped substrate and a doped annular well of the second type connecting the buried semiconductor layer; a doped semiconductor well of the first type surrounded by the annular well and delimited by the buried semiconductor layer, the doped semiconductor well of the first type containing a first base region and a second base region; a doped first emitter region of the second type located in the first base region and a doped second emitter region of the second type located in the second base region; a conductor track for electrically coupling the first emitter region with the second base region; and a vertical gate structure extending vertically across the semiconductor well containing the base regions to the buried semiconductor layer so as to electrically insulate the first base region and the second base region.

[0016] In other words, a Darlington transistor type configuration with two bipolar transistors is proposed, but with a single "triple well" containing two base regions, i.e. with the dimensions of the standard form of a single bipolar transistor.

[0017] In fact, the space occupied by the vertical gate structure for insulating the first and second base regions from each other within the well is negligible with respect to the size of the bipolar transistor. In particular, the space occupied by the vertical gate structure is much smaller than the space occupied for insulating the base regions in the standard way of a well doped with the opposite doping type to that of the base regions.

[0018] According to one embodiment, the vertical gate structure comprises a trench filled with an electrically conductive material, the electrically conductive material being electrically insulated on the bottom and the sides of the trench by a dielectric shell.

[0019] According to one embodiment, the vertical gate structure further comprises a region implanted at the bottom of the trench, the region being doped of the second type, occupying the space between the bottom of the trench and the buried semiconductor layer in the semiconductor well containing the base regions.

[0020] In fact, the trench filled with an electrically conductive material in a dielectric shell can reach the buried semiconductor layer, in which case the electrical insulation between the two base regions is entirely formed by the trench, in particular by the dielectric shell. In this case, in fact, it is possible that the trench does not reach the buried semiconductor layer, and in this case the vertical gate structure advantageously comprises said region implanted between the bottom of the trench and the buried semiconductor layer. Thus, the electrical insulation between the two base regions is formed by the region implanted at the bottom of the trench and the dielectric shell.

[0021] According to one embodiment, the vertical gate structure extends vertically from a front surface of the semiconductor well containing the base regions into the semiconductor well containing the base regions and longitudinally in the plane of the front surface radially from one edge of the annular well surrounding the semiconductor well containing the base regions to the other edge.

[0022] According to one embodiment, the integrated circuit further comprises said at least bipolar transistor, at least one non-volatile memory cell, the non-volatile memory cell comprising a floating gate transistor and a buried access transistor with a vertical gate, and wherein the semiconductor well containing the base regions has the same depth, the same composition and the same dopant concentration as the well of the memory cell containing the region forming the channel of the floating gate transistor.

[0023] The channel region of the floating gate transistor is generally the region between the source region and the drain region of the floating gate transistor.

[0024] In addition to the fact that the semiconductor well containing the base regions of the bipolar transistor can be co-integrated with the well of the memory cell formed, the depth of the well of the memory cell is advantageously lower than the three-well of the other type of embodiment. Furthermore, the dopant concentration in the well of the memory cell is advantageously lower than the concentration of the three-well of the other type of embodiment, making it possible to increase the electrical resistance of the base regions and therefore the voltage resistance of the PN junction formed with the well.

[0025] This results in an increase of the current gain β of the bipolar transistor formed in each base region. In fact, the current gain β is inversely proportional to the base dopant concentration and inversely proportional to the base depth (emitter-collector distance). However, the co-integration of the bipolar transistor with the non-volatile memory cell makes it possible to reduce the depth and concentration of the dopant in the well containing the base region.

[0026] According to one embodiment: the buried semiconductor layer of the common collector region has the same composition and the same depth as the buried semiconductor layer forming the source plane extending under the well of the memory cell; the annular well of the common collector region has the same composition and the same structure as the annular well surrounding the well of the memory cell and allows electrical contact with the buried semiconductor layer forming the source plane; the vertical gate structure electrically insulating the first and second base regions has the same structure and the same dimensions as the gate structure of the buried access transistor having a vertical gate.

[0027] According to one embodiment, the at least one bipolar transistor belongs to a temperature-independent reference voltage generation circuit.

[0028] According to another aspect, a method for manufacturing an integrated circuit in a doped semiconductor substrate of a first type is proposed, comprising manufacturing at least one bipolar transistor, comprising: forming a common collector region, comprising implanting a buried semiconductor layer doped with a second type opposite to the first type in a depth of the substrate, and implanting a doped semiconductor annular well of the second type connecting the buried semiconductor layer; implanting a doped semiconductor well of the first type in a region enclosed by the annular well and delimited by the buried semiconductor layer; forming a vertical gate structure extending vertically through the doped semiconductor well of the first type to the buried semiconductor layer, to electrically insulate a first base region and a second base region in the doped semiconductor well of the first type; implanting a first emitter region doped with the second type in the first base region, and implanting a second emitter region doped with the second type in the second base region; and forming a conductor track electrically coupling the first emitter region to the second base region.

[0029] In one embodiment, forming the vertical gate structure comprises etching a trench, forming a dielectric shell at the bottom and the sides of the trench, and filling the trench with an electrically conductive material.

[0030] In one embodiment, forming the vertical gate structure further comprises implanting a doped implant region of the second type at the bottom of the trench so as to occupy space in the doped semiconductor well of the first type between the bottom of the trench and the buried semiconductor layer.

[0031] In one embodiment, the vertical gate structure is formed to extend vertically in the doped semiconductor well of the first type from a front surface of the doped semiconductor well of the first type and radially longitudinally in a planar direction of the front surface from one edge of the annular well surrounding the doped semiconductor well of the first type to the other edge.

[0032] In one embodiment, the method further comprises fabricating at least one non-volatile memory cell comprising a floating gate transistor and a buried access transistor having a vertical gate, wherein implanting a well comprising a channel region of the floating gate transistor of said memory cell is performed simultaneously with implanting a doped semiconductor well of a first type.

[0033] In one embodiment: implanting a common collector region in a depth of a buried semiconductor layer is performed simultaneously with implanting the buried semiconductor layer, the buried semiconductor layer forming a source plane extending below a well of a memory cell; implanting an annular well of the common collector region is performed simultaneously with implanting an annular well surrounding the well of the memory cell and allowing electrical contact to the buried semiconductor layer forming the source plane; and forming a vertical gate structure electrically isolating a first base region and a second base region is performed simultaneously with forming a gate structure of a buried access transistor having a vertical gate. BRIEF DESCRIPTION OF DRAWINGS

[0034] Other advantages and features of the present invention are set forth in the following detailed description and appended claims, and are shown in the accompanying drawings, which are not being considered as limiting, wherein:

[0035] Figure 1 and Figure 2 An exemplary embodiment of a bipolar transistor is shown;

[0036] Figure 3 A Darlington configuration is shown, two transistors equivalent to a bipolar transistor;

[0037] Figure 4 A temperature independent voltage generator circuit (bandgap type) is shown; and

[0038] Figures 5 to 9 Fabrication steps of a bipolar transistor performed in co-integration with the fabrication of a non-volatile memory cell are shown. DETAILED DESCRIPTION

[0039] Figure 1 and Figure 2 An exemplary embodiment of a bipolar transistor TBP of an integrated circuit CI is shown. Figure 1 A cross-sectional view of the bipolar transistor TPB in the plane I-I of Figure 2 is shown, while Figure 2 a top view of the bipolar transistor TBP in the plane II-II of Figure 1 is shown.

[0040] The bipolar transistor TBP is formed in a doped semiconductor substrate PSUB of a first type, for example p-type.

[0041] The bipolar transistor TBP is designed in a Darlington configuration of two bipolar transistors, wherein the single "three-well" contains two base regions, i.e. a Darlington configuration of two transistors with standard form single bipolar transistor size.

[0042] Reference is made to Figure 3 , which shows a Darlington configuration of two transistors equivalent to a bipolar transistor TBP. Each transistor comprises a collector region C, a base region B1, B2 and an emitter region E1, E2. The collector regions C of the two transistors are coupled together, the emitter region E1 of the "upstream" transistor is coupled to the base region of the "downstream" transistor (the terms "upstream" and "downstream" are defined by this coupling). The common collector region C forms the equivalent collector region of the bipolar transistor TBP, the base region B1 of the upstream transistor forms the equivalent base region of the bipolar transistor TBP, and the emitter region E2 of the downstream transistor forms the equivalent emitter region of the bipolar transistor TBP.

[0043] When the upstream and downstream transistors of the Darlington configuration each have the same current gain β0, the equivalent current gain β of the bipolar transistor TBP can be expressed by β = β0 2 + 2 * β0. The equivalent base-emitter threshold voltage Vbe of the bipolar transistor TBP is the sum of the threshold voltages Vbe0 of the upstream and downstream transistors, i.e. Vbe = Vbe0 + Vbe0. For example, if β0 = 12, then β = 168, and if Vbe0 = 0.6 V, then Vbe = 1.2 V.

[0044] Reference is again made to Figure 1 and Figure 2 . The two base regions B1, B2 are formed in the same well PW of the three-well structure. The three-well structure, by containing a doped insulating well NISO-NW of opposite type (e.g. n-type) to the well PW, enables the electrical insulation of the well PW with a doping of the same type as the substrate PSUB (e.g. p-type). The PN junction formed with the opposite polarity to the insulating well NISO-NW thus enables the electrical insulation of the well PW from the substrate PSUB.

[0045] The well PW, containing the two base regions B1, B2, is thus surrounded laterally, i.e. in the x and y directions, by a doped annular well NW of the second type, and delimited in depth, i.e. in the vertical direction z, by a doped buried semiconductor layer NISO of the second type. The annular well NW extends in depth until it is connected to the buried semiconductor layer NISO.

[0046] The term "annular" refers to an annular form, not necessarily circular, i.e. a geometric region bounded by an inner and an outer perimeter which are parallel to each other. In the above view Figure 2 , the annular form of the well NW corresponds to a substantially square frame.

[0047] In addition, both the buried semiconductor region NISO and the doped ring well NW of the second type form a common collector region C, and a highly doped contact region C+ is formed on the front surface of the ring well NW (in the xy plane), which makes it possible to connect the metal terminal of the collector C.

[0048] To electrically insulate the first base region B1 contained in the well PW and the second base region B2 also contained in the well PW, the bipolar transistor includes a vertical gate structure SGV that extends vertically through the semiconductor well PW between the base regions B1 and B2 to the buried semiconductor layer NISO.

[0049] The vertical grid structure SGV includes trenches filled with a conductive material GV, which is electrically insulated from the bottom and sides of the trench by a dielectric shell OX.

[0050] This type of vertical gate structure SGV corresponds to the vertical gate structure of buried transistors, which are specifically used as non-volatile memory cells (CELs) in integrated circuits (see...). Figure 9 The access transistor TA in ) (see Figure 9 ).

[0051] Therefore, the vertical gate structure SGV can be advantageously manufactured "freely" by combining the corresponding manufacturing steps of the memory cell CEL. The vertical gate structure SGV will thus have the same structure (i.e., the same layout and the same material) and the same dimensions (specifically, the depth) as the gate of a buried access transistor with a vertical gate TA (see [reference]). Figure 9 ).

[0052] First alternative ( Figure 1 (Not explicitly shown in the diagram) In this case, the trench filled with conductive material GV has a depth that extends vertically through the well PW until it reaches or penetrates the buried semiconductor layer NISO. In this case, the dielectric shell OX and the conductive material GV maintained at a floating potential allow the first base region B1 and the second base region B2 to be electrically insulated from each other.

[0053] In the second alternative (such as) Figure 1 and Figure 2 As shown, the trench filled with conductive material GV has a depth that extends vertically into the well PW but does not reach the buried semiconductor region NISO. However, the vertical gate structure SGV may include an implantation region NIMP at and near the bottom of the trench (e.g., extending from the bottom of the trench), which is doped with a second type and connected to the buried semiconductor layer NISO.

[0054] Therefore, the implanted region NIMP occupies the space left between the bottom of the trench and the buried semiconductor layer NISO in the semiconductor well PW containing the base region, and enables electrical insulation between the two base regions B1 and B2.

[0055] This second alternative specifically corresponds to the case of co-integration using buried access transistors (TAs) with vertical gates having non-volatile memory cells (CELs) (see [reference]). Figure 9 ).

[0056] Therefore, the vertical gate structure SGV extends vertically from the front surface FA to the semiconductor well PW and then to the buried semiconductor layer NISO (visible in...). Figure 1 ).

[0057] Longitudinally, that is, in the planar direction of the front surface FA, for example, the y-direction, the vertical gate structure SGV extends radially from one edge of the annular well NW to the other edge (visible in... Figure 2 ).

[0058] Therefore, the vertical gate structure (SGV) occupies a very small space in the well PW, allowing the two base regions B1 and B2 in the same well PW to be insulated from each other. This enables the formation of two transistors arranged in a Darlington configuration in a region corresponding to the conventional design of a single bipolar transistor.

[0059] Finally, the second type of doped first emitter region E1 is located in the first base region B1, and the second type of doped second emitter region E2 is located in the second base region B2.

[0060] For example, conductor track M1, formed by metal tracks in the metal layer of the interconnect portion of integrated circuit CI, can form a Darlington configuration by electrically coupling a first emitter region E1 (e.g., an "upstream" transistor belonging to a Darlington configuration) to a second base region B2 (e.g., a "downstream" transistor belonging to a Darlington configuration).

[0061] The contact regions B1+ and B2 of the emitter regions E1 and E2, and the contact region C+ of the respective base regions B1 and B2, and the common collector region C are locally formed at the front surface FA in the opening of the lateral insulating region STI by highly concentrated dopant implantation.

[0062] For example, the transverse insulation zone STI is a standard shallow trench insulation (STI) design, which improves readability. Figure 2 These designs are not shown in the top view.

[0063] In addition, as described below, combined Figures 5 to 9 The fabrication of bipolar transistors (TBPs) can be integrated with other fabrication steps of non-volatile memory cells (CELs).

[0064] On the one hand, co-integration has the economic advantage of manufacturing bipolar transistors (TBPs) without the need for additional steps, i.e., without additional costs.

[0065] On the other hand, the co-integration with the non-volatile memory technology makes it possible to improve the performance of the bipolar transistor TBP, in addition to the quadratic increase of the current gain β of the Darlington configuration.

[0066] Indeed, the current gain β0 of one of the two transistors of the Darlington configuration can be expressed as a function of where μ n is the mobility of the n-type carriers, μ P is the mobility of the p-type carriers, W b is the width of the base region, N e is the dopant concentration of the emitter region, N b is the dopant concentration of the base region.

[0067] In other words, the current gain β0 is inversely proportional to the doping concentration of the base region N b and inversely proportional to the width of the base region W b (emitter-collector distance).

[0068] In the embodiment of the bipolar transistor TBP as shown in Figure 1 , the width W b of the base substantially corresponds to the depth of the well PW, i.e. the distance between the buried semiconductor layer NISO and the front surface FA.

[0069] However, the depth of the memory cell well is generally less than the depth of the three-well of the other type of embodiment, in particular due to the size of the vertical gate region of the access transistor. Indeed, a second depth implantation of the buried semiconductor layer is performed above the buried semiconductor layer NISO. In the representation of the figures, this second buried semiconductor layer belongs to the layer NISO. Moreover, the dopant concentration of the memory cell well is generally lower than the concentration in the three-well of the other embodiment, in particular to increase the voltage resistance of the PN junction formed with the well.

[0070] Thus, by reducing the width W b of the base and by reducing the concentration of the base dopant N b due to the co-integration with the memory cell forming the CEL, the current gain β0 of each of the two transistors of the Darlington configuration is increased.

[0071] For example, in the case of co-integration with the memory cell CEL, the current gain β0 can be substantially 12, representing more than a factor 2 of the current gain of a bipolar transistor typically co-integrated with CMOS (Complementary Metal Oxide Semiconductor) logic transistors.

[0072] As shown in Figure 3 , the equivalent current gain β of the bipolar transistor TBP benefits proportionally and quadratically from this gain, which can be 30 times the current gain of a conventional bipolar transistor as described above.

[0073] Figures 1 to 3 The value of the current gain β ~ 170 of the bipolar transistor TBP shown can be obtained with a Darlington configuration of three standard bipolar transistors, each with a current gain substantially equal to 5 and each with the same size of the bipolar transistor TBP. Therefore, the base-emitter threshold voltage of the Darlington configuration with three conventional transistors is 3*0.6V = 1.8V.

[0074] Therefore, with the bipolar transistor TBP described in relation to Figures 1 to 3 the size of such a standard design can be divided by 3, while limiting the base-emitter threshold voltage Vbe to 1.2V.

[0075] In addition to the direct advantage of reducing the size of the bipolar transistor TBP, this has an advantage in terms of reliability, in particular in terms of transistor matching. In fact, the matching error can be the result of the distance of the corresponding transistors from the position; however, having three times fewer transistors in a group also makes it possible to reduce the distance between the most distant transistors in the group, thus improving the matching.

[0076] In particular, the reference voltage generation circuit that is independent of temperature requires a high current gain and is sensitive to matching errors.

[0077] Reference is made in this regard to Figure 4 which shows a circuit BGC (typically a bandgap voltage generator circuit) suitable for generating a voltage that is independent of temperature. The circuit BGC comprises two input branches of an adder ADD, each branch comprising a bipolar transistor. The first branch comprises a current generator that injects a current into the collector of a bipolar transistor connected to a diode, the emitter being grounded. Therefore, the base-emitter voltage VBE of this transistor provides a signal that decreases with temperature at one input of the adder ADD. A temperature proportional current generator circuit VPTAT Gen generates a signal that increases with temperature at the other input of the adder ADD. The sum of the two signals V BE , KV T is substantially constant with temperature and constitutes a reference voltage signal V REF (T) that is independent of temperature.

[0078] In a circuit BGC of this type, the low current gain β has a considerable influence on accuracy, precision and variation with temperature.

[0079] Therefore, the bipolar transistor TBP as described in relation to Figures 1 to 3 is advantageously used in a reference voltage generation circuit BGC that is independent of temperature.

[0080] Figures 5 to 9 is shown in the above combination Figures 1 to 3The steps of the example of the method of manufacturing of the bipolar transistor TBP and the results of the steps.

[0081] In this example, the bipolar transistor TBP is manufactured in full co-integration with the manufacturing steps of the memory cells CEL manufactured in the same semiconductor substrate PSUB, for example in a doped silicon of a first type (typically, p-type).

[0082] Figure 5 The result 500 of the step of manufacturing of the shallow isolation trenches STI is shown, which typically comprises etching from the front surface FA of the PSUB substrate an opening called "trench" and filling the trench with a dielectric material such as silicon oxide.

[0083] The result 500 also shows the result of the implantation steps of the "triple-well" type structure in the bipolar transistor portion TBP and in the memory cell portion CEL.

[0084] The implantation steps of the "triple-well" thus comprise:

[0085] a deep implantation of the buried semiconductor layer NISO of the common collector region C of the bipolar transistor TBP, while a deep implantation is performed of the buried semiconductor layer NISOnvm, to form a source plane extending below the well PWnvm containing the memory cell CEL. The buried semiconductor layers NISO, NISOnvm are doped of a second type opposite to the first type, for example n-type;

[0086] a ring-shaped well NW of the common collector region C of the bipolar transistor is implanted, while a ring-shaped well NWnvm is implanted around the well containing the memory cell PWnvm. The ring-shaped wells NW, NWnvm are implanted with an energy such that a depth of the semiconductor layer NISO is reached, so as to form an insulating structure continuous with said buried semiconductor layers NISO, NISOnvm. The ring-shaped wells NW, NWnvm are of a second type of doping, for example n-type; and

[0087] the implantation of the doped semiconductor well PW of the first type is intended to contain the base regions B1, B2 (see Figure 6 ), while the well of the memory cell PWnvm is implanted, intended to contain in particular the channel regions of the floating gate transistors FGT1, FGT2 (see Figure 9 ).

[0088] In particular, the dopant of the doped well PW, PWnvm of the first type, respectively for containing the base regions B1, B2 and the memory cell CEL, has a concentration of 2 x 1018 12 cm -3 and 3 x 1018 13 cm -3between 300 nanometers and 700 nanometers. This relatively small depth is provided in order to limit the etching time of the trench TR, TRta to approximately this depth, which advantageously makes it possible to increase the current gain β of the bipolar transistor TBP.

[0089] Furthermore, the depth of the well PW, PWnvm is delimited by the vertical position of the buried semiconductor layer NISO, NISOnvm, for example, its depth is between 300 nanometers and 700 nanometers. This relatively small depth is provided in order to limit the etching time of the trench TR, TRta to approximately this depth, which advantageously makes it possible to increase the current gain β of the bipolar transistor TBP. Figure 6

[0090] Figure 6 The result of the etching step 600 for opening the trench TR, TRta is shown, in which a vertical gate structure electrically insulating the first base region B1 and the second base region B2 of the bipolar transistor and a vertical gate of the access transistor TA of the memory cell CEL are formed. Figure 9

[0091] The implantation is also performed at and near (for example, from the bottom) the trench TR, TRta in the respective well PW, PWnvm. Thus, the respective implantation region NIMP, NIMPta doped with the second type, for example, n-type, occupies the space between the bottom of the trench TR, TRta and the buried semiconductor layer NISO, NISOnvm.

[0092] In particular, the implantation of the implantation region NIMPta at the bottom of the trench TRta of the memory cell CEL makes it possible to form a source region in contact with the source plane NISOnvm, and this advantageously makes it possible to ensure the electrical insulation between the two base regions B1, B2 in the well PW of the bipolar transistor TBP.

[0093] On the one hand, in the representation of Figure 6 The trench TR, TRta is represented with the same depth in the representation of the bipolar transistor TBP and of the memory cell CEL. But strictly speaking, the trench TR of the bipolar transistor TBP is slightly deeper than the trench TRta of the memory cell CEL. Indeed, the trench TR of the bipolar transistor TBP passes through the lateral insulating region STI, and the anisotropic etching used to form the trench TR, TRta can be faster in the dielectric material of the lateral insulating region STI than in the crystalline silicon of the well PWnvm.

[0094] On the other hand, in the well PW of the bipolar transistor TBP, the implantation region NIMP initially starting from the bottom of the trench TR presents, after diffusion, so as to extend from the bottom of the shallow insulating trench STI to the buried semiconductor layer NISO.

[0095] ​​This effectively provides electrical insulation between the first base region B1 and the second base region B2. However, in case the deeper depth of the trench TR extends to the buried semiconductor layer NISO region, the structure within the trench TR, i.e. in particular the dielectric shell OX formed in step 700 described in the Figure 7

[0096] Figure 7 A step 700 is shown which comprises forming a dielectric shell OX on the bottom and the side of the trench TR of the bipolar transistor TBP, while forming the gate dielectric shell of the OXta of the access transistor of the memory cell CEL.

[0097] The step 700 further comprises filling the excess trench TR, TRta with a conductive material P0, e.g. polysilicon.

[0098] Figure 8 A result 800 is shown which typically results from a chemical mechanical polishing to remove the excess conductive material P0, i.e. the portion of the conductive material P0 which covers the front surface FA of the semiconductor substrate PSUB.

[0099] Furthermore, a floating gate structure SGF1, SGF2 is formed in the memory cell portion CEL.

[0100] The floating gate structure SGF1, SGF2 typically comprises a tunnel dielectric layer on the front surface FA of the well PWnvm, a floating gate region on the tunnel dielectric, an intergate dielectric layer on the floating gate and a control gate region on the intergate dielectric layer.

[0101] Figure 9 A result 900 is shown which results from the step of simultaneously implanting a second type dopant, e.g. n-type, an emitter region E1, E2, a collector contact region C+ into the openings of the shallow isolation trenches STI provided for this purpose, while self-aligning the source region S and the drain region D on both sides of the floating gate structure FGT1, FGT2 and the source plane contact region SL NISOnvm.

[0102] Furthermore, an implantation of a first type dopant, e.g. p-type, forms a base region contact region B1+, B2+ in the openings of the shallow isolation trenches STI provided for this purpose in the respective base region B1, B2, while implanting a substrate contact region P+ in the openings of the shallow isolation trenches STI provided for this purpose in the substrate PSUB.

[0103] ​Furthermore, contact pillars are made on the heavily doped regions B1+, B2+, C+, E1, E2, in order to couple, for example, the first emitter region E1 and the second base region B2+ by means of a metal track M1; and to form a base terminal B of the bipolar transistor TBP on the first base region B1+, an emitter terminal E of the bipolar transistor TBP on the second emitter region E2, and a collector terminal C of the bipolar transistor TBP on the collector contact region C+.

[0104] At the same time, contact pillars are formed in the memory cell CEL in order to form bit line terminals BL1, BL2 on the drain region D, word line terminals WL on the conductive gates of the access transistors TA, control gate line terminals CGL1, CGL2 on the control gates of the floating gate structures SGF1, SGF2, and source plane terminals SL on the source plane contact regions NWnvm, NISOnvm.

Claims

1. An integrated circuit comprising a Darlington bipolar transistor disposed in and / or on a first type of doped semiconductor substrate, the Darlington bipolar transistor comprising: A common collector region for the first and second transistors of the Darlington bipolar transistor, the common collector region comprising a second type of buried semiconductor layer in the doped semiconductor substrate, opposite to the first type, and a second type of doped ring well connecting the buried semiconductor layer; The first type of doped semiconductor well is surrounded by the ring well and defined by the buried semiconductor layer; A vertical structure extends vertically through the doped semiconductor well to divide the doped semiconductor well into a first base region for the first transistor, the first base region being electrically insulated from a second base region for the second transistor. The second type of doped first emitter region for the first transistor is located in the first base region; The second type of doped second emitter region for the second transistor is located in the second base region; as well as Conductor tracks are used to electrically couple the first emitter region of the first transistor to the second base region of the second transistor.

2. The integrated circuit of claim 1, wherein the vertical structure includes a trench filled with a conductive material, the conductive material being electrically insulated by a dielectric shell on the bottom and sides of the trench.

3. The integrated circuit of claim 2, wherein the vertical structure further comprises an implantation region located in the doped semiconductor well comprising the first base region and the second base region doped by the second type, and occupying the space between the bottom of the trench and the buried semiconductor layer.

4. The integrated circuit of claim 1, wherein the vertical structure extends vertically from the front surface of the doped semiconductor well, which includes the first base region and the second base region, and extends longitudinally from one edge of the doped annular well surrounding the doped semiconductor well to the other edge in a planar direction of the front surface.

5. The integrated circuit of claim 1 further comprises a non-volatile memory cell, the non-volatile memory cell comprising a floating gate transistor and a buried access transistor having a vertical gate, wherein the doped semiconductor well containing the first base region and the second base region has the same depth, the same composition and the same dopant concentration as the well of the non-volatile memory cell containing the channel region of the floating gate transistor.

6. The integrated circuit according to claim 5, wherein: The buried semiconductor layer of the common collector region has the same composition and the same depth as the buried semiconductor layer of the source plane extending below the well of the non-volatile memory cell; The doped ring well of the common collector region has the same composition and structure as the ring well surrounding the well of the non-volatile memory cell, and allows electrical contact with the buried semiconductor layer forming the source plane; and The vertical structure of the electrically insulating first base region and the second base region has the same structure and the same dimensions as the vertical gate of the buried access transistor.

7. The integrated circuit of claim 1, wherein the Darlington bipolar transistor is a circuit element of a temperature-independent reference voltage generation circuit.

8. A method for fabricating an integrated circuit in a semiconductor substrate doped with a first type, the method comprising: Manufacturing Darlington bipolar transistors includes: By implanting a buried semiconductor layer doped with a second type opposite to the first type into the semiconductor substrate, and implanting a doped ring well of the second type connected to the buried semiconductor layer, a common collector region for the first transistor and the second transistor of the Darlington bipolar transistor is formed. The first type of doped semiconductor well is injected into the region surrounded by the annular well and defined by the buried semiconductor layer; A vertical structure is formed, which extends vertically through the doped semiconductor well to the buried semiconductor layer to electrically insulate the first base region of the first transistor and the second base region of the second transistor; Implant a first emitter region of the second type, which is used for the first transistor, into the first base region; Implanting a second emitter region of the second type for the second transistor into the second base region; and A conductor track is formed, which is electrically coupled to the first emitter region of the first transistor and the second base region of the second transistor.

9. The method of claim 8, wherein forming the vertical structure comprises: Etched trenches; A dielectric shell is formed at the bottom and sides of the trench; as well as The trench is filled with a conductive material.

10. The method of claim 9, wherein forming the vertical structure further comprises: The second type of doped region is injected into the doped semiconductor well to occupy the space between the bottom of the trench and the buried semiconductor layer.

11. The method of claim 8, wherein the vertical structure extends vertically from the front surface of the doped semiconductor well into the doped semiconductor well, and extends longitudinally from one edge of the doped annular well surrounding the doped semiconductor well to the other edge in a planar direction of the front surface.

12. The method of claim 8, further comprising manufacturing a non-volatile memory cell, the non-volatile memory cell comprising a floating-gate transistor and a buried access transistor having a vertical gate: The implantation of the doped semiconductor well is performed simultaneously with the implantation of the well containing the channel region of the non-volatile memory cell.

13. The method according to claim 12, wherein: The implantation of the buried semiconductor layer in the common collector region is performed simultaneously with the implantation of the buried semiconductor layer extending beneath the well of the non-volatile memory cell; The doped ring well implanted into the common collector region is performed simultaneously with the implantation of the ring well surrounding the well of the non-volatile memory cell, the ring well allowing electrical contact with the buried semiconductor layer forming the source plane; as well as The formation of the vertical structure that electrically insulates the first base region and the second base region is performed simultaneously with the formation of the vertical gate of the buried access transistor.

14. An integrated circuit, comprising: Type 1 doped semiconductor substrate; A second type of buried semiconductor layer, opposite to the first type in the doped semiconductor substrate; The second type of doped ring well in contact with the buried semiconductor layer; The doped ring well surrounds the first type of doped semiconductor well; An insulating structure extends vertically through the doped semiconductor well to divide the doped semiconductor well into a first region of the first type that is electrically insulated from a second region of the first type. The first doped region of the second type is located in the first region; The second doped region of the second type is located in the second region; The first doped region is electrically connected to the second region; The integrated circuit is a Darlington bipolar transistor, including a first transistor and a second transistor. The first transistor and the second transistor have a common collector formed by the buried semiconductor layer and the doped ring well, a first base of the first transistor formed by the first region, a second base of the second transistor formed by the second region, a first emitter of the first transistor formed by the first doped region, and a second emitter of the second transistor formed by the second doped region.

15. The integrated circuit of claim 14, wherein the insulating structure includes trenches.

16. The integrated circuit of claim 15, wherein the trench is filled with a conductive material, the conductive material being electrically insulated by a dielectric shell on the bottom and sides of the trench.

17. The integrated circuit of claim 16, wherein the insulating structure further comprises an implantation region doped with the second type in the doped semiconductor well, the implantation region occupying the space between the bottom of the trench and the buried semiconductor layer.

18. The integrated circuit of claim 14, wherein the insulating structure extends vertically from the front surface of the doped semiconductor well in the doped semiconductor well and extends radially from one edge of the doped annular well surrounding the doped semiconductor well to another edge in a planar direction of the front surface.

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