Display panel, manufacturing method thereof and display device

Abstract

The display panel, a manufacturing method thereof and a display device belong to the technical field of display. The display panel comprises: a substrate, comprising a display area and a peripheral area located at the periphery of the display area; a first conductive layer, located on one side of the substrate, and the orthographic projection of the first conductive layer on the substrate is at least partially located in the peripheral area; a transistor device layer, located on the side of the first conductive layer away from the substrate, and the transistor device layer comprises transistor devices located in the display area and signal lines located in the peripheral area; and a second conductive layer, located on the side of the transistor device layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate is located in the peripheral area; wherein the second conductive layer is connected with the signal lines, and the second conductive layer is connected with the first conductive layer. The display panel can effectively enhance the shielding effect of the electric charge.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] Currently, with the development of OLED (Organic Light-Emitting Diode) display technology, consumers have put forward more stringent requirements for AMOLED display products, and more and more customers are beginning to pay attention to the display status of the screen under electrostatic testing.

[0003] The information disclosed in the background section is only for enhancing the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display panel and its manufacturing method, as well as a display device, which can effectively shield electrostatic charges.

[0005] To achieve the above-mentioned objectives, the present disclosure adopts the following technical solution:

[0006] According to a first aspect of this disclosure, a display panel is provided, comprising:

[0007] The substrate includes a display area and a peripheral area located around the display area;

[0008] A first conductive layer is disposed on one side of the substrate, and the orthographic projection of the first conductive layer on the substrate is at least partially located in the peripheral region.

[0009] A transistor device layer is disposed on the side of the first conductive layer away from the substrate, and the transistor device layer includes transistor devices located in the display area and signal lines located in the peripheral area;

[0010] A second conductive layer is disposed on the side of the transistor device layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate is located in the peripheral region.

[0011] The second conductive layer is connected to the signal line, and the second conductive layer is also connected to the first conductive layer.

[0012] In one exemplary embodiment of this disclosure, the display panel further includes:

[0013] A shielding metal layer is disposed on the side of the transistor device layer away from the substrate, and the orthogonal projection of the shielding metal layer on the substrate at least covers the orthogonal projection of the transistor device located in the display area on the substrate.

[0014] In an example embodiment of the present disclosure, a projection of the shielding metal layer on the substrate substrate at least partially locates in the peripheral region;

[0015] A projection of the shielding metal layer on the substrate substrate at least partially overlaps with a projection of the second conductive layer on the substrate substrate;

[0016] Or a projection of the shielding metal layer on the substrate substrate at least partially overlaps with a projection of the signal line on the substrate substrate.

[0017] In an example embodiment of the present disclosure, a projection of the second conductive layer on the substrate substrate at least partially overlaps with a projection of the signal line on the substrate substrate.

[0018] In an example embodiment of the present disclosure, a projection of the second conductive layer on the substrate substrate is a closed ring structure around the display region.

[0019] In an example embodiment of the present disclosure, the signal line is a power voltage line.

[0020] In an example embodiment of the present disclosure, the display panel further comprises:

[0021] A first electrode layer is arranged on a side of the transistor device layer away from the substrate substrate, and a projection of the first electrode layer on the substrate substrate is located in the display region.

[0022] A light-emitting functional layer is arranged on a side of the first electrode layer away from the substrate substrate.

[0023] A second electrode layer is arranged on a side of the light-emitting functional layer away from the substrate substrate.

[0024] Wherein, the second conductive layer is arranged in the same layer as the first electrode layer, and a projection of the second conductive layer on the substrate substrate does not overlap with a projection of the first electrode layer on the substrate substrate.

[0025] In an example embodiment of the present disclosure, the display panel further comprises:

[0026] A third conductive layer is arranged on a side of the transistor device layer away from the substrate substrate, and a projection of the third conductive layer on the substrate substrate at least partially locates in the display region.

[0027] A planarization layer is arranged on a side of the third conductive layer away from the substrate substrate.

[0028] A first electrode layer is disposed on a side of the planarization layer distal from the substrate, and a projection of the first electrode layer on the substrate is located in the display area.

[0029] A light-emitting functional layer is disposed on a side of the first electrode layer distal from the substrate.

[0030] A second electrode layer is disposed on a side of the light-emitting functional layer distal from the substrate.

[0031] The second conductive layer and the third conductive layer are disposed in the same layer, and a projection of the second conductive layer on the substrate does not overlap a projection of the third conductive layer on the substrate.

[0032] In an example embodiment of the present disclosure, the second electrode layer is multiplexed as the shielding metal layer.

[0033] In an example embodiment of the present disclosure, the display panel further comprises:

[0034] An encapsulation layer is disposed on a side of the transistor device layer distal from the substrate.

[0035] A touch electrode layer is disposed on a side of the encapsulation layer distal from the substrate, and the touch electrode layer comprises a plurality of touch electrodes located in the display area.

[0036] The second conductive layer and the touch electrode layer are disposed in the same layer, and a projection of the second conductive layer on the substrate does not overlap a projection of the touch electrode layer on the substrate.

[0037] In an example embodiment of the present disclosure, the transistor device layer comprises:

[0038] An active layer is disposed on a side of the first conductive layer distal from the substrate, and the active layer comprises an active region of a transistor device.

[0039] A first insulating layer is disposed on a side of the active layer distal from the substrate, and the first insulating layer covers a side surface of the active layer distal from the substrate.

[0040] A first gate metal layer is disposed on a side of the first insulating layer distal from the substrate, and the first gate metal layer comprises a gate of a transistor device.

[0041] A first interlayer dielectric layer is disposed on a side of the first gate metal layer distal from the substrate.

[0042] A source-drain metal layer is disposed on a side of the first interlayer dielectric layer distal from the substrate, and the source-drain metal layer is connected to the active layer.

[0043] The signal line is arranged in the same layer as the source-drain metal layer.

[0044] In an exemplary embodiment of the present disclosure, the display area includes a first side edge and a second side edge arranged opposite along a first direction, and a third side edge and a fourth side edge arranged opposite along a second direction;

[0045] The peripheral area includes a first sub-area connected to the first side edge, a second sub-area connected to the second side edge, a third sub-area connected to the third side edge, and a fourth sub-area connected to the fourth side edge;

[0046] The first conductive layer has a projection on the substrate substrate at least partially located in the first sub-area and the second sub-area;

[0047] The signal line has a projection on the substrate substrate at least partially located in the third sub-area or the fourth sub-area.

[0048] According to a second aspect of the present disclosure, a manufacturing method of a display panel is provided, comprising:

[0049] Providing a substrate substrate including a display area and a peripheral area located peripherally to the display area;

[0050] Forming a first conductive layer on one side of the substrate substrate, the first conductive layer having a projection on the substrate substrate at least partially located in the peripheral area;

[0051] Forming a transistor device layer on a side of the first conductive layer away from the substrate substrate, the transistor device layer including transistor devices located in the display area and signal lines located in the peripheral area;

[0052] Forming a second conductive layer on a side of the transistor device layer away from the substrate substrate, the second conductive layer having a projection on the substrate substrate located in the peripheral area;

[0053] The second conductive layer is connected to the signal line, and the second conductive layer is connected to the first conductive layer.

[0054] According to a third aspect of the present disclosure, a display device is provided, including the display panel according to the first aspect.

[0055] The display panel provided by the present disclosure comprises a substrate, a first conductive layer, a transistor device layer and a second conductive layer, and the first conductive layer and the second conductive layer are respectively located on both sides of the transistor device layer. The transistor device layer comprises a transistor device located in a display area and a signal line located in a peripheral area, and the second conductive layer is connected with the signal line and the first conductive layer, so that the three can form a conductor shell with a cavity around the transistor device in the display area, and the shielding effect on the electric charge can be effectively enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0056] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0057] Figure 1 is a schematic diagram of the principle of the influence of static electricity test on the transistor characteristics of the display panel in the prior art;

[0058] Figure 2 is a diagram of the movement of electric charges in the related art in which a shielding structure is arranged at the same layer position as the first gate metal layer;

[0059] Figure 3 is a schematic diagram of the structure of the substrate in the example embodiment of the present disclosure;

[0060] Figure 4 is a schematic diagram of the display panel in the example embodiment of the present disclosure;

[0061] Figure 5 is Figure 4 is a cross-sectional view in the A-A' direction;

[0062] Figure 6 is Figure 4 is a cross-sectional view in the B-B' direction;

[0063] Figure 7 is Figure 4 is a cross-sectional view in the C-C' direction;

[0064] Figure 8 is a schematic diagram of the shielding of electric charges of the display panel of the present disclosure;

[0065] Figure 9 is a comparison diagram of the shielding of electric charges of the display panel of the present disclosure and the shielding of electric charges in the related art;

[0066] Figure 10 is Figure 4 is another cross-sectional view in the A-A' direction;

[0067] Figure 11 is Figure 4 is another cross-sectional view in the B-B' direction.

[0068] The main element reference signs in the drawings are explained as follows:

[0069] 1-Substrate; 10-Display area; 11-Peripheral area; 111-First sub-region; 112-Second sub-region; 113-Third sub-region; 114-Fourth sub-region; 2-First conductive layer; 3-Transistor device layer; 31-Active layer; 32-First insulating layer; 33-First gate metal layer; 34-Second insulating layer; 35-Second gate metal layer; 36-First interlayer dielectric layer; 37-Source / drain metal layer; 38-Second active layer; 41-Passivation layer; 42-Planarization layer; 01-Second conductive layer; 02-Signal line; 5-Third conductive layer; 61-First electrode layer; 62-Light-emitting functional layer; 63-Second electrode layer; 64-Pixel definition layer; 641-Opening; 6-Light-emitting device; 60-Shielding metal layer; 71-First inorganic layer; 72-Organic layer; 73-Second inorganic layer; 8-Touch electrode layer; 91-First adhesive layer; 92-Polarizer; 93-Optical adhesive layer; 94-Cover plate; 95-Second interlayer dielectric layer; 03-Buffer layer. Detailed Implementation

[0070] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth to give a full understanding of embodiments of this disclosure.

[0071] For clarity, the thickness of regions and layers may be exaggerated in the figures. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed descriptions will be omitted.

[0072] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical concept of this disclosure.

[0073] When a structure is "on" other structures, it may mean that the structure is integrally formed on other structures, or that the structure is "directly" set on other structures, or that the structure is "indirectly" set on other structures through another structure.

[0074] The terms "one", "a", "said" are used to denote the presence of one or more elements / components / etc.; the terms "including" and "having" are used to mean open- ended including in order to permit additional elements / components / etc. to be present in addition to those listed; the terms "first", "second", etc. are used only as labels and do not limit the number of objects.

[0075] The electrostatic field test is a key project for evaluating the quality of OLED products. Currently, the OLED display panel has the problem of brightening in the electrostatic field (copper rod) test. As shown in Figure 1 The electrostatic field test produces a large amount of electric charge, in which the charge in the display area is shielded by the second electrode layer 63 (cathode layer) in the transmission process, and the charge outside the display area is transmitted to the substrate 1 through the cutting edge film layer of the panel, thereby affecting the thin film transistor characteristics in the pixel single channel of the display panel, resulting in brightening of the display panel. In addition, the substrate 1 will be induced to charged ions under the condition of continuous bias, thereby affecting the transistor characteristics and causing display differences in black and white areas. Figure 1 The buffer layer 03, the first insulating layer 32, the second insulating layer 34, the first interlayer dielectric layer 36, the polarizer 92, the optical adhesive layer 93, and the cover plate 94 and other film layers in the display panel are also shown in the figure. The distribution positions of the various film layers can refer to the film layer structure of the display panel in the prior art, and will not be described in detail here.

[0076] In the related art, some technicians coat silver paste on the back (non-light-emitting surface) of the display panel to guide the charge away, but this method has limited improvement effect and increases cost. In addition, as shown in Figure 2 Some other technicians set a shielding structure at the same layer position as the first gate metal layer 33 of the low-temperature polysilicon transistor in the display panel. However, this scheme can only shield the charge above the first gate metal layer 33 of the low-temperature polysilicon transistor, and cannot form an effective shielding effect on the oxide transistor located above the low-temperature polysilicon transistor.

[0077] As shown in Figures 3 to 7As shown, this embodiment of the present disclosure provides a display panel, including a substrate 1, a first conductive layer 2, a transistor device layer 3, and a second conductive layer 01. The substrate 1 includes a display area 10 and a peripheral area 11 located around the display area 10. The first conductive layer 2 is disposed on one side of the substrate 1, and the orthographic projection of the first conductive layer 2 on the substrate 1 is at least partially located in the peripheral area 11. The transistor device layer 3 is disposed on the side of the first conductive layer 2 away from the substrate 1, and the transistor device layer 3 includes a transistor device located in the display area 10 and a signal line 02 located in the peripheral area 11. The second conductive layer 01 is disposed on the side of the transistor device layer 3 away from the substrate 1, and the orthographic projection of the second conductive layer 01 on the substrate 1 is located in the peripheral area 11. The second conductive layer 01 is connected to the signal line 02 and is also connected to the first conductive layer 2.

[0078] The display panel disclosed herein includes a substrate 1, a first conductive layer 2, a transistor device layer 3, and a second conductive layer 01. The first conductive layer 2 and the second conductive layer 01 are located on opposite sides of the transistor device layer 3. The transistor device layer 3 includes transistor devices located in the display area 10 and signal lines 02 located in the peripheral area 11. The second conductive layer 01 is connected to the signal lines 02 and the first conductive layer 2. Thus, the three components can form a cavity-type conductive shell around the transistor devices in the display area 10, which can effectively enhance the shielding effect against charges.

[0079] Furthermore, under continuous bias voltage, the substrate 1 can generate charged ions, which can affect the characteristics of the transistor devices, leading to display differences in black and white areas and causing image retention. In this disclosure, the first conductive layer 2 is disposed between the transistor device layer 3 and the substrate 1, which can shield the influence of the charge from the substrate 1 on the transistor devices and improve the image retention problem of the display panel.

[0080] The components of the display panel provided in this embodiment will now be described in detail with reference to the accompanying drawings:

[0081] like Figures 3 to 7 As shown, this disclosure provides a display panel, which may be an OLED (Organic Light-Emitting Diode) display panel. The display panel includes a substrate 1, a first conductive layer 2, a transistor device layer 3, and a second conductive layer 01.

[0082] like Figure 3As shown, the substrate 1 can be an inorganic material substrate 1 or an organic material substrate 1. For example, in one embodiment of this disclosure, the material of the substrate 1 can be a glass material such as soda-lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. The substrate 1 can also be a flexible substrate 1. For example, in one embodiment of this disclosure, the material of the substrate 1 can be polyimide (PI). The substrate 1 can also be a composite of multiple materials. For example, in one embodiment of this disclosure, the substrate 1 can include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked sequentially.

[0083] The substrate 1 includes a display area 10 and a peripheral area 11 located around the display area 10. The display area 10 can be equipped with pixel circuits, light-emitting devices, and other structures to display an image. The peripheral area 11 can be equipped with peripheral circuits to drive the pixel circuits located in the display area 10. The display area 10 includes a first side and a second side disposed opposite to each other along a first direction X, and a third side and a fourth side disposed opposite to each other along a second direction Y. The first direction X and the second direction Y are approximately perpendicular, the first side and the second side are approximately parallel, and the third side and the fourth side are approximately parallel. The peripheral area 11 includes a first sub-area 111 connected to the first side, a second sub-area 112 connected to the second side, a third sub-area 113 connected to the third side, and a fourth sub-area 114 connected to the fourth side. The first sub-area 111, the second sub-area 112, the third sub-area 113, and the fourth sub-area 114 of the peripheral area 11 can be smoothly connected. It should be noted that in this disclosure, the terms "perpendicular," "parallel," and "equal" refer to perpendicularity, parallelism, and equality within the range of process error, rather than absolute perpendicularity, parallelism, and equality. For example, the perpendicularity of the first direction X and the second direction Y can mean that the angle between the first direction X and the second direction Y is within the range of 90° ± 5°.

[0084] like Figure 4 , Figure 5 and Figure 6 As shown, Figure 5 yes Figure 4 Cross-sectional view along the A-A' direction. Figure 6 yes Figure 4 A cross-sectional view along the B-B' direction shows that the first conductive layer 2 is disposed on one side of the substrate 1, and the orthogonal projection of the first conductive layer 2 on the substrate 1 is at least partially located in the peripheral region 11. The first conductive layer 2 may be made of a metallic material or a metallic alloy material, and this disclosure does not limit the specific materials used.

[0085] like Figure 3 , Figure 4 and Figure 6As shown, in some embodiments of the present disclosure, the orthogonal projection of the first conductive layer 2 on the substrate 1 can cover the display area 10. Further, the orthogonal projection of the first conductive layer 2 on the substrate 1 is at least partially located in the first sub-area 111 and the second sub-area 112. That is, the first conductive layer 2 extends along the first direction X, and part of the area thereof is located in the peripheral area 11. Of course, the orthogonal projection of the first conductive layer 2 on the substrate 1 can also be at least partially located in the third sub-area 113 and / or the fourth sub-area 114, or not located in the third sub-area 113 and the fourth sub-area 114, which is not limited in the present disclosure. The first conductive layer 2 can serve as a light shielding layer of the display panel.

[0086] As shown, Figure 3 , Figure 4 , Figure 5 , Figure 7 , the transistor device layer 3 is located on the side of the first conductive layer 2 away from the substrate 1, and the transistor device layer 3 includes transistor devices located in the display area 10 and signal lines 02 located in the peripheral area 11. Among them, Figure 7 is a cross-sectional view of the display area 10 of the display panel, and the transistor devices located in the display area 10 can be used to form pixel circuits. In some embodiments, the transistor device layer 3 can also include transistor devices located in the peripheral area 11 to form peripheral circuits, such as gate drive circuits 001 and light-emitting control circuits 002.

[0087] In some embodiments of the present disclosure, the transistor device can be a top-gate structure or a bottom-gate structure. As shown, Figure 7As shown, the transistor device layer 3 includes the active layer 31, the first insulating layer 32, the first gate metal layer 33, the first interlayer dielectric layer 36, and the source-drain metal layer 37. The active layer 31 is disposed on the side of the first conductive layer 2 away from the substrate 1, and includes the active region of the transistor device. The first insulating layer 32 is disposed on the side of the active layer 31 away from the substrate 1, and covers the surface of the active layer 31 on the side away from the substrate 1. The first gate metal layer 33 is disposed on the side of the first insulating layer 32 away from the substrate 1, and includes the gate of the transistor device. The first interlayer dielectric layer 36 is disposed on the side of the first gate metal layer 33 away from the substrate 1. The source-drain metal layer 37 is disposed on the side of the first interlayer dielectric layer 36 away from the substrate 1, and is connected to the active layer 31. The source-drain metal layer 37 includes the source and the drain of the transistor device. Further, the transistor device layer 3 can also include the second gate metal layer 35 and the second insulating layer 34. The second gate metal layer 35 is disposed between the first gate metal layer 33 and the first interlayer dielectric layer 36, and the second insulating layer 34 is disposed between the first gate metal layer 33 and the second gate metal layer 35. The first gate metal layer 33 can also include the first plate of a capacitor, and the second gate metal layer 35 can include the second plate of the capacitor. Different numbers of transistor devices and capacitors can form different structures of pixel circuits. The pixel circuit can be a 7T1C, 7T2C, 6T1C, or 6T2C pixel circuit, and the structure thereof is not specially limited herein. Wherein, nTmC represents that a pixel circuit includes n transistors (denoted by the letter "T") and m capacitors (denoted by the letter "C").

[0088] As shown, Figure 5 The transistor device layer 3 also includes the signal line 02, which is located in the peripheral area 11. The signal line 02 can be used to transmit various signals, such as a clock signal, a power voltage signal, etc. In some embodiments of the present disclosure, the signal line 02 is a power voltage line, which can be used to transmit a power voltage Vdd or Vss. Thus, when the second conductive layer 01 is connected to the signal line 02, a stable voltage signal can be formed. The signal line 02 can be disposed in the same layer as the source-drain metal layer 37. In the present disclosure, the same layer refers to being made of the same material and by the same process.

[0089] As shown, Figure 3 and Figure 5 The distribution position of the signal line 02 can be set according to the actual requirements of the display panel. In an embodiment, the orthogonal projection of the signal line 02 on the substrate 1 is located in the third sub-area 113 or the fourth sub-area 114. For example, the fourth sub-area 114 also includes a binding area, and the orthogonal projection of the signal line 02 on the substrate 1 is located in the fourth sub-area 114.

[0090] As shown, Figure 4 , Figure 5 andFigure 7 As shown in the figure, in some embodiments of the present disclosure, the display panel further comprises a third conductive layer 5, a passivation layer 41 and a planarization layer 42. The third conductive layer 5 is arranged on the side of the transistor device layer 3 away from the substrate 1, and the passivation layer 41 is arranged between the transistor device layer 3 and the third conductive layer 5. The passivation layer 41 covers the surface of the transistor device layer 3, specifically, the passivation layer 41 covers the surface of the source-drain metal layer 37 away from the substrate 1. The planarization layer 42 is arranged on the side of the third conductive layer 5 away from the substrate 1.

[0091] As shown in the figure, Figure 5 and Figure 6 In some embodiments, the orthographic projection of the passivation layer 41 on the substrate 1 is at least partially located in the peripheral area 11, and there is a gap between the passivation layer 41 located in the peripheral area 11 and the passivation layer 41 located in the display area 10, so that the passivation layer 41 located in the peripheral area 11 forms a barrier portion to block the invasion of external moisture into the display area 10. In addition, the orthographic projection of the planarization layer 42 on the substrate 1 is at least partially located in the peripheral area 11, and there is a gap between the planarization layer 42 located in the peripheral area 11 and the planarization layer 42 located in the display area 10, and the planarization layer 42 located in the peripheral area 11 at least partially covers the barrier portion formed by the passivation layer 41, together with the passivation layer 41 to block the invasion of external moisture.

[0092] As shown in the figure, Figure 7 The display panel further comprises a first electrode layer 61, a light-emitting functional layer 62 and a second electrode layer 63. The first electrode layer 61 is arranged on the side of the transistor device layer 3 away from the substrate 1, specifically, the first electrode layer 61 can be arranged on the side of the planarization layer 42 away from the substrate 1, and the orthographic projection of the first electrode layer 61 on the substrate 1 is located in the display area 10. The first electrode layer 61 can be a single layer or a multi-layer structure, and its material can include one or more of conductive metal, metal oxide and alloy. In an embodiment, the first electrode layer 61 is made of transparent material, such as indium tin oxide (ITO), which has good conductivity and corrosion resistance.

[0093] The light-emitting functional layer 62 is arranged on the side of the first electrode layer 61 away from the substrate 1. The light-emitting functional layer 62 can include, in order from the side away from the substrate 1, a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer and an electron injection layer. The hole and the electron can be combined into an exciton in the light-emitting material layer, and the exciton can radiate photons to produce visible light. The specific light-emitting principle is not described here in detail.

[0094] The second electrode layer 63 is arranged on the side of the light-emitting functional layer 62 away from the substrate 1. The second electrode can be a single layer or a multi-layer structure, and its material can include one or more of conductive metal, metal oxide and alloy.

[0095] The display panel further comprises a pixel definition layer 64 disposed on the side of the first electrode layer 61 away from the substrate 1. The pixel definition layer 64 is provided with a plurality of openings 641, and the range defined by each opening 641 is the range of a light emitting device 6. The shape of the opening 641, i.e. the shape of the contour of the orthographic projection of the opening 641 on the driving backplane 1, can be a polygon, a smooth closed curve or other shape, and the smooth closed curve can be a circle, an ellipse or an irregular polygon, etc., which is not particularly limited here. The first electrode layer 61 comprises a plurality of first electrodes, and the plurality of openings 641 one-to-one correspond to the first electrodes, and the range of any opening 641 is within the boundary of the corresponding first electrode. Each opening 641 defines a light emitting device 6. In addition, as shown in Figure 5 and Figure 6 The orthographic projection of the pixel definition layer 64 on the substrate 1 is at least partially located in the peripheral area 11, and there is a gap between the pixel definition layer 64 located in the peripheral area 11 and the pixel definition layer 64 located in the display area 10, and the pixel definition layer 64 located in the peripheral area 11 can at least partially cover the barrier formed by the passivation layer 41 and the planarization layer 42, together with the passivation layer 41 and the planarization layer 42 to block the invasion of external moisture.

[0096] The light emitting functional layer 62 of each light emitting device 6 can be independent of each other and one-to-one correspond to each opening 641. Of course, the light emitting functional layer 62 of each light emitting device 6 can also share at least part of the film layer of the light emitting functional layer 62, such as the electron transport layer, thereby reducing the process difficulty.

[0097] The second electrode layer 63 can cover the light emitting functional layer 62, which can serve as the cathode of the light emitting device 6. Further, the same second electrode can be shared by each light emitting device 6, specifically, the second electrode layer 63 is a continuous conductive layer covering the light emitting functional layer 62 and the pixel definition layer 64 of each light emitting device 6, that is, the orthographic projection of the second electrode layer 63 on the pixel definition layer 64 covers each opening 641. A plurality of pixel circuits can one-to-one correspond to drive each light emitting device 6 to emit light.

[0098] As shown in Figure 5 and Figure 6 The second conductive layer 01 is disposed on the side of the transistor device layer 3 away from the substrate 1, and the orthographic projection of the second conductive layer 01 on the substrate 1 is located in the peripheral area 11; wherein the second conductive layer 01 is connected with the signal line 02, and the second conductive layer 01 is connected with the first conductive layer 2.

[0099] As shown in Figure 5 , Figure 6 and Figure 7As shown, in some embodiments of the present disclosure, the display panel further comprises an encapsulation layer covering the side of the second electrode layer 63 away from the substrate 1, which can be used to protect the light-emitting device 6 and prevent water and oxygen in the external environment from eroding the light-emitting device 6. Specifically, the encapsulation can be implemented in the manner of thin-film encapsulation (TFE), and specifically, the encapsulation layer can comprise a first inorganic layer 71, an organic layer 72, and a second inorganic layer 73, wherein the first inorganic layer 71 covers the surface of the second electrode layer 63 away from the substrate 1, the organic layer 72 can be arranged on the surface of the first inorganic layer 71 away from the substrate 1, and the boundary of the organic layer 72 is limited to the inside of the boundary of the first inorganic layer 71, and the second inorganic layer 73 covers the organic layer 72 and the first inorganic layer 71 not covered by the organic layer 72. Water and oxygen can be blocked by the second inorganic layer 73, and the organic layer 72 having flexibility can achieve planarization.

[0100] In some embodiments, the display panel further comprises a second dielectric layer 95 and a touch electrode layer 8, which can be arranged on the side of the encapsulation layer away from the substrate 1, and is used to sense the touch operation of the user so as to interact with the image displayed by the display panel. Taking mutual-capacitive touch as an example, the touch electrode layer 8 can comprise a first touch electrode and a second touch electrode, which can be distributed in space along the first direction and the second direction perpendicular to each other, so as to determine the touch position by sensing the change of the capacitance between the first touch electrode and the second touch electrode. The second dielectric layer 95 is arranged between the encapsulation layer and the touch electrode layer 8.

[0101] The display panel further comprises a first adhesive layer 91, a polarizer 92, an optical adhesive layer 93, and a cover plate 94, wherein the first adhesive layer 91 is arranged on the side of the touch electrode layer 8 away from the substrate 1, and the polarizer 92, the optical adhesive layer 93, and the cover plate 94 are sequentially arranged in the direction away from the substrate 1. The cover plate 94 is a transparent cover plate 94, which can be made of glass or other transparent materials.

[0102] In the present disclosure, the second conductive layer 01 can have various distribution modes, which will be specifically described below in combination with the drawings.

[0103] As Figure 5 and Figure 6As shown in the embodiment of the present disclosure, the second conductive layer 01 is arranged in the same layer as the first electrode layer 61, and the orthogonal projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthogonal projection of the first electrode layer 61 on the substrate 1. That is, the second conductive layer 01 and the first electrode layer 61 are made of the same material and by the same process, and the second conductive layer 01 is not connected to the first electrode layer 61. In this embodiment, the second conductive layer 01 can be made of indium tin oxide (ITO) like the first electrode layer 61. The material has corrosion resistance, so that even if the second conductive layer 01 is exposed at the cutting edge of the display panel, it will not be corroded, thereby helping to improve the shielding performance of the second conductive layer 01.

[0104] Further, in this embodiment, when the signal line 02 is arranged in the same layer as the source-drain metal layer 37, the second conductive layer 01 can be connected to the signal line 02 through the third conductive layer 5. For example, the third conductive layer 5 includes a transition part in the peripheral area 11, and the second conductive layer 01 can be connected to the transition part through a via. The transition part is connected to the signal line 02 through a via, thereby completing the connection between the second conductive layer 01 and the signal line 02.

[0105] As shown in the embodiment of the present disclosure, the second conductive layer 01 is arranged in the same layer as the first electrode layer 61, and the orthogonal projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthogonal projection of the first electrode layer 61 on the substrate 1. That is, the second conductive layer 01 and the first electrode layer 61 are made of the same material and by the same process, and the second conductive layer 01 is not connected to the first electrode layer 61. In this embodiment, the second conductive layer 01 can be made of indium tin oxide (ITO) like the first electrode layer 61. The material has corrosion resistance, so that even if the second conductive layer 01 is exposed at the cutting edge of the display panel, it will not be corroded, thereby helping to improve the shielding performance of the second conductive layer 01. Figure 3 Figure 4 As shown in the embodiment of the present disclosure, the second conductive layer 01 is arranged in the same layer as the first electrode layer 61, and the orthogonal projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthogonal projection of the first electrode layer 61 on the substrate 1. That is, the second conductive layer 01 and the first electrode layer 61 are made of the same material and by the same process, and the second conductive layer 01 is not connected to the first electrode layer 61. In this embodiment, the second conductive layer 01 can be made of indium tin oxide (ITO) like the first electrode layer 61. The material has corrosion resistance, so that even if the second conductive layer 01 is exposed at the cutting edge of the display panel, it will not be corroded, thereby helping to improve the shielding performance of the second conductive layer 01.

[0106] As shown in the embodiment of the present disclosure, the second conductive layer 01 is arranged in the same layer as the first electrode layer 61, and the orthogonal projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthogonal projection of the first electrode layer 61 on the substrate 1. That is, the second conductive layer 01 and the first electrode layer 61 are made of the same material and by the same process, and the second conductive layer 01 is not connected to the first electrode layer 61. In this embodiment, the second conductive layer 01 can be made of indium tin oxide (ITO) like the first electrode layer 61. The material has corrosion resistance, so that even if the second conductive layer 01 is exposed at the cutting edge of the display panel, it will not be corroded, thereby helping to improve the shielding performance of the second conductive layer 01. Figure 10 Figure 11 As shown in the embodiment of the present disclosure, the second conductive layer 01 is arranged in the same layer as the first electrode layer 61, and the orthogonal projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthogonal projection of the first electrode layer 61 on the substrate 1. That is, the second conductive layer 01 and the first electrode layer 61 are made of the same material and by the same process, and the second conductive layer 01 is not connected to the first electrode layer 61. In this embodiment, the second conductive layer 01 can be made of indium tin oxide (ITO) like the first electrode layer 61. The material has corrosion resistance, so that even if the second conductive layer 01 is exposed at the cutting edge of the display panel, it will not be corroded, thereby helping to improve the shielding performance of the second conductive layer 01.

[0107] ​​Furthermore, in this embodiment, when the signal line 02 is disposed on the same layer as the source / drain metal layer 37, the second conductive layer 01 can be connected to the signal line 02 through a via. Similar to the above embodiment, the connection area between the second conductive layer 01 and the signal line 02 in this embodiment can be set according to the distribution position of the signal line 02. For example, if the orthographic projection of the signal line 02 on the substrate 1 is located in the fourth sub-region 114, then correspondingly, the region where the orthographic projection of the second conductive layer 01 on the substrate 1 is located in the fourth sub-region 114 is connected to the signal line 02. Further, the region where the orthographic projection of the second conductive layer 01 on the substrate 1 is located in the first sub-region 111 and the second sub-region 112 is connected to the first conductive layer 2.

[0108] Of course, in addition to the above embodiments, the second conductive layer 02 can also be disposed on the same layer as other electrode layers, and this disclosure does not impose any special limitations. For example, the second conductive layer 01 is disposed on the same layer as the touch electrode layer 8, and the orthographic projection of the second conductive layer 01 on the substrate 1 does not overlap with the orthographic projection of the touch electrode layer 8 on the substrate 1. That is, the second conductive layer 01 and the touch electrode layer 8 are manufactured using the same material and the same process. The touch electrode layer 8 and the second conductive layer 01 can be single-layer films or multi-layer films, for example, the touch electrode layer 8 can be a titanium (Ti) / aluminum (Al) / titanium (Ti) multi-layer film. In this embodiment, when the signal line 02 is disposed on the same layer as the source / drain metal layer 37, the second conductive layer 01 can be connected to the signal line 02 through the third conductive layer 5. For example, the third conductive layer 5 includes a transition portion located in the peripheral area 11. The second conductive layer 01 can be connected to the transition portion through a via, and the transition portion can be connected to the signal line 02 through the via, thereby completing the connection between the second conductive layer 01 and the signal line 02.

[0109] In the above embodiments, the second conductive layer 01 is disposed in the same layer as the first electrode layer 61, the third conductive layer 5 or the touch electrode layer 8. In these embodiments, no additional outward process steps are required to form the second conductive layer 01, which is convenient to manufacture and does not require additional production costs.

[0110] In addition, this disclosure also enhances the electrostatic shielding effect of the display panel through other means. For example... Figures 4 to 7 As shown, in some embodiments, the display panel further includes a shielding metal layer 60 disposed on the side of the transistor device layer 3 away from the substrate 1. The orthogonal projection of the shielding metal layer 60 on the substrate 1 at least covers the orthogonal projection of the transistor devices located in the display area 10 on the substrate 1. The shielding metal layer 60 can be a single metal layer that can completely shield the charge above the transistor devices located in the display area 10. Figure 8 , Figure 9 As shown, Figure 9In the present disclosure, the left drawing is a shielding schematic diagram in the prior art, and the right drawing is a shielding schematic diagram in the present disclosure. Compared with the prior art, the shielding metal layer 60, the second conductive layer 01, the signal line 02 and the second conductive layer 01 in the present disclosure can shield the transistor device in the display panel from multiple directions and multiple angles, avoiding the influence of the static test on the transistor device.

[0111] As shown in FIG. 1, further, the orthogonal projection of the shielding metal layer 60 on the substrate 1 is at least partially located in the peripheral area 11, and the edges between the shielding metal layer 60, the signal line 02 and the second conductive layer 01 overlap with each other, that is, the shielding metal layer 60, the signal line 02 and the second conductive layer 01 form a complete shielding surface in the plane parallel to the substrate 1, which can completely shield the charges from the copper bar rubbing and the electrostatic field test, preventing the lightening caused by the feature deviation of the transistor device due to the downward movement of the charges. Figure 9 The overlapping mode of the shielding metal layer 60, the signal line 02 and the second conductive layer 01 forming a complete shielding surface in the plane parallel to the substrate 1 can be various, which can be set according to the distribution positions of the signal line 02 and the second conductive layer 01. For example, the second conductive layer 01 is located on the side of the signal line 02 away from the display area 10, the orthogonal projection of the shielding metal layer 60 on the substrate 1 at least partially overlaps with the orthogonal projection of the second conductive layer 01 on the substrate 1; or the orthogonal projection of the shielding metal layer 60 on the substrate 1 at least partially overlaps with the orthogonal projection of the signal line 02 on the substrate 1, and the orthogonal projection of the second conductive layer 01 on the substrate 1 at least partially overlaps with the orthogonal projection of the signal line 02 on the substrate 1. For another example, the signal line 02 is located on the side of the second conductive layer 01 away from the display area 10, the orthogonal projection of the shielding metal layer 60 on the substrate 1 at least partially overlaps with the orthogonal projection of the signal line 02 on the substrate 1; or the orthogonal projection of the shielding metal layer 60 on the substrate 1 at least partially overlaps with the orthogonal projection of the second conductive layer 01 on the substrate 1, and the orthogonal projection of the second conductive layer 01 on the substrate 1 at least partially overlaps with the orthogonal projection of the signal line 02 on the substrate 1.

[0112] In the present disclosure, the second electrode layer 63 can be reused as the shielding metal layer 60, which can achieve the shielding effect without increasing additional process steps.

[0113] The present disclosure further provides a manufacturing method of a display panel, comprising:

[0114] Step S100, providing a substrate 1, the substrate 1 comprising a display area 10 and a peripheral area 11 located at the periphery of the display area 10;

[0115]

[0116] ​Step S200, forming a first conductive layer 2 on one side of the substrate 1, the orthographic projection of the first conductive layer 2 on the substrate 1 at least partially locates in the peripheral area 11;

[0117] Step S300, forming a transistor device layer 3 on the side of the first conductive layer 2 away from the substrate 1, the transistor device layer 3 includes transistor devices in the display area 10 and signal lines 02 in the peripheral area 11;

[0118] Step S400, forming a second conductive layer 01 on the side of the transistor device layer 3 away from the substrate 1, the orthographic projection of the second conductive layer 01 on the substrate 1 locates in the peripheral area 11;

[0119] Wherein, the second conductive layer 01 is connected with the signal lines 02, and the second conductive layer 01 is connected with the first conductive layer 2.

[0120] The display device of the present disclosure can be a mobile phone, a tablet computer, a television, etc. electronic device, which will not be listed one by one here.

[0121] It should be noted that although the steps of the method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. In addition or alternatively, some steps can be omitted, a plurality of steps can be combined into one step, and / or one step can be divided into a plurality of steps, etc., which should be considered as part of the present disclosure.

[0122] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components presented in the specification. The present disclosure can have other embodiments and can be implemented and executed in various ways. The foregoing variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in the specification extends to all alternative combinations of two or more individual features mentioned or obvious from the text and / or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of the specification illustrate the best way known for implementing the present disclosure and will enable a person skilled in the art to utilize the present disclosure.

Claims

1. A display panel, characterized in that, include: The substrate includes a display area and a peripheral area located around the display area; A first conductive layer is disposed on one side of the substrate, and the orthographic projection of the first conductive layer on the substrate is at least partially located in the peripheral region. A transistor device layer is disposed on the side of the first conductive layer away from the substrate, and the transistor device layer includes transistor devices located in the display area and signal lines located in the peripheral area; A second conductive layer is disposed on the side of the transistor device layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate is located in the peripheral region; wherein, the second conductive layer is connected to the signal line and the second conductive layer is connected to the first conductive layer; A shielding metal layer is disposed on the side of the transistor device layer away from the substrate, and the orthogonal projection of the shielding metal layer on the substrate at least covers the orthogonal projection of the transistor device located in the display area on the substrate; the orthogonal projection of the shielding metal layer on the substrate is at least partially located in the peripheral area; The orthographic projection of the shielding metal layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate; Or the orthographic projection of the shielding metal layer on the substrate overlaps at least partially with the orthographic projection of the signal line on the substrate.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the second conductive layer on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate.

3. The display panel according to claim 1, characterized in that, The orthographic projection of the second conductive layer onto the substrate is a closed ring structure surrounding the display area.

4. The display panel according to claim 1, characterized in that, The display panel also includes: A first electrode layer is disposed on the side of the transistor device layer away from the substrate, and the orthographic projection of the first electrode layer on the substrate is located in the display area; A light-emitting functional layer is disposed on the side of the first electrode layer away from the substrate. The second electrode layer is disposed on the side of the light-emitting functional layer away from the substrate. The second conductive layer is disposed in the same layer as the first electrode layer, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the first electrode layer on the substrate.

5. The display panel according to claim 1, characterized in that, The display panel also includes: A third conductive layer is disposed on the side of the transistor device layer away from the substrate, and the orthogonal projection of the third conductive layer on the substrate is at least partially located in the display area; A planarization layer is disposed on the side of the third conductive layer away from the substrate. A first electrode layer is disposed on the side of the planarization layer away from the substrate, and the orthographic projection of the first electrode layer on the substrate is located in the display area; A light-emitting functional layer is disposed on the side of the first electrode layer away from the substrate. The second electrode layer is disposed on the side of the light-emitting functional layer away from the substrate. The second conductive layer and the third conductive layer are disposed in the same layer, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the third conductive layer on the substrate.

6. The display panel according to claim 4 or 5, characterized in that, The second electrode layer is reused as the shielding metal layer.

7. The display panel according to claim 1, characterized in that, The display panel also includes: An encapsulation layer is disposed on the side of the transistor device layer away from the substrate. A touch electrode layer is disposed on the side of the encapsulation layer away from the substrate, and the touch electrode layer includes a plurality of touch electrodes located in the display area; The second conductive layer is disposed in the same layer as the touch electrode layer, and the orthographic projection of the second conductive layer on the substrate does not overlap with the orthographic projection of the touch electrode layer on the substrate.

8. The display panel according to claim 1, characterized in that, The display area includes a first side and a second side disposed opposite to each other along a first direction, and a third side and a fourth side disposed opposite to each other along a second direction; The peripheral area includes a first sub-area connected to the first side, a second sub-area connected to the second side, a third sub-area connected to the third side, and a fourth sub-area connected to the fourth side; The orthographic projection of the first conductive layer onto the substrate is at least partially located in the first sub-region and the second sub-region; The orthogonal projection of the signal line onto the substrate is at least partially located in the third sub-region or the fourth sub-region.

9. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, the substrate including a display area and a peripheral area located around the display area; A first conductive layer is formed on one side of the substrate, and the orthographic projection of the first conductive layer on the substrate is at least partially located in the peripheral region; A transistor device layer is formed on the side of the first conductive layer away from the substrate, the transistor device layer including transistor devices located in the display area and signal lines located in the peripheral area; A second conductive layer is formed on the side of the transistor device layer away from the substrate, and the orthographic projection of the second conductive layer on the substrate is located in the peripheral region; wherein the second conductive layer is connected to the signal line and the second conductive layer is connected to the first conductive layer; A shielding metal layer is formed on the side of the transistor device layer away from the substrate, and the orthogonal projection of the shielding metal layer on the substrate at least covers the orthogonal projection of the transistor device located in the display area on the substrate; the orthogonal projection of the shielding metal layer on the substrate is at least partially located in the peripheral area; The orthographic projection of the shielding metal layer on the substrate at least partially overlaps with the orthographic projection of the second conductive layer on the substrate; Or the orthographic projection of the shielding metal layer on the substrate overlaps at least partially with the orthographic projection of the signal line on the substrate.

10. A display device comprising a display panel as described in any one of claims 1-8.

Images