A chip and method for improving noise isolation capability using vacuum isolation strips

Abstract

A chip that utilizes a vacuum isolation band to improve noise isolation capability is characterized in that: the chip includes a noise region (1), a low-noise region (2), a noise isolation band (3), a vacuum isolation band (4), and a high-voltage trap (5); wherein, the noise region (1) and the low-noise region (2) are respectively used to accommodate the noise circuit (101) and the low-noise circuit (201~206) within the chip, and are physically isolated by the noise isolation band (3), the vacuum isolation band (4), and the high-voltage trap (5). The method in this invention can further improve the chip's isolation capability against interference signals while reducing the chip area.

Description

Technical Field

[0001] This invention relates to the field of chip manufacturing, and more specifically, to a chip and method for improving noise isolation capability using a vacuum isolation strip. Background Technology

[0002] Currently, with the continuous development of integrated circuit technology and chip manufacturing processes, the size of packaged chips is getting smaller and smaller. This makes it very easy for the chip's performance to be affected by mutual interference between a noisy module that generates a lot of noise when it is in operation and a low-noise module that needs to be controlled with a small current when it is in operation.

[0003] In existing technologies, isolation rings connected to the highest or lowest potential are often used for noise isolation and to prevent latch-up in chips with CMOS transistors. However, the method of using isolation rings to isolate the noisy and low-noise parts of a circuit has a relatively simple implementation, limited isolation effect, and a large distance between the noise and low-noise circuits at both ends of the isolation ring, which makes it difficult to further reduce the chip size.

[0004] To address the aforementioned issues, there is an urgent need for a chip and method that utilizes vacuum isolation strips to enhance noise isolation capabilities. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a chip and method for improving noise isolation capabilities using a vacuum isolation strip. By simultaneously setting a vacuum isolation strip next to the noise isolation strip, the movement of charge carriers in the isolation region is reduced, thereby reducing signal crosstalk between the noise circuit and the low-noise circuit.

[0006] The present invention adopts the following technical solution.

[0007] The first aspect of the present invention relates to a chip that utilizes a vacuum isolation band to improve noise isolation capability, characterized in that: the chip includes a noise region 1, a low-noise region 2, a noise isolation band 3, a vacuum isolation band 4, and a high-voltage trap 5; wherein, the noise region 1 and the low-noise region 2 are respectively used to accommodate the noise circuit 101 and the low-noise circuits 201~206 within the chip, and the noise region and the low-noise region are physically isolated from each other by the noise isolation band 3, the vacuum isolation band 4, and the high-voltage trap 5.

[0008] Preferably, the noise circuit includes a high-power device for performing switching operations; the low-noise circuit includes a control circuit for controlling the high-power device to perform switching operations.

[0009] Preferably, the chip further includes a chip substrate, on which a substrate epitaxial layer 6 is disposed. The noise circuit, the low-noise circuit, the noise isolation band, and the high-voltage trap are all disposed in the chip substrate and the substrate epitaxial layer 6. Furthermore, the noise isolation band and the high-voltage trap form a PN junction to achieve noise isolation between the noise region and the low-noise region.

[0010] Preferably, the noise isolation band is an N+ type doped isolation band, and the high voltage trap is a P+ type doped substrate.

[0011] Preferably, in the PN junction formed by the noise isolation zone and the high-voltage trap, the N-terminal is adjacent to the noise circuit, and the P-terminal is adjacent to the low-noise circuit.

[0012] Preferably, the vacuum isolation band is located in the epitaxial layer 6 of the substrate; the vacuum isolation band is disposed adjacent to the noise isolation band, or the vacuum isolation band and the noise isolation band are separated by a high-voltage trap; and the vacuum isolation band is separated from the low-noise circuit by a high-voltage trap.

[0013] Preferably, the high-pressure trap between the noise zone and the low-noise zone is disposed adjacent to the low-noise zone and located on one side of the vacuum isolation zone; or, the high-pressure trap between the noise zone and the low-noise zone is divided into two parts by the vacuum isolation zone.

[0014] Preferably, both the vacuum isolation band and the substrate epitaxial layer are P-type doped, and the doping concentrations of the vacuum isolation band and the substrate epitaxial layer are the same and both are less than the doping concentration of the high-voltage trap.

[0015] Preferably, the total width of the vacuum isolation strip, the noise isolation strip, and the high-voltage trap portion that forms a PN junction with the noise isolation strip is greater than or equal to 50 μm.

[0016] A second aspect of this invention relates to a method for improving noise isolation capability using a vacuum isolation strip, wherein: a chip for improving noise isolation capability using a vacuum isolation strip as described in the first aspect of this invention is employed. The beneficial effect of this invention is that, compared with the prior art, the chip and method for improving noise isolation capability using a vacuum isolation strip in this invention can simultaneously provide a noise isolation strip and a vacuum isolation strip in the isolation region between a noisy circuit and a low-noise circuit. This reduces the number of mobile charge carriers in the chip substrate and reduces charge accumulation on both sides of the isolation region, thereby reducing interference from the noisy circuit to signals carried in the low-noise circuit. The method in this invention can improve the chip's isolation capability against interference signals while reducing the chip area. Attached Figure Description

[0017] Figure 1 This is a top view of the internal structure of a chip according to an embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability.

[0018] Figure 2This is a top view of the internal structure of a chip according to another embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability;

[0019] Figure 3 This is a cross-sectional view of the internal structure of a chip according to an embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability.

[0020] Figure 4 This is a cross-sectional view of the internal structure of a chip according to another embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability.

[0021] Figure label:

[0022] 1-Noise Zone

[0023] 101-Noise Circuit

[0024] 2-Low noise zone

[0025] 201~206 - Low-noise circuits

[0026] 3-Noise isolation zone,

[0027] 4-Vacuum isolation zone,

[0028] 5-High-pressure trap,

[0029] 6-Substrate epitaxial layer. Detailed Implementation

[0030] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0031] In existing technologies, isolation rings are typically embedded in the chip substrate to reduce noise interference and latch-up phenomena in CMOS integrated circuits. However, in the chip manufacturing processes used in existing technologies, the isolation effect of the isolation rings on high-power circuits is limited, and the spacing between high-power circuits and low-noise circuits also makes it difficult to reduce the chip size.

[0032] To achieve better isolation and smaller chip size, this invention proposes a novel chip isolation scheme.

[0033] Figure 1 This is a top view of the internal structure of a chip according to an embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability. Figure 2 This is a top view of the internal structure of a chip according to another embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability. (See attached image.) Figure 1-2As shown, a chip that utilizes a vacuum isolation band to improve noise isolation capability includes a noise region 1, a low-noise region 2, a noise isolation band 3, a vacuum isolation band 4, and a high-voltage trap 5. The noise region 1 and the low-noise region 2 are used to accommodate the noise circuit 101 and the low-noise circuits 201-206 within the chip, respectively, and the noise region and the low-noise region are physically isolated from each other by the noise isolation band 3, the vacuum isolation band 4, and the high-voltage trap 5.

[0034] Specifically, noise region 1 in a chip refers to the area where components and circuits carrying large voltages and currents are located. The voltage and current in these components may frequently undergo drastic changes in direction or value range depending on the circuit's operating state, which may cause significant interference to surrounding sensitive signals.

[0035] Additionally, the low-noise region 2 in the chip refers to the area where components and circuits carrying smaller voltages, currents, or more precise control signals are located. Since signal errors can severely impact the chip's output performance, this part of the circuitry should be isolated from noisy circuitry.

[0036] In one embodiment of the present invention, for a certain boost-buck converter chip, the internal switching transistor generates significant noise during operation due to its high power consumption in the on-state and frequent switching between on and off states. Therefore, this switching transistor can be classified into noise region 1. On the other hand, the control circuit that controls the switching transistor's on / off state transmits signals with relatively small amplitudes, and these signals directly affect the chip's operating state. To minimize or eliminate interference with this part of the circuit, it can be classified into low-noise region 2.

[0037] Preferably, the noise circuit 101 includes a high-power device for performing switching operations; the low-noise circuits 201-206 include a control circuit for controlling the high-power device to perform switching operations.

[0038] Understandably, high-power devices refer to those devices whose voltage exceeds a certain percentage of the chip voltage or whose current exceeds a certain percentage of the chip's total input or output current when the device is in normal operating condition. For example, in boost / buck converter chips, high-power devices include switching transistors. In other types of chips, CMOS transistors and other similar devices are also generally considered high-power devices.

[0039] Preferably, the chip further includes a chip substrate, on which a substrate epitaxial layer 6 is disposed. The noise circuit, the low-noise circuit, the noise isolation band and the high-voltage trap are all disposed in the chip substrate and the trap in the substrate epitaxial layer 6. Furthermore, the noise isolation band and the high-voltage trap form a PN junction to achieve noise isolation between the noise region 1 and the low-noise region 2.

[0040] Similar to the configuration of most chips in the prior art, both the noise circuit and the low-noise circuit are disposed on the chip substrate and its epitaxial layer. However, to ensure good isolation, the noise circuit can be disposed at one corner or one end of the chip, while the low-noise circuit is disposed at the other end. Furthermore, an isolation band is provided between the noise circuit and the low-noise circuit.

[0041] Generally speaking, chip substrates are divided into two types: P-type doping and N-type doping. In this invention, the chip substrate and noise isolation band can be set to have different doping types, while the high voltage trap and the chip substrate can be set to have the same doping type, but with a certain difference in doping concentration.

[0042] Preferably, the noise isolation band 3 is an N+ type doped isolation band, and the high voltage trap 5 is a P+ type doped substrate.

[0043] When there are different circuit structures or component structures in the chip, in order to more conveniently integrate different functions and different components, the doping type of the substrate can be selected according to the chip situation, and the doping concentration and type of the noise isolation band 3 and the high voltage trap 5 can be selected accordingly.

[0044] Preferably, in the PN junction formed by the noise isolation band 3 and the high-voltage trap, the N-terminal is adjacent to the noise circuit, and the P-terminal is adjacent to the low-noise circuit.

[0045] Similarly, in one embodiment of the present invention, since the high-power devices included in the noise circuit are more suitable to be disposed on a P-type or P+ type substrate, an N-terminal, i.e., the part where the noise isolation band is located, can be disposed adjacent to the noise circuit, so that the noise of the noise circuit part is effectively blocked by the PN junction, thereby reducing the influence of the noise circuit.

[0046] Preferably, the vacuum isolation band 4 is located in the epitaxial layer 6 of the substrate; the vacuum isolation band 4 is disposed adjacent to the noise isolation band 3, or the vacuum isolation band 4 and the noise isolation band 3 are separated by a high-voltage trap 5; and the vacuum isolation band 4 is separated from the low-noise circuit by the high-voltage trap 5. Preferably, the high-voltage trap 5 between the noise region 1 and the low-noise region 2 is disposed in the critical low-noise region and is located on one side of the vacuum isolation band; or, the high-voltage trap 5 between the noise region 1 and the low-noise region 2 is divided into two parts by the vacuum isolation band.

[0047] Figure 3 This is a cross-sectional view of the internal structure of a chip according to an embodiment of the present invention that utilizes a vacuum isolation strip to improve noise isolation capability. Figure 4 This is a cross-sectional view of the internal structure of a chip according to another embodiment of the present invention, which utilizes a vacuum isolation strip to improve noise isolation capability. (See attached image.) Figure 3-4As shown, a substrate epitaxial layer 6 can be grown on the epitaxial portion of the chip substrate. Noise circuits and low-noise circuits can be set on this epitaxial layer according to the requirements described above. A certain distance is reserved between the noise circuits and the low-noise circuits to achieve isolation. Specifically, to realize the high-voltage well 5, after the epitaxial layer is grown, a cover mask is used to photolithographically etch the high-voltage well 5 portion, and then P+ type doping is implanted into this portion. To realize the vacuum isolation band, N+ type doping can be implanted using the same method. In the prior art, to minimize the chip area, the P-type and N-type doping of different concentrations between the various components in the circuit and the isolation band are usually tightly connected. However, in this invention, to achieve better isolation, there is a certain distance between the high-voltage well 5 and the vacuum isolation band 4. No other doping is added at this distance after the substrate epitaxial layer is formed; this distance or width is referred to as the vacuum isolation band in this invention. The vacuum isolation band can have the same composition as the substrate epitaxial layer and be formed using the same method.

[0048] Preferably, the high-pressure trap between the noise zone and the low-noise zone is arranged adjacent to the low-noise zone and located on one side of the vacuum isolation zone; alternatively, the high-pressure trap between the noise zone and the low-noise zone is divided into two parts by the vacuum isolation zone. It is understood that the schematic diagrams of the two different arrangements are as follows: Figure 3 and Figure 4 .

[0049] Preferably, both the vacuum isolation band 4 and the substrate epitaxial layer 6 are P-type doped, and the doping concentrations of the vacuum isolation band 4 and the substrate epitaxial layer 6 are the same and both are less than the doping concentration of the high-voltage trap 5.

[0050] In this embodiment of the invention, the doping concentration of the substrate epitaxial layer should be much smaller than the doping degree of the chip substrate 5, for example, by more than an order of magnitude difference in doping concentration.

[0051] Specifically, although the PN junction formed between the noise isolation band 3 and the chip substrate 5 can isolate some of the noise, when the noise in the noise circuit section is too high, or when the spacing between the noise circuit and the low-noise circuit is too small, some noise will still pass through the PN junction and affect the low-noise circuit.

[0052] At this point, if a trench-like vacuum isolation band 4 is implemented between the two circuit sections and beside the noise isolation band, the number of carriers moving within the chip substrate can be further reduced.

[0053] Preferably, both the vacuum isolation band 4 and the epitaxial layer of the substrate are P-type doped, and the doping concentrations of the vacuum isolation band 4 and the epitaxial layer of the substrate 6 are the same and lower than the doping concentration of the high-voltage well. Because the doping concentration of the vacuum isolation band 4 is low, there are fewer mobile charge carriers, resulting in a higher impedance across the PN junction, thereby reducing signal crosstalk.

[0054] Preferably, the total width of the vacuum isolation strip, the noise isolation strip, and the high-voltage trap 5 that forms a PN junction with the noise isolation strip is greater than or equal to 50 μm.

[0055] Generally, depending on the chip manufacturing process, the spacing between noisy and low-noise circuits can be set to be greater than or equal to 50μm. Within this 50μm, a noise isolation band can occupy a width of 10 to 20μm, while the majority of the remaining 30μm can be used for implanting dopants with the same composition as the chip substrate but at a much higher concentration. The remaining portion of this 30μm can be retained, thus creating a vacuum isolation band. Its width can be adjusted according to the chip manufacturing process specifications or based on actual conditions. Generally, the wider the vacuum isolation band, the higher its impedance and the better the isolation effect for the noise circuit, but it also places higher demands on the chip manufacturing process.

[0056] For example, when fabricating a vacuum isolation band, the area of ​​the mask on the high-voltage well can be adjusted. For instance, reducing the chip opening area when doping is implanted into the high-voltage well reduces the overall volume of doping in the chip, thereby enabling the formation of a vacuum isolation band between the high-voltage well and the noise isolation band.

[0057] The beneficial effects of this invention are that, compared with the prior art, the chip and method of this invention, which utilizes a vacuum isolation strip to improve noise isolation capability, can simultaneously set a noise isolation strip and a vacuum isolation strip in the isolation region between the noisy circuit and the low-noise circuit. This reduces the number of mobile charge carriers in the chip substrate and reduces charge accumulation on both sides of the isolation region, thereby reducing interference from the noisy circuit to signals carried in the low-noise circuit. The method of this invention can improve the chip's isolation capability against interference signals while reducing the chip area.

[0058] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A chip that utilizes a vacuum isolation strip to improve noise isolation capability, characterized in that: The chip includes a noise region, a low-noise region, a noise isolation band, a vacuum isolation band, and a high-voltage trap; wherein... The noise region and the low-noise region are respectively used to accommodate the noise circuit and the low-noise circuit in the chip, and the noise region and the low-noise region are physically isolated by a noise isolation strip, a vacuum isolation strip and a high-voltage trap. The chip also includes a chip substrate, on which a substrate epitaxial layer is disposed. The noise circuit, the low-noise circuit, the noise isolation band, and the high-voltage trap are all disposed in the substrate epitaxial layer. Furthermore, the noise isolation band and the high-voltage trap form a PN junction to achieve noise isolation between the noise region and the low-noise region. The vacuum isolation band is located in the epitaxial layer of the substrate; the high-voltage trap between the noise region and the low-noise region is divided into two parts by the vacuum isolation band, and the vacuum isolation band and the noise isolation band are separated by the high-voltage trap; and the vacuum isolation band and the low-noise circuit are separated by the high-voltage trap. The substrate epitaxial layer and noise isolation band of the chip are respectively set to have different doping types. The high voltage trap and the substrate epitaxial layer of the chip are set to have the same doping type. The vacuum isolation band and the substrate epitaxial layer have the same composition and doping concentration, and the doping concentration of the vacuum isolation band and the substrate epitaxial layer is lower than that of the high voltage trap.

2. The chip according to claim 1, characterized in that: The noise circuit includes high-power devices for performing switching operations; The low-noise circuit includes a control circuit for controlling the high-power device to perform switching operations.

3. A chip according to claim 1 that utilizes a vacuum isolation strip to improve noise isolation capability, characterized in that: The noise isolation band is an N+ type doped isolation band, and the high voltage well is a P+ type doped well.

4. A chip with improved noise isolation capability using a vacuum isolation strip as described in claim 3, characterized in that: In the PN junction formed by the noise isolation strip and the high-voltage trap, the N-terminal is adjacent to the noise circuit, and the P-terminal is adjacent to the low-noise circuit.

5. A chip according to claim 1 that utilizes a vacuum isolation strip to improve noise isolation capability, characterized in that: Both the vacuum isolation band and the epitaxial layer of the substrate are P-type doped.

6. A chip according to claim 1 that utilizes a vacuum isolation strip to improve noise isolation capability, characterized in that: The total width of the vacuum isolation strip, the noise isolation strip, and the high-voltage trap portion that forms a PN junction with the noise isolation strip is greater than or equal to 50 μm.

7. A method for improving noise isolation capability using vacuum isolation strips, characterized in that: The chip described in any one of claims 1-6 uses a vacuum isolation strip to improve noise isolation capability.

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