Dual-trench silicon carbide transistor and method of manufacturing the same
By setting a first PN junction structure within the source trench structure of a silicon carbide transistor, the problem of temperature detection in existing technologies is solved, enabling accurate temperature detection and signal amplification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WEEN SEMICON TECH CO LTD
- Filing Date
- 2022-08-31
- Publication Date
- 2026-05-22
AI Technical Summary
Existing dual-groove silicon carbide transistors cannot detect their own temperature.
A first PN junction structure is set within the source trench structure of a silicon carbide transistor. By utilizing the linear relationship between the forward voltage and temperature under a certain current mode, temperature detection is achieved. Furthermore, the detection accuracy and signal amplification are improved through the uniformly distributed first PN junction structure.
Temperature detection of the silicon carbide transistor itself was achieved, improving the accuracy of detection and amplifying the temperature detection signal.
Smart Images
Figure CN115377192B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor devices, and in particular relates to a dual-trench silicon carbide transistor and a method for manufacturing the same. Background Technology
[0002] A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is a voltage-controlled device that can be widely used in various power electronic systems.
[0003] Compared to traditional vertical-structure metal-oxide-semiconductor (MOSFETs), MOSFETs with a double-trench structure, formed by trenching in both the source and gate regions, exhibit smaller cell size, lower power consumption, and higher channel density. Furthermore, the double-trench MOSFET structure avoids the parasitic JFET (Junction Field-Effect Transistor) effect, making it a highly attractive technology. However, existing double-trench silicon carbide (SiC) MOSFETs cannot detect their own temperature. Summary of the Invention
[0004] This application provides a dual-trench silicon carbide transistor and its manufacturing method, which enables temperature detection of the dual-trench silicon carbide transistor itself.
[0005] In a first aspect, embodiments of this application provide a dual-trench silicon carbide transistor, comprising:
[0006] A silicon carbide substrate of the first doping type, the silicon carbide substrate includes a first surface, and an epitaxial layer of the first doping type is disposed on the first surface;
[0007] A second-doped well region is set within the epitaxial layer;
[0008] A first cell region is provided within the epitaxial layer, the first cell region including at least one first cell and at least one second cell, the first cell and the second cell being arranged in parallel;
[0009] The first cell includes a first gate trench structure disposed between the well regions;
[0010] The second cell includes:
[0011] A second gate trench structure disposed between the well regions;
[0012] A first source trench structure is disposed within the well region and located in the outer region of the second gate trench structure, and spaced apart from the second gate trench structure. The first source trench structure includes a first PN junction structure disposed at the bottom of the first source trench structure.
[0013] The first doping type is the opposite of the second doping type.
[0014] In some alternative implementations, the first PN junction structure includes:
[0015] A first doped structure of the first doping type is disposed on the side near the second gate trench structure;
[0016] And a second doped structure of a second doping type disposed on the side away from the second gate trench structure.
[0017] In some alternative implementations, the first source trench structure further includes:
[0018] A first doped region of a first doped type is disposed on the side of the first PN junction structure away from the first surface, and the first doped region is insulated from the first PN junction structure.
[0019] In some alternative implementations, the second cell further includes:
[0020] A second doped region of a second doped type is disposed within the well region and on the side of the bottom of the first source trench structure near the first surface;
[0021] A third doped region of a first doped type is disposed within the well region and spaced apart from the first source trench structure.
[0022] In some alternative embodiments, the dual-trench silicon carbide transistor further includes a second cell region disposed near the first gate trench structure, the second cell region including a third cell, and the third cell including a second source trench structure disposed in the well region.
[0023] The second source trench structure includes:
[0024] The fourth doped region of the second doping type is set at the bottom of the second source trench structure;
[0025] And a fifth doping region of the first doping type disposed in the fourth doping region away from the first surface;
[0026] The fourth and fifth doped regions are insulated from each other.
[0027] In some alternative implementations, the third cell further includes:
[0028] A sixth doped region of the second doping type is disposed within the well region and on the side of the bottom of the second source trench structure near the first surface;
[0029] A seventh doped region of the first doping type is disposed within the well region and spaced apart from the second source trench structure.
[0030] In some alternative implementations, the dual-trench silicon carbide transistor further includes a third cell region disposed near the first source trench structure, the third cell region including a fourth cell and a fifth cell arranged in parallel.
[0031] The fourth cell includes:
[0032] A third gate trench structure is disposed on the side close to the first source trench structure;
[0033] A fourth source trench structure disposed within the well region and spaced apart from the third gate trench structure, the fourth source trench structure including a second PN junction structure disposed at the bottom of the fourth source trench structure;
[0034] The fifth cell includes:
[0035] A fourth gate trench structure is disposed on the side near the fourth source trench structure;
[0036] A fifth source trench structure is disposed within the well region and spaced apart from the fourth gate trench structure. The fifth source trench structure includes an eighth doped region of the first doping type disposed at the bottom of the fifth source trench structure.
[0037] In some alternative implementations, the second PN junction structure includes:
[0038] A third doped structure of the second doping type is disposed on the side near the third gate trench structure;
[0039] A fourth doped structure of the first doping type is disposed on the side near the fourth gate trench structure.
[0040] In some alternative implementations, the fourth source trench structure further includes:
[0041] A ninth doped region of the first doping type is disposed on the side of the second PN junction structure away from the first surface, and the ninth doped region is insulated from the second PN junction structure.
[0042] The fifth source trench structure also includes:
[0043] A tenth doped region of the first doping type is disposed on the side of the eighth doped region away from the first surface, and the tenth doped region is insulated from the eighth doped region.
[0044] In some alternative implementations, the fourth cell further includes:
[0045] An eleventh doped region of the second doping type is located within the well region and on the side of the bottom of the fourth source trench structure near the first surface.
[0046] A twelfth doped region of the first doping type, located within the well region and spaced from the fourth source trench structure;
[0047] The fifth cell also includes:
[0048] The thirteenth doped region of the second doping type is located within the well region and on the side of the bottom of the fifth source trench structure near the first surface.
[0049] The fourteenth doped region of the first doping type is located within the well region and is spaced apart from the fifth source trench structure.
[0050] Secondly, embodiments of this application provide a method for manufacturing a dual-trench silicon carbide transistor, including:
[0051] A silicon carbide substrate of a first doping type is provided, the silicon carbide substrate including a first surface, and an epitaxial layer of the first doping type is disposed on the first surface;
[0052] A second type of doped well region is formed within the epitaxial layer;
[0053] A first cell region is formed within the epitaxial layer. The first cell region includes at least one first cell and at least one second cell, with the first cell and the second cell arranged in parallel.
[0054] The first cell includes a first gate trench structure disposed between the well regions;
[0055] The second cell includes:
[0056] A second gate trench structure disposed between the well regions;
[0057] A first source trench structure is disposed within the well region and located in the outer region of the second gate trench structure, and spaced apart from the second gate trench structure. The first source trench structure includes a first PN junction structure disposed at the bottom of the first source trench structure.
[0058] This application provides a dual-trench silicon carbide transistor, which includes a first cell region disposed within an epitaxial layer. The first cell region includes at least one first cell and at least one second cell, arranged in parallel. The first cell includes a first gate trench structure disposed between well regions, and the second cell includes a second gate trench structure disposed between well regions. A first source trench structure is disposed within the well region, outside the second gate trench structure, and spaced from it. The first source trench structure includes a first PN junction structure disposed at its bottom. By setting the first PN junction structure within the first source trench structure, and utilizing the linear relationship between the forward voltage and temperature of the first PN junction structure under a certain current mode, the temperature of the dual-trench silicon carbide transistor itself can be detected. Furthermore, on the one hand, since the first PN junction structure is uniformly distributed within the silicon carbide metal oxide semiconductor field-effect transistor, the accuracy of temperature detection within the silicon carbide metal oxide semiconductor field-effect transistor can be improved; on the other hand, since the resistance formed between the first PN junction structures is sufficiently large within the silicon carbide metal oxide semiconductor field-effect transistor, the temperature detection signal can be amplified. Attached Figure Description
[0059] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0060] Figure 1 This is a schematic diagram of a structure of an embodiment of the dual-trench silicon carbide transistor provided in this application;
[0061] Figure 2 This is another structural schematic diagram of an embodiment of the dual-trench silicon carbide transistor provided in this application;
[0062] Figure 3 This is a schematic diagram of the chip layout of the temperature sensing diode in the dual-groove silicon carbide transistor provided in this application;
[0063] Figure 4 This is a schematic flowchart of an embodiment of the dual-trench silicon carbide transistor manufacturing method provided in this application;
[0064] Figure 5 This is a schematic diagram of the cross-sectional structure of the silicon carbide substrate provided in this application;
[0065] Figure 6 This is a schematic diagram of the cross-sectional structure of the trap region provided in this application;
[0066] Figure 7This is a schematic diagram of the cross-sectional structure for forming the third doped region provided in this application;
[0067] Figure 8 This is a schematic diagram of the cross-sectional structure forming the first trench, the second trench, the third trench and the fourth trench provided in this application;
[0068] Figure 9 This is a schematic diagram of the cross-sectional structure for forming the second doped region provided in this application;
[0069] Figure 10 This is a cross-sectional structural diagram of the formation of the first gate trench structure, the second gate trench structure, and the formation of interlayer dielectric on the surfaces of the second trench and the fourth trench, provided in this application.
[0070] Figure 11 This is a schematic diagram of the cross-sectional structure forming the first PN junction structure provided in this application;
[0071] Figure 12 This is a schematic diagram of a cross-sectional structure in which an interlayer dielectric is formed on a first PN junction structure, as provided in this application.
[0072] Figure 13 This is a schematic diagram of the cross-sectional structure for forming the first doped region provided in this application.
[0073] Explanation of component symbols in the attached diagram:
[0074] 1: Silicon carbide substrate; 11: First surface; 12: Second surface;
[0075] 2: Epitaxial layer;
[0076] 3: Trap area;
[0077] 41: First gate trench structure; 42: First trench;
[0078] 5: Second cell; 51: Second gate trench structure; 52: First source trench structure; 521: First PN junction structure; 5211: First doped structure; 5212: Second doped structure; 522: First doped region; 53: Second doped region; 54: Third doped region; 55: Second trench; 56: Third trench; 57: Fourth trench;
[0079] 6: Third cell; 61: Second source trench structure; 611: Fourth doped region; 612: Fifth doped region; 62: Sixth doped region; 63: Seventh doped region;
[0080] 7: Fourth cell; 71: Third gate trench structure; 72: Fourth source trench structure; 721: Second PN junction structure; 7211: Third doped structure; 7212: Fourth doped structure; 722: Ninth doped region; 73: Eleventh doped region; 74: Twelfth doped region;
[0081] 8: Fifth cell; 81: Fourth gate trench structure; 82: Fifth source trench structure; 821: Eighth doped region; 822: Tenth doped region; 83: Thirteenth doped region; 84: Fourteenth doped region;
[0082] 9. Interlayer medium;
[0083] 10: Drain structure.
[0084] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation
[0085] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.
[0086] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.
[0087] To address the problems of the prior art, this application provides a dual-trench silicon carbide transistor and a method for manufacturing the same. The dual-trench silicon carbide transistor provided in this application will be described below.
[0088] Figure 1 A schematic diagram of one embodiment of the dual-trench silicon carbide transistor provided in this application is shown.
[0089] like Figure 1 As shown, the dual-trench silicon carbide transistor provided in this application embodiment may include:
[0090] A silicon carbide substrate 1 of the first doping type is provided, the silicon carbide substrate 1 includes a first surface 11, and an epitaxial layer 2 of the first doping type is disposed on the first surface 11;
[0091] A second-doped well region 3 is disposed within the epitaxial layer 2;
[0092] A first cell region is provided within the epitaxial layer 2. The first cell region may include at least one first cell and at least one second cell 5, with the first cell and the second cell 5 arranged in parallel.
[0093] The first cell may include a first gate trench structure 41 disposed between the well regions 3;
[0094] The second cell 5 may include:
[0095] A second gate trench structure 51 is disposed between the well regions 3;
[0096] A first source trench structure 52 is disposed within the well region 3 and located in the outer region of the second gate trench structure 51 and spaced apart from the second gate trench structure 51. The first source trench structure 52 includes a first PN junction structure 521 disposed at the bottom of the first source trench structure 52.
[0097] The first doping type is the opposite of the second doping type.
[0098] This application provides a dual-trench silicon carbide transistor, which includes a first cell region disposed within an epitaxial layer. The first cell region includes at least one first cell and at least one second cell, arranged in parallel. The first cell includes a first gate trench structure disposed between well regions, and the second cell includes a second gate trench structure disposed between well regions. A first source trench structure is disposed within the well region, outside the second gate trench structure, and spaced from it. The first source trench structure includes a first PN junction structure disposed at its bottom. By setting the first PN junction structure within the first source trench structure, and utilizing the linear relationship between the forward voltage and temperature of the first PN junction structure under a certain current mode, the temperature of the dual-trench silicon carbide transistor itself can be detected. Furthermore, on the one hand, since the first PN junction structure is uniformly distributed within the silicon carbide metal oxide semiconductor field-effect transistor, the accuracy of temperature detection within the silicon carbide metal oxide semiconductor field-effect transistor can be improved; on the other hand, since the resistance formed between the first PN junction structures is sufficiently large within the silicon carbide metal oxide semiconductor field-effect transistor, the temperature detection signal can be amplified.
[0099] In this embodiment, the silicon carbide substrate 1 of the first doping type can be an N-type silicon carbide substrate 1; the epitaxial layer 2 of the first doping type can be an N-type epitaxial layer 2; and the well region 3 of the second doping type can be a P-type well region 3.
[0100] The first doping type is the opposite of the second doping type. It can be understood as the first doping type being either N-type or P-type, and the second doping type being either N-type or P-type. For example, if the first doping type is N-type, then the second doping type is P-type.
[0101] The second gate trench structure 51 disposed between the well regions 3 can be understood as follows: a part of the sidewall of the second gate trench structure 51 is in contact with the well region 3, another part of the sidewall of the second gate trench structure 51 is not in contact with the well region 3, and the bottom of the second gate trench structure 51 is not in contact with the well region 3.
[0102] In some alternative embodiments, the silicon carbide substrate 1 may further include a second surface 12 opposite to the first surface 11, the second surface 12 being provided with a drain structure 10.
[0103] In some alternative implementations, the first PN junction structure 521 may include:
[0104] A first doped structure 5211 of the first doped type is disposed on one side near the second gate trench structure 51;
[0105] And a first doped structure 5212 of a second doped type disposed on the side away from the second gate trench structure 51.
[0106] In this embodiment, the first doped structure 5211 of the first doping type can be an N-type first doped structure 5211, and the first doped structure 5212 of the second doping type can be a P-type first doped structure 5212.
[0107] The contact surface between the first doped structure 5211 and the first doped structure 5212 is perpendicular to the first surface 11.
[0108] In some alternative implementations, the first source trench structure 52 may further include:
[0109] A first doped region 522 of a first doped type is disposed on the side of the first PN junction structure 521 away from the first surface 11, and the first doped region 522 is insulated from the first PN junction structure 521.
[0110] In this embodiment, the first doped region 522 of the first doping type can be an N-type first doped region 522.
[0111] Optionally, an interlayer dielectric (ILD) 9 can be provided between the first doped region 522 and the first PN junction structure 521 to achieve mutual insulation between the first doped region 522 and the first PN junction structure 521. The material of the interlayer dielectric 9 can be the same as or different from the material of the gate oxide layer of the second gate trench structure 51, and is not limited here.
[0112] In some alternative implementations, the second cell 5 may further include:
[0113] A second doped region 53 of the second doping type is disposed in the well region 3 and on the side of the bottom of the first source trench structure 52 near the first surface 11;
[0114] A third doped region 54 of the first doped type is disposed within the well region 3 and spaced apart from the first source trench structure 52.
[0115] In this embodiment, the second doped region 53 of the second doping type can be a P-type second doped region 53; the third doped region 54 of the first doping type can be an N-type third doped region 54.
[0116] The second doped region 53 of the second doping type, which is located in the well region 3 and on the side of the bottom of the first source trench structure 52 near the first surface 11, can be understood as the second doped region 53 of the second doping type located in the well region 3 and in contact with the bottom of the first source trench structure 52. That is, the second doped region 53 is located in the well region 3 and is in partial or complete contact with the first source trench structure 52.
[0117] This embodiment of the application takes a first cell region comprising one first cell and one second cell 5 as an example. In actual implementation, the number of first cells and the number of second cells 5 in the first cell region can be set according to the actual situation and are not limited here. For example, the first cell region may include 100 first cells and 100 second cells 5.
[0118] Optionally, the number of the first cell corresponds to the number of the second cell 5, for example, the number of the first cell is equal to the number of the second cell 5.
[0119] like Figure 2 As shown, in some optional embodiments, the dual-trench silicon carbide transistor may further include a second cell region disposed near the first gate trench structure 41, the second cell region including a third cell 6, and the third cell 6 including a second source trench structure 61 disposed in the well region 3.
[0120] The second source trench structure 61 may include:
[0121] A fourth doped region 611 of the second doped type is disposed at the bottom of the second source trench structure 61;
[0122] And a fifth doping region 612 of the first doping type disposed in the fourth doping region 611 away from the first surface 11;
[0123] The fourth doped region 611 and the fifth doped region 612 are mutually insulated.
[0124] In this embodiment, the fourth doped region 611 of the second doping type can be a P-type fourth doped region 611, and the fifth doped region 612 of the first doping type can be an N-type fifth doped region 612.
[0125] Optionally, an interlayer dielectric (ILD) 9 can be provided between the fourth doped region 611 and the fifth doped region 612 to achieve mutual insulation between the fourth doped region 611 and the fifth doped region 612.
[0126] In some alternative implementations, the third cell 6 may further include:
[0127] A sixth doped region 62 of the second doping type is disposed in the well region 3 and on the side of the bottom of the second source trench structure 61 near the first surface 11;
[0128] A seventh doped region 63 of the first doped type is disposed within the well region 3 and spaced apart from the second source trench structure 61.
[0129] In this embodiment, the sixth doped region 62 of the second doping type can be a P-type sixth doped region 62; the seventh doped region 63 of the first doping type can be an N-type seventh doped region 63.
[0130] The sixth doped region 62 of the second doping type, which is located in the well region 3 and on the side of the bottom of the second source trench structure 61 near the first surface 11, can be understood as the sixth doped region 62 of the second doping type located in the well region 3 and in contact with the bottom of the second source trench structure 61. That is, the sixth doped region 62 is located in the well region 3 and is in partial or complete contact with the second source trench structure 61.
[0131] The second cell region can be in contact with the first cell region. Specifically, the seventh doped region 63 of the second cell region can be in contact with the first gate trench structure 41 of the first cell region.
[0132] In some alternative implementations, the dual-trench silicon carbide transistor may further include a third cell region disposed on one side near the first source trench structure 52, the third cell region may include a fourth cell 7 and a fifth cell 8 arranged in parallel.
[0133] The fourth cell 7 may include:
[0134] A third gate trench structure 71 is disposed on one side near the first source trench structure 52;
[0135] A fourth source trench structure 72 is disposed within the well region 3 and spaced apart from the third gate trench structure 71. The fourth source trench structure 72 may include a second PN junction structure 721 disposed at the bottom of the fourth source trench structure 72.
[0136] The fifth cell 8 may include:
[0137] A fourth gate trench structure 81 is disposed on one side near the fourth source trench structure 72;
[0138] A fifth source trench structure 82 is disposed within the well region 3 and spaced apart from the fourth gate trench structure 81. The fifth source trench structure 82 may include an eighth doped region 821 of the first doped type disposed at the bottom of the fifth source trench structure 82.
[0139] In this embodiment, the eighth doped region 821 of the first doping type can be an N-type eighth doped region 821.
[0140] The third cell region can be in contact with the second cell region. Specifically, the third gate trench structure 71 of the third cell region can be in contact with the third doped region 54 of the second cell region.
[0141] In some alternative implementations, the second PN junction structure 721 may include:
[0142] A third doped structure 7211 of the second doping type is disposed on one side near the third gate trench structure 71;
[0143] A fourth doped structure 7212 of the first doping type is disposed on one side near the fourth gate trench structure 81.
[0144] In this embodiment, the third doped structure 7211 of the second doping type can be a P-type third doped structure 7211; the fourth doped structure 7212 of the first doping type can be an N-type fourth doped structure 7212.
[0145] The contact surface between the third doped structure 7211 and the fourth doped structure 7212 is perpendicular to the first surface 11.
[0146] In some alternative implementations, the fourth source trench structure 72 may further include:
[0147] A ninth doped region 722 of the first doping type is disposed on the side of the second PN junction structure 721 away from the first surface 11, and the ninth doped region 722 is insulated from the second PN junction structure 721.
[0148] The fifth source trench structure 82 may also include:
[0149] A tenth doping region 822 of the first doping type is disposed on the side of the eighth doping region 821 away from the first surface 11, and the tenth doping region 822 is insulated from the eighth doping region 821.
[0150] In this embodiment, the ninth doping region 722 of the first doping type can be an N-type ninth doping region 722; the tenth doping region 822 of the first doping type can be an N-type tenth doping region 822.
[0151] Optionally, an interlayer dielectric 9 can be provided between the ninth doped region 722 and the second PN junction structure 721 to achieve mutual insulation between the ninth doped region 722 and the second PN junction structure 721; or an interlayer dielectric 9 can be provided between the tenth doped region 822 and the eighth doped region 821 to achieve mutual insulation between the tenth doped region 822 and the eighth doped region 821.
[0152] In some alternative implementations, the fourth cell 7 may further include:
[0153] An eleventh doped region 73 of the second doping type is disposed in the well region 3 and on the side of the bottom of the fourth source trench structure 72 near the first surface 11.
[0154] A twelfth doped region 74 of the first doping type is disposed within the well region 3 and spaced from the fourth source trench structure 72;
[0155] The fifth cell 8 may also include:
[0156] A thirteenth doped region 83 of the second doping type is disposed in the well region 3 and on the side of the bottom of the fifth source trench structure 82 near the first surface 11.
[0157] A fourteenth doped region 84 of the first doping type is disposed within the well region 3 and spaced apart from the fifth source trench structure 82.
[0158] In this embodiment, the eleventh doping region 73 of the second doping type can be the eleventh doping region 73 of the P-type; the twelfth doping region 74 of the first doping type can be the twelfth doping region 74 of the N-type; the thirteenth doping region 83 of the second doping type can be the thirteenth doping region 83 of the P-type; and the fourteenth doping region 84 of the first doping type can be understood as the fourteenth doping region 84 of the N-type.
[0159] The eleventh doped region 73 of the second doping type, which is located in the well region 3 and on the side of the bottom of the fourth source trench structure 72 near the first surface 11, can be understood as the eleventh doped region 73 of the second doping type located in the well region 3 and in contact with the bottom of the fourth source trench structure 72. That is, the eleventh doped region 73 is located in the well region 3 and is in partial or complete contact with the fourth source trench structure 72.
[0160] The thirteenth doped region 83 of the second doping type, which is located in the well region 3 and on the side of the bottom of the fifth source trench structure 82 near the first surface 11, can be understood as the thirteenth doped region 83 of the second doping type located in the well region 3 and in contact with the bottom of the fifth source trench structure 82. That is, the thirteenth doped region 83 is located in the well region 3 and is in partial or complete contact with the fifth source trench structure 82.
[0161] Optionally, the third doped region 54 may be in contact with the first gate trench structure 41, the second gate trench structure 51, or the third gate trench structure 71; the seventh doped region 63 may be in contact with the first gate trench structure 41; the twelfth doped region 74 may be in contact with the third gate trench structure 71 or the fourth gate trench structure 81; and the thirteenth doped region 83 may be in contact with the fourth gate trench structure 81.
[0162] In this embodiment, the first gate trench structure 41, the second gate trench structure 51, the third gate trench structure 71 and the fourth gate trench structure 81 may be the same or different, and no limitation is made here.
[0163] Optionally, the size, shape, and ion concentration of the second doped region 53, the sixth doped region 62, the eleventh doped region 73, and the thirteenth doped region 83 may be the same or different, and no limitation is made here.
[0164] In this embodiment, the first PN junction structure 521 can be understood as the first part of the temperature sensing diode (TSD) integrated in the double-groove silicon carbide transistor, the fourth doped region 611 can be understood as the second part of the temperature sensing diode integrated in the double-groove silicon carbide transistor, the second PN junction structure 721 can be understood as the third part of the temperature sensing diode integrated in the double-groove silicon carbide transistor, and the eighth doped region 821 can be understood as the fourth part of the temperature sensing diode integrated in the double-groove silicon carbide transistor. That is, the temperature sensing diode is formed by connecting the fourth doped region 611, the first PN junction structure 521, the second PN junction structure 721, and the eighth doped region 821 in series. The series resistance formed by the series connection is relatively large, which can amplify the temperature detection signal.
[0165] Figure 3This diagram illustrates the chip layout of the temperature sensing diode in the dual-trench silicon carbide transistor provided in this application. Figure 3 As shown, the temperature sensing diode may include a TSD anode and a TSD cathode. The TSD cathode may be N-type (shown in white in the figure), and the TSD anode may be P-type (shown in black in the figure). The TSD anode corresponds to the fourth doping region 611, and the TSD cathode corresponds to the eighth doping region 821. The portion between the TSD anode and the TSD cathode corresponds to the first PN junction structure 521 and the second PN junction structure 721, respectively.
[0166] It is worth noting that this embodiment uses N-type as the first doping type and P-type as the second doping type as an example. However, in actual implementation, the silicon carbide substrate 1 is not limited to N-type and can also be P-type. When the silicon carbide substrate 1 is P-type, the conductivity type of structures such as the epitaxial layer 2 and the well region 3 will also change accordingly.
[0167] Based on the dual-trench silicon carbide transistor provided in the above embodiments, this application also provides a method for manufacturing a dual-trench silicon carbide transistor. The method for manufacturing a dual-trench silicon carbide transistor will be described below.
[0168] Figure 4 A schematic flowchart of an embodiment of the dual-trench silicon carbide transistor manufacturing method provided in this application is shown.
[0169] like Figure 4 As shown, the manufacturing method of a dual-trench silicon carbide transistor may include steps S401 to S406. Please refer to the following: Figures 5 to 13 , Figures 5 to 13 This is a schematic diagram of the cross-sectional structure corresponding to a series of processes in the manufacturing method of the dual-trench silicon carbide transistor provided in this application.
[0170] S401. A silicon carbide substrate 1 of a first doping type is provided. The silicon carbide substrate 1 includes a first surface 11, on which an epitaxial layer 2 of the first doping type is disposed.
[0171] In this embodiment, the epitaxial layer 2 of the first doping type can be an N-type epitaxial layer 2.
[0172] like Figure 5 As shown, in some optional embodiments, an N-type silicon carbide substrate 1 is first provided, and then an N-type epitaxial layer 2 is formed on the silicon carbide substrate 1.
[0173] S402, A second-doped well region 3 is formed within the epitaxial layer 2.
[0174] In this embodiment, the second doped type of well region 3 can be a P-type well region 3.
[0175] like Figure 6 As shown, in some alternative embodiments, P-type ion doping is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a P-type well region 3.
[0176] S403. A first cell region is formed in the epitaxial layer 2. The first cell region includes multiple first cells and multiple second cells 5, and the first cells and second cells 5 are arranged in parallel.
[0177] The first cell includes a first gate trench structure 41 disposed between the well regions 3;
[0178] Second cell 5 includes:
[0179] A second gate trench structure 51 is disposed between the well regions 3;
[0180] A first source trench structure 52 is disposed within the well region 3 and located in the outer region of the second gate trench structure 51, and spaced apart from the second gate trench structure 51. The first source trench structure 52 includes a first PN junction structure 521 disposed at the bottom of the first source trench structure 52.
[0181] like Figures 7 to 13 As shown, in some optional embodiments, forming a first cell region within the epitaxial layer 2 may include:
[0182] A third doped region 54 of the first doping type is formed on the surface of the well region 3 away from the first surface 11; a first trench 42, a second trench 55, a third trench 56 and a fourth trench 57 are formed in the epitaxial layer 2;
[0183] A second doped region 53 of the second doping type is formed at the bottom of the second trench 55 and the bottom of the fourth trench 57;
[0184] A first gate trench structure 41 is formed in the first trench 42, a second gate trench structure 51 is formed in the third trench 56, and an interlayer dielectric 9 is formed on the surface of the second trench 55 and the surface of the fourth trench 57.
[0185] A first PN junction structure 521 is formed on the interlayer dielectric 9 of the second trench 55 and the interlayer dielectric 9 of the fourth trench 57;
[0186] An interlayer dielectric 9 is formed on the side of the first PN junction structure 521 away from the first surface 11;
[0187] A first doped region 522 of a first doped type is formed on the side of the interlayer dielectric 9 away from the first surface 11, and the interlayer dielectric 9 is formed on the upper surface of the first gate trench structure 41 and the upper surface of the second gate trench structure 42.
[0188] Optionally, ion doping of a first doping type is performed on the surface of the well region 3 away from the first surface 11 to form a third doped region 54 of the first doping type within the well region 3. Optionally, trench etching is performed downward on the surface of the epitaxial layer 2 away from the first surface 11 to form a first trench 42, a second trench 55, a third trench 56, and a fourth trench 57 in the epitaxial layer 2. For example, trench etching is performed downward on the surface of the epitaxial layer 2 away from the first surface 11 using a mask to form the first trench 42, the second trench 55, the third trench 56, and the fourth trench 57 in the epitaxial layer 2.
[0189] Optionally, a second type of ion doping is performed at the bottom of the second trench 55 and the bottom of the fourth trench 57 to form a second doped region 53 of the second type of doping at the bottom of the second trench 55 and the bottom of the fourth trench 57.
[0190] Optionally, forming a first gate trench structure 41 within the first trench 42 may include forming a first gate oxide layer within the first trench 42; and forming a first gate material on the first gate oxide layer. The first gate material may include polysilicon.
[0191] Accordingly, forming a second gate trench structure 51 within the second trench 55 may include forming a second gate oxide layer within the second trench 55; and forming a second gate material on the second gate oxide layer. The second gate material may include polysilicon. Both the first gate oxide layer and the second gate oxide layer may be interlayer dielectric 9.
[0192] Optionally, forming a first PN junction structure 521 on the interlayer dielectric 9 of the second trench 55 and the interlayer dielectric 9 of the fourth trench 57 may include: forming a fifteenth doped region (not shown) of a first doping type on the interlayer dielectric 9 of the second trench 55 and the interlayer dielectric 9 of the third trench 56; and forming a first doped structure 5211 of the first doping type and a first doped structure 5212 of the second doping type in the fifteenth doped region.
[0193] As an example, ion doping of a first doping type is performed on the interlayer medium 9 of the second trench 55 and the interlayer medium 9 of the third trench 56 to form a fifteenth doped region of the first doping type in the second trench 55 and the third trench 56; ion heavy doping of a second doping type is performed in the fifteenth doped region to form a first doped structure 5211 of the first doping type and a first doped structure 5212 of the second doping type in the fifteenth doped region.
[0194] Optionally, a first doped region 522 of the first doping type is formed on the side of the interlayer medium 9 away from the first surface 11. This can be achieved by performing ion doping of the first doping type on the side of the interlayer medium 9 away from the first surface 11 to form the first doped region 522 of the first doping type.
[0195] Optionally, after forming a first doped region 522 of the first doped type on the side of the interlayer medium 9 away from the first surface 11, metal deposition, passivation treatment, back masking, and formation of back metal can also be performed.
[0196] In some alternative embodiments, the dual-trench silicon carbide transistor may further include a second cell region disposed on one side near the first gate trench structure 41, the second cell region including a third cell 6, the third cell 6 including a second source trench structure 61 disposed in the well region 3;
[0197] The second source trench structure 61 includes:
[0198] A fourth doped region 611 of the second doped type is disposed at the bottom of the second source trench structure 61;
[0199] And a fifth doping region 612 of the first doping type disposed in the fourth doping region 611 away from the first surface 11;
[0200] The fourth doped region 611 and the fifth doped region 612 are mutually insulated.
[0201] In this embodiment, forming a third cell 6 structure within the epitaxial layer 2 may include:
[0202] A fifth trench is formed within trap region 3;
[0203] A fourth doped region 611 of the second doping type is formed in the fifth trench;
[0204] An interlayer dielectric 9 is formed on the side of the fourth doped region 611 away from the first surface 11;
[0205] A fifth doped region 612 of the first doping type is formed on the side of the interlayer medium 9 away from the first surface 11.
[0206] Optionally, trench etching is performed downward on the surface of epitaxial layer 2 away from the first surface 11 to form a fifth trench in epitaxial layer 2. For example, a mask is used to perform trench etching downward on the surface of epitaxial layer 2 away from the first surface 11 to form a fifth trench in epitaxial layer 2.
[0207] Optionally, forming a fourth doped region 611 of the second doping type in the fifth trench may include performing ion doping of the second doping type in the fifth trench to form a fourth doped region 611 of the second doping type in the fifth trench.
[0208] Optionally, a fifth doped region 612 of the first doping type is formed on the side of the interlayer medium 9 away from the first surface 11. This can be achieved by performing ion doping of the first doping type on the side of the interlayer medium 9 away from the first surface 11 to form the fifth doped region 612 of the first doping type.
[0209] In some alternative embodiments, before forming the fifth trench within the epitaxial layer 2, the method may further include:
[0210] A seventh doped region 63 of the first doping type is formed on the surface of the well region 3 away from the first surface 11.
[0211] Optionally, ion doping of the first doping type is performed on the surface of the well region 3 away from the first surface 11 to form a seventh doped region 63 of the first doping type within the well region 3.
[0212] In some alternative embodiments, after forming the fifth trench within the epitaxial layer 2, the method may further include:
[0213] A sixth doped region 62 of the second doping type is formed at the bottom of the fifth trench.
[0214] Optionally, a second type of ion doping is performed at the bottom of the fifth trench to form a sixth doped region 62 of the second type of doping at the bottom of the fifth trench.
[0215] The manufacturing method of the fourth cell 7 is similar to that of the second cell 5, and the manufacturing method of the fifth cell 8 is similar to that of the third cell 6, so it will not be described in detail here.
[0216] In some alternative embodiments, the silicon carbide substrate 1 further includes a second surface 12 opposite to the first surface 11, the second surface 12 being provided with a drain structure 10.
[0217] It is worth noting that this embodiment uses N-type as the first doping type and P-type as the second doping type as an example. However, in actual implementation, the silicon carbide substrate 1 is not limited to N-type and can also be P-type. When the silicon carbide substrate 1 is P-type, the conductivity type of structures such as the epitaxial layer 2 and the well region 3 will also change accordingly.
[0218] Regarding the trench silicon carbide transistor manufacturing method in the above embodiments, the various structures and beneficial effects have been described in detail in the embodiments related to the trench silicon carbide transistor, and will not be elaborated here.
[0219] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.
Claims
1. A dual-trench silicon carbide transistor, characterized in that, include: A silicon carbide substrate of the first doping type, the silicon carbide substrate including a first surface, on which an epitaxial layer of the first doping type is disposed; A second doped type well region is disposed within the epitaxial layer; A first cell region is disposed within the epitaxial layer, the first cell region comprising at least one first cell and at least one second cell, the first cell and the second cell being arranged in parallel; The first cell includes a first gate trench structure disposed between the well regions; The second cell includes: A second gate trench structure is disposed between the well regions; A first source trench structure is disposed within the well region and located in the outer region of the second gate trench structure, and spaced apart from the second gate trench structure. The first source trench structure includes a first PN junction structure disposed at the bottom of the first source trench structure. The first doping type is the opposite of the second doping type; The first source trench structure further includes: A first doped region of the first doping type is disposed on the side of the first PN junction structure away from the first surface, and the first doped region is insulated from the first PN junction structure.
2. The dual-trench silicon carbide transistor according to claim 1, characterized in that, The first PN junction structure includes: A first doped structure of the first doping type is disposed on one side near the second gate trench structure; And a second doped structure of the second doping type disposed on the side away from the second gate trench structure.
3. The dual-trench silicon carbide transistor according to claim 1, characterized in that, The second cell also includes: A second doped region of the second doping type is disposed within the well region and on the side of the bottom of the first source trench structure near the first surface. A third doped region of the first doping type is disposed within the well region and spaced apart from the first source trench structure.
4. The dual-trench silicon carbide transistor according to claim 1, characterized in that, The dual-trench silicon carbide transistor further includes a second cell region disposed near the first gate trench structure, the second cell region including a third cell, and the third cell including a second source trench structure disposed within the well region; The second source trench structure includes: A fourth doped region of the second doping type is disposed at the bottom of the second source trench structure; And a fifth doping region of the first doping type disposed in the fourth doping region away from the first surface; The fourth doped region and the fifth doped region are mutually insulated.
5. The dual-trench silicon carbide transistor according to claim 4, characterized in that, The third cell also includes: A sixth doped region of the second doping type is disposed within the well region and on the side of the bottom of the second source trench structure near the first surface. A seventh doped region of the first doping type is disposed within the well region and spaced apart from the second source trench structure.
6. The dual-trench silicon carbide transistor according to claim 1, characterized in that, The dual-trench silicon carbide transistor further includes a third cell region disposed near the first source trench structure, the third cell region including a fourth cell and a fifth cell arranged in parallel. The fourth cell includes: A third gate trench structure is disposed on the side close to the first source trench structure; A fourth source trench structure is disposed within the well region and spaced apart from the third gate trench structure, the fourth source trench structure including a second PN junction structure disposed at the bottom of the fourth source trench structure; The fifth cell includes: A fourth gate trench structure is disposed on one side near the fourth source trench structure; A fifth source trench structure is disposed within the well region and spaced apart from the fourth gate trench structure. The fifth source trench structure includes an eighth doped region of the first doping type disposed at the bottom of the fifth source trench structure.
7. The dual-trench silicon carbide transistor according to claim 6, characterized in that, The second PN junction structure includes: A third doped structure of the second doping type disposed on the side near the third gate trench structure; A fourth doped structure of the first doping type is disposed on one side near the fourth gate trench structure.
8. The dual-trench silicon carbide transistor according to claim 6, characterized in that, The fourth source trench structure further includes: A ninth doped region of the first doping type is disposed on the side of the second PN junction structure away from the first surface, and the ninth doped region is insulated from the second PN junction structure. The fifth source trench structure further includes: A tenth doping region of the first doping type is disposed on the side of the eighth doping region away from the first surface, and the tenth doping region is insulated from the eighth doping region.
9. The dual-trench silicon carbide transistor according to claim 8, characterized in that, The fourth cell also includes: The eleventh doped region of the second doping type is disposed within the well region and on the side of the bottom of the fourth source trench structure near the first surface. A twelfth doped region of the first doping type is disposed within the well region and spaced apart from the fourth source trench structure; The fifth cell also includes: The thirteenth doped region of the second doping type is disposed within the well region and on the side of the bottom of the fifth source trench structure near the first surface. The fourteenth doped region of the first doping type is disposed within the well region and spaced apart from the fifth source trench structure.
10. A method for manufacturing a dual-trench silicon carbide transistor, characterized in that, include: A silicon carbide substrate of a first doping type is provided, the silicon carbide substrate including a first surface, and an epitaxial layer of the first doping type is disposed on the first surface; A second type of doped well region is formed within the epitaxial layer; A first cell region is formed within the epitaxial layer, the first cell region comprising at least one first cell and at least one second cell, the first cell and the second cell being arranged in parallel; The first cell includes a first gate trench structure disposed between the well regions; The second cell includes: A second gate trench structure is disposed between the well regions; A first source trench structure is disposed within the well region and located in the outer region of the second gate trench structure, and spaced apart from the second gate trench structure. The first source trench structure includes a first PN junction structure disposed at the bottom of the first source trench structure. The first source trench structure further includes: A first doped region of the first doping type is disposed on the side of the first PN junction structure away from the first surface, and the first doped region is insulated from the first PN junction structure.