LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a preparation method thereof, wherein the LDMOS device comprises a substrate, a metal silicide reaction barrier layer, a metal silicide layer, a first etching stop layer and a first interlayer dielectric layer, a first metal plug, a second etching stop layer and a second interlayer dielectric layer, a second metal plug, a third etching stop layer, a third interlayer dielectric layer and a third metal plug. The metal silicide reaction barrier layer, the first etching stop layer and the first interlayer dielectric layer form a first field plate; the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer and the second interlayer dielectric layer form a second field plate. In the application, the first field plate and the second field plate are short-circuited to a source terminal or a gate terminal or form an independent electrode through the multiple metal plugs without additional process steps, so that the electric field distribution can be effectively adjusted and the breakdown voltage can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to an LDMOS device and a preparation method thereof. BACKGROUND

[0002] DMOS (Double-diffused MOS) devices are widely used in power management circuits due to their high voltage resistance, large current driving capability and extremely low power consumption. In an LDMOS (Lateral Double-diffused MOS) device, the on-resistance is an important indicator.

[0003] In a BCD process, although the LDMOS is integrated in the same chip as the CMOS, due to the requirements of high voltage resistance and low characteristic resistance, the on-resistance R_sp of the current LDMOS device is in conflict with the breakdown voltage BV, and a higher breakdown voltage and a lower characteristic resistance are needed to improve the competitiveness of the product.

[0004] The existing LDMOS device usually uses a metal silicide reaction barrier layer in the Salicide (Self-Aligned Silicide) process technology as the field plate dielectric layer of the LDMOS device, and uses a contact hole as a field plate conductive electrode. However, for a higher BV LDMOS device, a single field plate dielectric layer often cannot meet the design requirements of the optimal BV / Rsp (higher breakdown voltage and lower characteristic resistance). SUMMARY

[0005] The present application provides an LDMOS device and a preparation method thereof, which can solve the problem that the field plate dielectric layer of the current LDMOS device cannot meet the design requirements of high BV / low Rsp.

[0006] In one aspect, the present application provides an LDMOS device, comprising:

[0007] a substrate, an epitaxial layer and a gate structure on the substrate are formed, wherein a drift region, a body region, a P-type heavily doped region and an N-type heavily doped region are formed in the epitaxial layer;

[0008] a metal silicide reaction barrier layer, the metal silicide reaction barrier layer covers the drift region;

[0009] a metal silicide layer, the metal silicide layer covers the P-type heavily doped region and the N-type heavily doped region;

[0010] a first etching stop layer and a first interlayer dielectric layer stacked, the first etching stop layer covering the metal silicide reaction barrier layer and the metal silicide layer, the first interlayer dielectric layer covering the first etching stop layer;

[0011] a first metal plug respectively leading out the gate structure, the P-type heavily doped region and the N-type heavily doped region to a surface of the first interlayer dielectric layer;

[0012] a second etching stop layer and a second interlayer dielectric layer stacked, the second etching stop layer covering the first interlayer dielectric layer, the second interlayer dielectric layer covering the second etching stop layer;

[0013] a second metal plug respectively leading out the first metal plug, the first interlayer dielectric layer to a surface of the second interlayer dielectric layer;

[0014] a third etching stop layer and a third interlayer dielectric layer stacked, the third etching stop layer covering the second interlayer dielectric layer, the third interlayer dielectric layer covering the third etching stop layer;

[0015] a third metal plug respectively leading out the second metal plug, the second interlayer dielectric layer to a surface of the third interlayer dielectric layer;

[0016] wherein the metal silicide reaction barrier layer, the first etching stop layer and the first interlayer dielectric layer constitute a first field plate of the device; the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer and the second interlayer dielectric layer constitute a second field plate of the device.

[0017] Optionally, in the LDMOS device, an upper surface of the first interlayer dielectric layer is flat.

[0018] Optionally, in the LDMOS device, the LDMOS device further comprises a first silicon oxide layer between the first interlayer dielectric layer and the second etching stop layer.

[0019] Optionally, in the LDMOS device, the first etching stop layer comprises a second silicon oxide layer and a silicon nitride layer stacked, the second silicon oxide layer covering the metal silicide reaction barrier layer and the metal silicide layer, the silicon nitride layer covering the second silicon oxide layer.

[0020] Optionally, in the LDMOS device, the second etching stop layer is SiCN; the third etching stop layer is SiCN.

[0021] Optionally, in the LDMOS device, the gate structure comprises a gate oxide layer, a polysilicon gate on the gate oxide layer, and a sidewall on both sides of the polysilicon gate.

[0022] In another aspect, the embodiments of the present application also provide a method for manufacturing an LDMOS device, comprising:

[0023] A substrate is provided, and an epitaxial layer and a gate structure on the epitaxial layer are formed on the substrate, wherein the epitaxial layer comprises a drift region, a body region, a P-type heavily doped region, and an N-type heavily doped region;

[0024] A metal silicide reaction barrier layer is formed, and the metal silicide reaction barrier layer covers the drift region;

[0025] A metal silicide layer is formed, and the metal silicide layer covers the P-type heavily doped region and the N-type heavily doped region;

[0026] A first etching stop layer and a first interlayer dielectric layer are formed in a stack, the first etching stop layer covers the metal silicide reaction barrier layer and the metal silicide layer, and the first interlayer dielectric layer covers the first etching stop layer;

[0027] A first metal plug is formed to lead out the gate structure, the P-type heavily doped region, and the N-type heavily doped region to a surface of the first interlayer dielectric layer, respectively;

[0028] A second etching stop layer and a second interlayer dielectric layer are formed in a stack, the second etching stop layer covers the first interlayer dielectric layer, and the second interlayer dielectric layer covers the second etching stop layer;

[0029] A second metal plug is formed to lead out the first metal plug and the first interlayer dielectric layer to a surface of the second interlayer dielectric layer, respectively;

[0030] A third etching stop layer and a third interlayer dielectric layer are formed in a stack, the third etching stop layer covers the second interlayer dielectric layer, and the third interlayer dielectric layer covers the third etching stop layer;

[0031] A third metal plug is formed to lead out the second metal plug and the second interlayer dielectric layer to a surface of the third interlayer dielectric layer, respectively;

[0032] The metal silicide reaction barrier layer, the first etching stop layer, and the first interlayer dielectric layer constitute a first field plate of the device; and the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer, and the second interlayer dielectric layer constitute a second field plate of the device.

[0033] Optionally, in the method for manufacturing the LDMOS device, after the first etching stop layer and the first interlayer dielectric layer are formed in a stack, the method for manufacturing the LDMOS device further comprises:

[0034] performing a CMP process on the first interlayer dielectric layer to planarize an upper surface of the first interlayer dielectric layer.

[0035] Optionally, in the method for manufacturing the LDMOS device, after the first metal plug is formed, and before the second etching stop layer is formed, the method for manufacturing the LDMOS device further comprises:

[0036] forming a first silicon oxide layer covering the first interlayer dielectric layer and the first metal plug.

[0037] Optionally, in the method for manufacturing the LDMOS device, the step of forming the first etching stop layer comprises:

[0038] forming a second silicon oxide layer covering the metal silicide reaction barrier layer and the metal silicide layer, and a silicon nitride layer covering the second silicon oxide layer.

[0039] The technical scheme of the present application has at least the following advantages:

[0040] The present application uses the combination of the metal silicide reaction barrier layer, the first etching stop layer and the first interlayer dielectric layer as the first field plate of the LDMOS device; and uses the combination of the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer and the second interlayer dielectric layer as the second field plate of the LDMOS device. The present application does not need to increase additional process steps to manufacture the first field plate and the second field plate, only needs to adjust the layout of the device appropriately, and short-circuits the first field plate and the second field plate to the source terminal or the gate terminal or an independent electrode through the multiple metal plugs (the first metal plug, the second metal plug and the third metal plug), so that the electric field distribution can be effectively adjusted and the breakdown voltage can be improved, thereby meeting the design requirements of high BV / low Rsp. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical scheme in the specific embodiments or prior art of the present application, the drawings needed in the specific embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0042] Figures 1-6is a schematic diagram of a semiconductor structure in each process step of preparing the LDMOS device of the embodiment of the present application;

[0043] In the drawings: reference numerals

[0044] 101-P-type substrate, 102-drift region, 103-gate oxide layer, 104-poly-silicon gate, 105-P-type body region, 106-side wall, 107-P-type heavily doped region, 108-N-type heavily doped region, 109-metal silicidation reaction barrier layer, 110-metal silicide layer, 111-first etching stop layer, 112-first interlayer dielectric layer, 113-first metal plug, 114-second etching stop layer, 115-second interlayer dielectric layer, 116-second metal plug, 116-1-second metal plug used as a conductive layer of a first field plate of the device, 117-third etching stop layer, 118-third interlayer dielectric layer, 119-third metal plug, 119-1-third metal plug used as a conductive layer of a second field plate of the device. DETAILED DESCRIPTION

[0045] The technical solutions in the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.

[0046] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0047] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements, it can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0049] The present application provides a preparation method of an LDMOS device. Figures 1-6 , Figures 1-6 is a semiconductor structure schematic diagram in each process step of the preparation method of the LDMOS device.

[0050] Specifically, the present embodiment takes an N-LDMOS device as an example, and the preparation method of the LDMOS device comprises the following steps.

[0051] First, as shown in Figure 1 , a substrate 101 is provided, an epitaxial layer can be formed on the substrate 101, further, a gate structure can be formed on the epitaxial layer, wherein a drift region 102, a P-type body region 105, a P-type heavily doped region 107 and an N-type heavily doped region 108 are formed in the epitaxial layer. Specifically, the drift region 102 is located in the upper half (including the top end) of the epitaxial layer, and the gate structure can comprise a gate oxide layer 103, a polysilicon gate 104 located on the gate oxide layer 103 and a sidewall 106 located on both sides of the polysilicon gate 104.

[0052] Then, as shown in Figure 2 , a metal silicide reaction barrier layer 109 is formed, which covers the drift region 102 and covers part of the surface of the N-type heavily doped region 108 on the left side of the sidewall 106 periphery and part of the surface of the N-type heavily doped region 108 on the right side. Preferably, the material of the metal silicide reaction barrier layer 109 can be silicon oxide.

[0053] Next, in the metal silicide reaction, a metal silicide layer 110 is formed, which covers the P-type heavily doped region 107 and the N-type heavily doped region 108, i.e. the metal silicide layer 110 is formed on the semiconductor structure surface which is not covered by the metal silicide reaction barrier layer 109.

[0054] Further, a stacked first etching stop layer 111 and a first interlayer dielectric layer 112 are formed, the first etching stop layer 111 covers the metal silicide reaction barrier layer 109 and the metal silicide layer 110, and the first interlayer dielectric layer 112 covers the first etching stop layer 111. Specifically, the step of forming the first etching stop layer can comprise: forming a stacked second silicon oxide layer and a silicon nitride layer, the second silicon oxide layer covers the metal silicide reaction barrier layer and the metal silicide layer, and the silicon nitride layer covers the second silicon oxide layer.

[0055] Preferably, after forming the first etching stop layer 111 and the first interlayer dielectric layer 112 of the stack, the method for fabricating the LDMOS device further comprises: performing a CMP process on the first interlayer dielectric layer 112 to planarize the upper surface of the first interlayer dielectric layer 112.

[0056] Next, as shown in FIG. 1C, a first metal plug 113 is formed through the first interlayer dielectric layer 112 and the first etching stop layer 111 to respectively lead out the gate structure, the P-type heavily doped region 107 and the N-type heavily doped region 108 to the surface of the first interlayer dielectric layer 112. Figure 3

[0057] Preferably, after forming the first metal plug 113 and before forming the second etching stop layer, the method for fabricating the LDMOS device further comprises: forming a first silicon oxide layer covering the first interlayer dielectric layer 112 and the first metal plug 113.

[0058] Further, a second etching stop layer 114 and a second interlayer dielectric layer 115 of a stack are formed, the second etching stop layer 114 covering the first interlayer dielectric layer 112, and the second interlayer dielectric layer 115 covering the second etching stop layer 114.

[0059] Next, as shown in FIG. 1E, a second metal plug 116 is formed through the second etching stop layer 114 and the second interlayer dielectric layer 115, the second metal plug 116 being a copper layer of damascene process to respectively lead out the first metal plug 113 and the first interlayer dielectric layer 112 to the surface of the second interlayer dielectric layer 115. Figure 4 Further, as shown in FIG. 1F, a third etching stop layer 117 and a third interlayer dielectric layer 118 of a stack are formed, the third etching stop layer 117 covering the second interlayer dielectric layer 115, and the third interlayer dielectric layer 118 covering the third etching stop layer 117.

[0060] Figure 5 Finally, as shown in FIG. 1G, a third metal plug 119 is formed through the third etching stop layer 117 and the third interlayer dielectric layer 118 to respectively lead out the second metal plug 116 and the second interlayer dielectric layer 115 to the surface of the third interlayer dielectric layer 118.

[0061] Figure 6

[0062] ​​​​The metal silicide reaction barrier layer 109, the first etching stop layer 111 and the first interlayer dielectric layer 112 constitute a first field plate of the device; and the metal silicide reaction barrier layer 109, the first etching stop layer 111, the first interlayer dielectric layer 112, the second etching stop layer 114 and the second interlayer dielectric layer 115 constitute a second field plate of the device.

[0063] In the embodiment, the second metal plug in contact with the first interlayer dielectric layer 112 is a second metal plug 116-1 used as a conductive layer of a first field plate of the device. The third metal plug in contact with the second interlayer dielectric layer 115 is a third metal plug 119-1 used as a conductive layer of a second field plate of the device.

[0064] Based on the same inventive concept, the embodiment of the present application provides an LDMOS device, as shown in the accompanying drawings. Figure 6 The LDMOS device comprises:

[0065] a substrate 101, on which an epitaxial layer and a gate structure on the epitaxial layer are formed, wherein the epitaxial layer has a drift region 102, a P-type body region 105, a P-type heavily doped region 107 and an N-type heavily doped region 108 formed therein; specifically, the drift region 102 is located in the upper half (including the top end) of the epitaxial layer, and the gate structure can include a gate oxide layer 103, a polysilicon gate 104 on the gate oxide layer 103 and a sidewall 106 on both sides of the polysilicon gate 104;

[0066] a metal silicide reaction barrier layer 109, which covers the drift region 102, a part of the surface of the N-type heavily doped region 108 on the left side of the sidewall 106 and a part of the surface of the N-type heavily doped region 108 on the right side;

[0067] a metal silicide layer 110, which covers the P-type heavily doped region 107 and the N-type heavily doped region 108;

[0068] a first etching stop layer 111 and a first interlayer dielectric layer 112 stacked, the first etching stop layer 111 covering the metal silicide reaction barrier layer 109 and the metal silicide layer 110, and the first interlayer dielectric layer 112 covering the first etching stop layer 111, wherein the upper surface of the first interlayer dielectric layer 112 is flat;

[0069] a first metal plug 113, which leads the gate structure, the P-type heavily doped region 107 and the N-type heavily doped region 108 to the surface of the first interlayer dielectric layer 112, respectively;

[0070] a second etching stop layer 114 covering the first interlayer dielectric layer 112 and a second interlayer dielectric layer 115 covering the second etching stop layer 114;

[0071] a second metal plug 116 penetrating through the second etching stop layer 114 and the second interlayer dielectric layer 115, the second metal plug 116 leading out the first metal plug 113 and the first interlayer dielectric layer 112 to a surface of the second interlayer dielectric layer 115, respectively;

[0072] a third etching stop layer 117 covering the second interlayer dielectric layer 115 and a third interlayer dielectric layer 118 covering the third etching stop layer 117; and,

[0073] a third metal plug 119 penetrating through the third etching stop layer 117 and the third interlayer dielectric layer 118, the third metal plug 119 leading out the second metal plug 116 and the second interlayer dielectric layer 115 to a surface of the third interlayer dielectric layer 118, respectively;

[0074] wherein the metal silicide reaction barrier layer 109, the first etching stop layer 111 and the first interlayer dielectric layer 112 constitute a first field plate of the device; the metal silicide reaction barrier layer 109, the first etching stop layer 111, the first interlayer dielectric layer 112, the second etching stop layer 114 and the second interlayer dielectric layer 115 constitute a second field plate of the device.

[0075] In the embodiment, the second metal plug in contact with the first interlayer dielectric layer 112 is the second metal plug 116-1 serving as a conductive layer of the first field plate of the device. The third metal plug in contact with the second interlayer dielectric layer 115 is the third metal plug 119-1 serving as a conductive layer of the second field plate of the device.

[0076] Preferably, the LDMOS device can further comprise a first silicon oxide layer between the first interlayer dielectric layer 112 and the second etching stop layer 114.

[0077] Preferably, the first etching stop layer 111 can comprise a second silicon oxide layer covering the metal silicide reaction barrier layer 109 and the metal silicide layer 110 and a silicon nitride layer covering the second silicon oxide layer.

[0078] In the embodiment, the second etching stop layer 114 includes but is not limited to SiCN; and the third etching stop layer 117 includes but is not limited to SiCN.

[0079] In summary, the combination of the metal silicide reaction barrier layer 109, the first etching stop layer 111 and the first interlayer dielectric layer 112 is used as the first field plate of the LDMOS device; and the combination of the metal silicide reaction barrier layer 109, the first etching stop layer 111, the first interlayer dielectric layer 112, the second etching stop layer 114 and the second interlayer dielectric layer 115 is used as the second field plate of the LDMOS device. The present application does not need additional process steps to make the first field plate and the second field plate, only needs to make appropriate adjustments to the layout of the LDMOS device, and through the multiple metal plugs (the first metal plug 113, the second metal plug 116 and the third metal plug 119) to short the first field plate and the second field plate to the source terminal (the P-type heavily doped region 107 and the N-type heavily doped region 108) or the gate terminal (the polysilicon gate 104) or to an independent electrode, so as to effectively adjust the electric field distribution and improve the breakdown voltage, and meet the design requirements of high BV / low Rsp.

[0080] Obviously, the above-mentioned embodiments are only examples for clearly illustrating, but not limit the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted, and the obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. An LDMOS device, characterized by, The LDMOS device comprises: a substrate, an epitaxial layer and a gate structure formed on the epitaxial layer are formed on the substrate, wherein the epitaxial layer is formed with a drift region, a body region, a P-type heavily doped region and an N-type heavily doped region; a metal silicide reaction barrier layer covering the drift region; a metal silicide layer covering the P-type heavily doped region and the N-type heavily doped region; a first etching stop layer and a first interlayer dielectric layer are stacked, the first etching stop layer covers the metal silicide reaction barrier layer and the metal silicide layer, and the first interlayer dielectric layer covers the first etching stop layer; a first metal plug respectively leading the gate structure, the P-type heavily doped region and the N-type heavily doped region to the surface of the first interlayer dielectric layer; a second etching stop layer and a second interlayer dielectric layer are stacked, the second etching stop layer covers the first interlayer dielectric layer, and the second interlayer dielectric layer covers the second etching stop layer; a second metal plug respectively leading the first metal plug and the first interlayer dielectric layer to the surface of the second interlayer dielectric layer; a third etching stop layer and a third interlayer dielectric layer are stacked, the third etching stop layer covers the second interlayer dielectric layer, and the third interlayer dielectric layer covers the third etching stop layer; a third metal plug respectively leading the second metal plug and the second interlayer dielectric layer to the surface of the third interlayer dielectric layer; wherein the metal silicide reaction barrier layer, the first etching stop layer and the first interlayer dielectric layer constitute a first field plate of the device; the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer and the second interlayer dielectric layer constitute a second field plate of the device.

2. The LDMOS device of claim 1, wherein, The upper surface of the first interlayer dielectric layer is flat.

3. The LDMOS device of claim 1, wherein, The LDMOS device further comprises a first silicon oxide layer between the first interlayer dielectric layer and the second etching stop layer.

4. The LDMOS device of claim 1, wherein, The first etching stop layer comprises a second silicon oxide layer and a silicon nitride layer stacked, the second silicon oxide layer covers the metal silicide reaction barrier layer and the metal silicide layer, and the silicon nitride layer covers the second silicon oxide layer.

5. The LDMOS device of claim 1, wherein, The second etching stop layer is SiCN, and the third etching stop layer is SiCN.

6. The LDMOS device of claim 1, wherein, The gate structure comprises a gate oxide layer, a polysilicon gate on the gate oxide layer and a sidewall on both sides of the polysilicon gate.

7. A method of fabricating an LDMOS device, characterized by, The method comprises: providing a substrate, an epitaxial layer and a gate structure formed on the epitaxial layer are formed on the substrate, wherein the epitaxial layer is formed with a drift region, a body region, a P-type heavily doped region and an N-type heavily doped region; forming a metal silicide reaction barrier layer covering the drift region; forming a metal silicide layer covering the P-type heavily doped region and the N-type heavily doped region; forming a first etching stop layer and a first interlayer dielectric layer in a stack, the first etching stop layer covering the metal silicide reaction barrier layer and the metal silicide layer, the first interlayer dielectric layer covering the first etching stop layer; forming a first metal plug to lead out the gate structure, the P-type heavily doped region and the N-type heavily doped region to a surface of the first interlayer dielectric layer, respectively; forming a second etching stop layer and a second interlayer dielectric layer in a stack, the second etching stop layer covering the first interlayer dielectric layer, the second interlayer dielectric layer covering the second etching stop layer; forming a second metal plug to lead out the first metal plug, the first interlayer dielectric layer to a surface of the second interlayer dielectric layer, respectively; forming a third etching stop layer and a third interlayer dielectric layer in a stack, the third etching stop layer covering the second interlayer dielectric layer, the third interlayer dielectric layer covering the third etching stop layer; forming a third metal plug to lead out the second metal plug, the second interlayer dielectric layer to a surface of the third interlayer dielectric layer, respectively; wherein the metal silicide reaction barrier layer, the first etching stop layer and the first interlayer dielectric layer constitute a first field plate of the device; the metal silicide reaction barrier layer, the first etching stop layer, the first interlayer dielectric layer, the second etching stop layer and the second interlayer dielectric layer constitute a second field plate of the device.

8. The method of claim 7, wherein the LDMOS device is formed by: After forming the first etching stop layer and the first interlayer dielectric layer in the stack, the method for manufacturing the LDMOS device further comprises: performing a CMP process on the first interlayer dielectric layer to planarize an upper surface of the first interlayer dielectric layer.

9. The method of claim 7, wherein the LDMOS device is formed by the steps of: After forming the first metal plug, and before forming the second etching stop layer, the method for manufacturing the LDMOS device further comprises: forming a first silicon oxide layer, the first silicon oxide layer covering the first interlayer dielectric layer and the first metal plug.

10. The method of claim 7, wherein the LDMOS device is formed by: The step of forming the first etching stop layer comprises: forming a second silicon oxide layer and a silicon nitride layer in a stack, the second silicon oxide layer covering the metal silicide reaction barrier layer and the metal silicide layer, the silicon nitride layer covering the second silicon oxide layer.

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