Semiconductor device with schottky diode and method of manufacturing the same

Abstract

The application discloses a semiconductor device with a Schottky diode and a manufacturing method thereof. According to an embodiment, the semiconductor device comprises a substrate with a first surface and a second surface, a well region, a source region in the well region, a contact region in contact with the well region and the source region, a Schottky region, and a source metal layer with a first part in contact with the Schottky region to form a Schottky diode, the Schottky region being surrounded by the well region and the contact region in a first plane perpendicular to a direction from the first surface to the second surface. The application also provides a method for manufacturing the semiconductor device. The semiconductor device according to the application has a high switching speed, a high chip density and a low cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and more particularly, to a semiconductor device with Schottky diode and a manufacturing method thereof. BACKGROUND

[0002] Semiconductor devices, such as silicon carbide (SiC) semiconductor devices, such as silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs), have a wide range of applications, such as power devices for electric vehicles. However, the existing device structure has many deficiencies, such as large cell pitch. This not only makes the device size large and the chip density low, thereby increasing the cost, but also affects the device opening speed, which is not conducive to high-speed applications. SUMMARY

[0003] The present application proposes a semiconductor device with Schottky diode and a manufacturing method thereof to solve one or more technical problems in the prior art.

[0004] According to an aspect of the present application, a semiconductor device with Schottky diode is provided. The semiconductor device includes: a substrate of a first conductivity type, the substrate having a first face and a second face; a well region of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the well region being located in the substrate and extending from the first face toward the second face; a source region of the first conductivity type, the source region being located in the well region and extending from the first face toward the second face; a contact region of the second conductivity type, the contact region being located in the substrate and extending from the first face toward the second face, the contact region contacting the well region and the source region; a Schottky region extending from the first face toward the second face, the Schottky region being a part of the substrate; and a source metal layer disposed on the first face, a first portion of the source metal layer contacting the Schottky region to form a Schottky diode, the Schottky region being surrounded by the well region and the contact region in a first plane perpendicular to a direction from the first face toward the second face.

[0005] According to another aspect of the present application, a semiconductor device with Schottky diode is provided. The semiconductor device includes: a substrate of a first conductivity type, the substrate having a first face and a second face; a plurality of well regions of a second conductivity type disposed in the substrate, the second conductivity type being opposite to the first conductivity type; a plurality of source regions, each source region being disposed in a corresponding well region; a plurality of contact regions of the second conductivity type, each contact region contacting adjacent well regions and source regions, the contact regions having a higher impurity concentration than the well regions; and a plurality of Schottky regions, each Schottky region being surrounded by the well regions and the contact regions in a first plane, the first plane being perpendicular to a direction from the first face toward the second face.

[0006] According to a further aspect of the present application, a method of fabricating a semiconductor device having a Schottky diode is provided. The method includes providing a substrate of a first conductivity type, the substrate having a first side and a second side; forming a well region of a second conductivity type in the substrate; forming a source region of the first conductivity type in the well region; simultaneously forming a Schottky region of the first conductivity type and a contact region of the second conductivity type in the substrate, such that the contact region contacts the well region and the source region, and such that the Schottky region is surrounded by the well region and the contact region in a first plane perpendicular to a direction from the first side toward the second side; and forming a source metal layer on the first side, such that the source metal layer forms a Schottky diode with the Schottky region and forms an ohmic contact with the source region and the contact region.

[0007] The semiconductor device having a Schottky diode and the method of fabricating the same according to the present application have many technical advantages. For example, the semiconductor device according to embodiments of the present application has a small device size, a high switching speed, and a high chip density, as compared to the prior art, which not only reduces the chip manufacturing cost, but also expands the application range, such as being suitable for high speed applications. The semiconductor device according to embodiments of the present application also overcomes the disadvantages of the body diode in the prior art, thereby improving the device characteristics. Further, the method according to embodiments of the present application does not need to add a new process step, especially an expensive mask, and uses a self-alignment method and a novel design of the window of the hard mask to embed the Schottky diode in the device, thereby improving the device characteristics without sacrificing the process complexity, while being cost effective. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a plan view of a semiconductor device according to a first embodiment of the present application;

[0009] Figure 2A is Figure 1 is a cross-sectional view along AA;

[0010] Figure 2B is Figure 1 is a cross-sectional view along BB;

[0011] Figure 2C is Figure 1 is a cross-sectional view along CC;

[0012] Figure 2D is Figure 1 is a cross-sectional view along DD;

[0013] Figures 3A-3C is a schematic view of forming a well region according to a second embodiment of the present application;

[0014] Figures 4A-4C is a schematic view of forming a source region according to a second embodiment of the present application;

[0015] Figures 5A-5C is a schematic view of removing the first hard mask and the spacer layer according to the second embodiment of the present application;

[0016] Figures 6A-6C is a schematic view of forming the second hard mask according to the second embodiment of the present application;

[0017] Figures 7A-7C is a schematic view of forming the contact region according to the second embodiment of the present application;

[0018] Figures 8A-8C is a schematic view of forming the dielectric layer and the gate according to the second embodiment of the present application;

[0019] Figures 9A-9C is a schematic view of forming the source metal layer according to the second embodiment of the present application. DETAILED DESCRIPTION

[0020] For the purpose of facilitating the understanding of the present application, a plurality of exemplary embodiments will be described below in conjunction with the relevant drawings. It should be understood by those skilled in the art that the embodiments herein are merely for the purpose of illustrating the present application, and by no means limit the present application.

[0021] Figure 1 is a plan view of a semiconductor device according to the first embodiment of the present application. Figures 2A-2D is Figure 1 are cross-sectional structure schematic views along AA, BB, CC, and DD, respectively. For the purpose of brevity, each schematic view only shows a portion of the device structure, for example, a typical portion. Also, when the device includes a plurality of repeating units, only one or several repeating units are shown.

[0022] As shown, the semiconductor device 100 includes a substrate 102, a well region 110, a source region 120, a contact region 130, a Schottky region 140, and a source metal layer 180. The substrate 102 has a first conductivity type (for example, N-type), and has a first surface 102a and a second surface 102b, the first surface 102a being opposite to the second surface 102b. The well region 110 has a second conductivity type (for example, P-type), and is located in the substrate 102 and extends from the first surface 102a toward the second surface 102b (z-direction in the figure). Figures 2A-2D The source region 120 has the first conductivity type, is located in the well region 110 and extends from the first surface 102a toward the second surface 102b. The contact region 130 has the second conductivity type, is located in the substrate 102 and extends from the first surface 102a toward the second surface 102b, and the contact region 130 contacts the well region 110 and the source region 130. The Schottky region 140 extends from the first surface 102a toward the second surface 102b, and the Schottky region 140 is a portion of the substrate 102.

[0023] The source metal layer 180 is disposed on the first surface 102a, and at least a portion (i.e., a first portion) of the source metal layer 180 is in contact with the Schottky region 140 to form a Schottky diode or a Schottky contact 182. In addition, at least another portion (i.e., a second portion) of the source metal layer 180 is in contact with the contact region 130 to form an ohmic contact 184. At least still another portion (i.e., a third portion) of the source metal layer 180 is in contact with the source region 130 to form an ohmic contact 186.

[0024] The depths (i.e., depths in the z-direction in the xz-plane) of the contact region 130 and the well region 110 can be set according to actual needs. For example, in one embodiment, the depth of the well region 110 ranges from 0.6 micrometers (um) to 1.8 um, such as 0.6 um, 0.8 um, 1.0 um, 1.2 um, 1.4 um, 1.6 um, 1.8 um, etc. The depth of the contact region 130 ranges from 0.4 um to 1.8 um, such as 0.4 um, 0.8 um, 1.2 um, 1.6 um, 1.8 um, etc. In other embodiments, other depth values are also possible.

[0025] As shown in FIG. 1, the semiconductor device 100 further includes a gate 170 disposed on the first surface 102a. The gate 170 is of a second conductive type, which is opposite to the first conductive type. The gate 170 is disposed on the first surface 102a, and extends from the first surface 102a toward the second surface 102b. The gate 170 is disposed on the well region 110, and is in contact with the well region 110. The gate 170 is also disposed on the JFET region 150, and is in contact with the JFET region 150. The gate 170 is also disposed on the Schottky region 140, and is in contact with the Schottky region 140. The gate 170 is also disposed on the substrate 102, and is in contact with the substrate 102. The gate 170 is also disposed on the contact region 130, and is in contact with the contact region 130. The gate 170 is also disposed on the source region 130, and is in contact with the source region 130. The gate 170 is also disposed on the drain region 120, and is in contact with the drain region 120. Figures 2A-2D The gate 170 is disposed on the first surface 102a, and is in contact with the substrate 102. The gate 170 is disposed on the first surface 102a, and is in contact with the well region 110. The gate 170 is disposed on the first surface 102a, and is in contact with the JFET region 150. The gate 170 is disposed on the first surface 102a, and is in contact with the Schottky region 140. The gate 170 is disposed on the first surface 102a, and is in contact with the contact region 130. The gate 170 is disposed on the first surface 102a, and is in contact with the source region 130. The gate 170 is disposed on the first surface 102a, and is in contact with the drain region 120.

[0026] In addition, the semiconductor device 100 further includes a junction field effect (JFET) region 150. The JFET region 150 is disposed under at least a portion of the gate 170, and is located in the substrate 102, and extends from the first surface 102a toward the second surface 102b. The JFET region 150 is of the first conductive type, and can have the same impurity concentration as a portion of the substrate 102, or can have a higher impurity concentration. The depth and impurity profile of the JFET region 150 can be adjusted according to actual needs.

[0027] Referring again to FIG. 1, Figure 1In at least one plane perpendicular to the direction in which the first face 102a faces the second face 102b (i.e., the first plane, which in the present figure is exemplified as the xy plane, the first plane is perpendicular to the z axis), the Schottky region 140 is surrounded by the well region 110 and the contact region 130. The boundary of the Schottky region 140 is exemplified as a quadrilateral, with opposite edges along the x direction (first opposite edges) in contact with the well region 110, and opposite edges along the y direction (second opposite edges) in contact with the contact region 130. In at least one direction (in the present embodiment, the x direction), the length of at least one edge of the boundary of the Schottky region 140 (in the present embodiment, the first direction is exemplified as the x direction) ranges from 0.8 um to 2.5 um, such as 0.8 um, 1.0 um, 1.5 um, 1.8 um, 2.2 um, 2.5 um, etc. In other embodiments, other length values are possible.

[0028] Further, in at least one direction of the first plane (in the present embodiment, the x direction), the JFET region 150 separates the well regions 110. For example, at least a portion of the JFET region 150 and the substrate 102 is disposed between adjacent well regions 110.

[0029] In the prior art, the source contact width is typically equal to a portion of the source region width plus the width of the contact region. In contrast, in accordance with the device design of embodiments of the present application, such as with reference to Figure 2B , the source contact width is equal to the width W of the contact region 130 in the xz plane along the x direction. That is, in contrast to the prior art, the device structure in accordance with embodiments of the present application enables a smaller cell pitch, thereby enabling a smaller device area, which increases the chip density, which is cost advantageous. Further, the smaller device area is advantageous for the switching speed of the device, which enables the device to be suitable for fast switching applications.

[0030] Further, semiconductors typically have a body diode. The performance of the body diode has a non-negligible impact on the overall performance of the device. For many semiconductor devices, such as SiC devices, the body diode has a high turn-on voltage (e.g., up to 4 V), which is typically disadvantageous because the body diode is difficult to turn on during operation, which greatly degrades the operating speed of the semiconductor device, which is not effective for high speed device applications. In accordance with the device structure of embodiments of the present application, a Schottky diode is embedded, which greatly improves the turn-on capability of the body diode (e.g., for SiC devices, the turn-on voltage of the Schottky diode can be less than 1.0 V).

[0031] Further, in accordance with some embodiments of the present application, a JFET region is also embedded, which further reduces the body resistance of the semiconductor device, improves the current capability of both the diode and the MOSFET, and thereby improves the current capability of the overall semiconductor device. It is understood by those skilled in the art that the JFET region is not necessary, and in some embodiments of the semiconductor device, the JFET region is not provided.

[0032] Figures 3A-9C A method of manufacturing a semiconductor device according to a second embodiment of the present application is shown. The shown exemplary method of manufacturing can be used, for example, to manufacture the semiconductor device 100 according to the first embodiment of the present application. The shown exemplary method of manufacturing can be considered as an example of a number of methods of manufacturing the semiconductor device 100 according to the first embodiment of the present application.

[0033] For the sake of brevity, only a few typical steps of the overall process are shown. Furthermore, for the sake of clarity, for each process step shown, a cross-sectional view of the device state under the step is shown in combination with a plan view of the device state under the step. Figure 1 Exemplary is given along AA, BB, CC. For example Figure 3A , 3B , 3C correspond to the same step, showing the cross-sectional device state along AA, BB, CC, respectively, under the step. This applies analogously to Figure 1 . Figures 4A-9C .

[0034] As shown in Figures 3A-3C , a semiconductor substrate 202 is provided and a well region 210 is formed on the substrate 202. The semiconductor substrate 202 is of a first conductivity type. For the sake of convenience, the first conductivity type is exemplified as N-type and the second conductivity type is exemplified as P-type in the following. The substrate 202 can comprise a plurality of epitaxial layers and drift layers as desired, and can have a suitable doping profile and thickness. The substrate 202 comprises a semiconductor material, such as one of SiC, silicon, etc.

[0035] To form the well region 210, a first hard mask can be formed on a first side 202a of the substrate 202. The first hard mask can be formed of a suitable oxide, such as a silane (SiH4) based oxide or a tetraethyl orthosilicate (TEOS) based oxide. The oxide as the first hard mask can be formed by a suitable process, including but not limited to low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), etc. In the present particular embodiment, the first hard mask is formed by deposition of plasma enhanced tetraethyl orthosilicate (PETEOS).

[0036] The first hard mask can then be patterned to obtain a patterned first hard mask 204. In the present particular embodiment, photolithography and dry etching are performed on the first hard mask to expose portions of the first side 202a corresponding to the well region 210 as a window for ion implantation. The P-type well region 210 is formed with the patterned first hard mask 204 as a mask by performing ion implantation, such as aluminum ion implantation at a temperature in the range of 400°C to 600°C.

[0037] Referring to Figures 4A-4CAn oxide layer is formed on the patterned first hard mask 204 and the exposed portion of the first surface 202a (i.e. the window corresponding to the well region 210), and then the oxide layer is patterned to obtain the spacer layer 206, thereby exposing a window on the first surface 202a for forming the source region 220. N-type ion implantation (e.g. ion implantation of one of nitrogen, phosphorus, etc.) is performed using the patterned first hard mask 204 and the spacer layer 206 as a mask to obtain the source region 220.

[0038] In Figures 5A-5C The spacer layer 206 and the patterned first hard mask 204 are removed. In Figures 6A-6C A second hard mask is formed on the first surface 202a. The second hard mask is, for example, an oxide film or layer, which can include TEOS-based oxide such as PETEOS, SiH4-based oxide, etc. The second hard mask is patterned to obtain the patterned second hard mask 208, thereby exposing a window on the first surface 202a corresponding to the contact region 230, and P-type ion implantation (e.g. ion implantation of aluminum) is performed using the window to form the contact region 230. At least a portion of the first surface 202a is protected or shielded by the patterned second hard mask 208, thereby forming the Schottky region 240 extending downward from the portion.

[0039] In Figures 7A-7C The patterned second hard mask 208 is removed. N-type ion implantation is performed using an optical mask to form the JFET region 250. In Figures 8A-8C The dielectric layer 260 and the gate 270 are formed. For example, silicon dioxide can be first formed on a portion of the first surface 202a as a first dielectric layer or gate oxide layer, and then the gate 270 is formed, and then a second dielectric layer is formed on the gate 270 and the portion of the first dielectric layer not covered by the gate 270, thereby protecting and isolating the gate 270.

[0040] In Figures 9A-9C The source metal layer 280 is formed. The source metal layer 280 can include one or more metal layers. For example, one of nickel (Ni), titanium (Ti), platinum (Pt), etc. can be first deposited as a metal layer for Schottky contact and an ohmic contact metal layer, and then high-speed thermal annealing (RTA) is performed, for example, annealing at 500°C for 30 seconds for titanium, and then aluminum with a thickness in the range of 2um to 5um is deposited as a top metal layer after etching the contact hole of the gate to form the source metal layer 280. The source metal layer 280 forms a Schottky diode or Schottky contact 282 with the Schottky region 240, an ohmic contact 284 with the contact region 230, and an ohmic contact 286 with the source region 220.

[0041] According to the above process, without adding a new mask, but only by improving the hard mask window design, the Schottky diode can be embedded into the semiconductor device to improve the device performance. This does not increase the process cost, and the device improvement is achieved. In addition, the process uses a self-alignment method to form the source region, which can save the mask cost and achieve the stability and consistency of the channel.

[0042] The above examples are only for the purpose of illustrating the idea of the present application, and are not a limitation of the present application. For example, Figures 3A-9C The method of the above example is only illustrative, and one or more other method variations can be conceived by those skilled in the art on the basis of the present text, without the need for creative effort.

[0043] In the above examples, the first conductivity type is N-type, and the second conductivity type is P-type. Those skilled in the art will understand that the first conductivity type can also be P-type, and the second conductivity type can also be N-type.

[0044] Those skilled in the art will also understand that, for the purpose of clear illustration, the elements (such as elements, regions, layers, etc.) in the various drawings are not drawn to scale. The various elements in the drawings are also not necessarily in their actual shape. In actual devices, many regions, such as well regions, source regions, contact regions, are usually not regular geometric shapes. For example, the corners are usually rounded, not regular right angles. For example, the spacer layer 206 shown in Figure 4C in the text is usually not a regular, uniform thickness shape. Such processing in the text is only for the purpose of illustrating the idea of the present application, and is also the usual practice in the art, without impairing the clarity of the description.

[0045] The semiconductor device can also have multiple repeating units. For example Figure 1 The semiconductor device 100 shown in the text can include multiple well regions, source regions, Schottky regions, contact regions, JFET regions, etc. For the purpose of clarity, multiple repeating units are not shown. In addition, as described in the text, "semiconductor device" can refer to a repeating unit or cell itself, or to a device composed of several cell cycles arranged in a period.

[0046] Figures 2A-2D The structure diagram shown in the text is a cross-sectional view along a plane perpendicular to Figure 1 the plane shown in the text, and for the purpose of clear display, the gate, dielectric layer and source metal layer are added in Figures 2A-2D , which is only for a clearer display of the device structure relationship on the first surface of the substrate.

[0047] In Figure 2B and 9BIn some embodiments, the depth of the contact region is less than the depth of the well region. This is merely illustrative, in some other embodiments, the depth of the contact region can be equal to, or greater than, the depth of the well region.

[0048] In the above embodiments, reference to ion implantation can be to a single ion implantation, or to multiple ion implantations, for example chain implantations to adjust the impurity profile.

[0049] In the above embodiments, the semiconductor device can comprise a MOSFET, an Insulated Gate Bipolar Transistor (IGBT), or other type of semiconductor device.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The embodiments of this application are illustrated by, but not limited to, the following non-limiting examples. Various modifications enabling a person skilled in the art, based on the disclosed embodiments, fall within the scope of the application.

Claims

1. A semiconductor device having a Schottky diode, characterized by, Comprising: a substrate of a first conductivity type, the substrate having a first side and a second side; a well region of a second conductivity type, the second conductivity type being opposite the first conductivity type, the well region being located in the substrate and extending in a direction from the first side toward the second side; a source region of the first conductivity type, the source region being located in the well region and extending in the direction from the first side toward the second side; a contact region of the second conductivity type, the contact region being located in the substrate and extending in the direction from the first side toward the second side, the contact region being in contact with the well region and the source region; a Schottky region extending in the direction from the first side toward the second side, the Schottky region being a portion of the substrate; and a source metal layer disposed on the first side, a first portion of the source metal layer being in contact with the Schottky region to form a Schottky diode, the Schottky region being surrounded by the well region and the contact region in a first plane perpendicular to the direction from the first side toward the second side; a boundary of the Schottky region is a quadrilateral in the first plane, a first opposite side of the quadrilateral being in contact with the well region, a second opposite side of the quadrilateral being in contact with the contact region; wherein the second opposite side of the quadrilateral is along an x-direction, a source contact width of the source metal layer is equal to a width of the contact region in the first plane along the x-direction. a length of the Schottky region in the x-direction ranges from 0.8um to 2.5um in the first plane.

2. The semiconductor device having a Schottky diode according to claim 1, characterized by a second portion of the source metal layer forms an ohmic contact with the contact region.

3. The semiconductor device having a Schottky diode according to claim 1, characterized by a third portion of the source metal layer forms an ohmic contact with the source region.

4. The semiconductor device having a Schottky diode according to claim 1, characterized by a depth of the well region ranges from 0.6um to 1.8um in the direction from the first side toward the second side, a depth of the contact region ranges from 0.4um to 1.8um in the direction from the first side toward the second side.

5. The semiconductor device having a Schottky diode according to claim 1, characterized by Further comprising:

6. The semiconductor device having a Schottky diode according to claim 1, characterized by a gate disposed on the first side; and a JFET region disposed under at least a portion of the gate, the JFET region being located in the substrate and extending in the direction from the first side toward the second side. the JFET region separates adjacent well regions in at least one direction of the first plane. the first conductivity type is N-type, and the second conductivity type is P-type.

7. The semiconductor device having a Schottky diode according to claim 6, characterized by the substrate comprises one of silicon and silicon carbide.

8. The semiconductor device having a Schottky diode according to claim 1, characterized by Comprising:

9. The semiconductor device having a Schottky diode according to claim 1, characterized by a substrate of a first conductivity type, the substrate having a first side and a second side; 10. A semiconductor device having a Schottky diode, characterized by a plurality of well regions of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type; a plurality of source regions, each source region disposed in a corresponding well region; a plurality of contact regions of the second conductivity type, each contact region in contact with an adjacent well region and source region, the contact region having a higher impurity concentration than the well region; and a plurality of Schottky regions, each Schottky region surrounded by a well region and a contact region in a first plane perpendicular to a direction from the first side toward the second side. the Schottky region is a quadrilateral in the first plane, a first opposite side of the quadrilateral being in contact with the well region, a second opposite side of the quadrilateral being in contact with the contact region; wherein the second opposite side of the quadrilateral is along an x-direction, a source contact width of the source metal layer is equal to a width of the contact region in the first plane along the x-direction. a length of the Schottky region in the x-direction ranges from 0.8um to 2.5um in the first plane. a second portion of the source metal layer forms an ohmic contact with the contact region. a third portion of the source metal layer forms an ohmic contact with the source region. a depth of the well region ranges from 0.6um to 1.8um in the direction from the first side toward the second side, a depth of the contact region ranges from 0.4um to 1.8um in the direction from the first side toward the second side. Further comprising: a gate disposed on the first side; and a JFET region disposed under at least a portion of the gate, the JFET region being located in the substrate and extending in the direction from the first side toward the second side. the JFET region separates adjacent well regions in at least one direction of the first plane. the first conductivity type is N-type, and the second conductivity type is P-type. the substrate comprises one of silicon and silicon carbide. a source metal layer disposed on the first face, the source metal layer in contact with the plurality of Schottky regions forming Schottky diodes, the source metal layer in contact with the plurality of contact regions and the plurality of source regions forming ohmic contacts; a source contact width of the source metal layer equal to a width of the contact regions in the first face along the x-direction.

11. The semiconductor device having a Schottky diode according to claim 10, characterized by a length of each of the plurality of Schottky regions in a first direction of the first plane ranges from 0.8um to 2.5um.

12. The semiconductor device having a Schottky diode according to claim 10, characterized by further comprising: a plurality of JFET regions, each of the JFET regions disposed between adjacent well regions in at least one direction of the first plane.

13. A method of manufacturing a semiconductor device having a Schottky diode, characterized by, comprising: providing a substrate of a first conductivity type, the substrate having a first face and a second face; forming well regions of a second conductivity type in the substrate; forming source regions of the first conductivity type in the well regions; simultaneously forming Schottky regions of the first conductivity type and contact regions of the second conductivity type in the substrate such that the contact regions are in contact with the well regions and the source regions, and such that in a first plane perpendicular to a direction from the first face towards the second face, the Schottky regions are surrounded by the well regions and the contact regions; and forming a source metal layer on the first face such that the source metal layer forms Schottky diodes with the Schottky regions and ohmic contacts with the source regions and the contact regions; wherein a source contact width of the source metal layer is equal to a width of the contact regions in the first face along the x-direction.

14. The method of claim 13, wherein, the step of forming the well regions comprises: forming a first hardmask on the first face; patterning the first hardmask to obtain a patterned first hardmask; and performing ion implantation of the second conductivity type with the patterned first hardmask as a mask to form the well regions.

15. The method of claim 14, wherein, the step of forming the source regions comprises: forming an oxide layer on the patterned first hardmask and exposed portions of the first face; patterning the oxide layer to obtain a spacer layer; and performing ion implantation of the first conductivity type with the patterned first hardmask and the spacer layer as a mask to obtain the source regions.

16. The method of claim 15, wherein, the step of forming the contact regions and the Schottky regions comprises: removing the spacer layer and the patterned first hardmask; forming a second hardmask on the first face; patterning the second hardmask to obtain a patterned second hardmask; and performing ion implantation of the second conductivity type with the patterned second hardmask as a mask to form the contact regions, and such that at least a portion of the first face protected by the patterned second hardmask forms the Schottky regions.

17. The method of claim 16, wherein, further comprising: removing the patterned second hardmask; performing ion implantation of the first conductivity type with an optical mask to form JFET regions.

18. The method according to any one of claims 13 to 17, characterized in that, further comprising, prior to forming the source metal layer: forming a first dielectric layer on a portion of the first face; forming a gate on a portion of the first dielectric layer; and forming a second dielectric layer on another portion of the first dielectric layer and the gate.

Images