Stacked structure for selective contact, cell front structure and method of manufacture

Abstract

This invention provides a stacked structure for selective contact, a front-side battery structure, and a fabrication method. The stacked structure includes a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate. A second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front-side metal electrode. This stacked structure solves the problem of difficult-to-control etching process by adding an etch-resistant layer, thereby enabling a fabrication process that allows for the full deposition of polysilicon thin films, the formation of locally patterned protective regions, and the etching away of the remaining unpatterned polysilicon thin films. This allows for the application of an ultrathin silicon oxide / heavily doped polysilicon structure to the front side of the battery, passivating the contact between the metal electrode and the silicon substrate, avoiding the existence of high recombination regions, reducing carrier recombination, and maintaining carrier collection efficiency, ultimately improving the battery's open-circuit voltage, fill factor, and conversion efficiency.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a stacked structure for selective contact, a front-side structure of the cell, and a method for its fabrication. Background Technology

[0002] In 2014, the Fraunhofer Institute in Germany first proposed the tunneling silicon oxide passivated contact structure (TOPCon) to improve the passivation of the back side of crystalline silicon solar cells and enhance cell performance. This structure uses an n-type silicon wafer, on which nano-SiO₂ is fabricated. x As a tunneling layer, subsequently in SiO x A layer of heavily doped polycrystalline silicon is deposited on the top using methods such as PECVD, and finally, a full-area metal electrode is fabricated on the back. Because polycrystalline silicon exhibits strong parasitic light absorption in the short wavelength range, this structure is mainly used on the back of the cell. The front design of the high-efficiency crystalline silicon solar cell fabricated using a tunnel oxide passivation contact structure is similar to that of a traditional PERC cell, employing AlO4 on top of the pn junction. x / SiN x Stacked metal electrodes, serving as passivation and antireflection layers, are fabricated using methods such as screen printing and sintering. During the sintering process, the metal electrodes on the front of the solar cell penetrate the surface AlO₂. x / SiN x The stacked electrodes form direct contact with the single-crystal silicon substrate. On one hand, due to the large number of free electrons in the metal, the metal electrode contact area causes severe recombination between free electrons in the metal and holes in the semiconductor at the substrate surface, resulting in a saturation current density in the metal electrode contact area as high as 1000-2000 fA / cm². 2 This greatly affects battery efficiency; on the other hand, metal atoms may diffuse into the single-crystal silicon substrate under high temperature, causing severe recombination of charge carriers in the bulk, making it difficult to improve battery efficiency.

[0003] Selective emitter (SEPA) is a diffusion technique that heavily dops the metal electrode region and lightly dops the non-metal region. This technique heavily dops the area where the emitter contacts the metal electrode, and lightly dops other areas. The heavy doping in the metal-contact region reduces the sheet resistance, thus decreasing the contact resistance with the metal electrode. The high sheet resistance in other areas reduces recombination of incident light in the lightly doped regions. Simultaneously, the low sheet resistance of the heavily doped region and the high sheet resistance of the lightly doped region form a high-low junction, which acts as a field passivation. Currently, commercially available SEPA structures commonly employ laser propulsion technology, which uses a laser to ablate phosphosilicate glass or borosilicate glass, creating localized heavy doping during the ablation process. First, a layer of phosphosilicate glass (PSG) or borosilicate glass (BSG) is grown on a substrate. Then, a laser is used to scan and propel the diffused surface to form a laser-doped selective emitter. Finally, the surface phosphosilicate glass is removed by chemical cleaning. However, the high-energy laser during laser propulsion can cause severe ablation damage to the structural surface, generating many defects and recombination centers. This results in a still relatively large recombination current, with the saturation current density in the metal contact area potentially reaching 1000 fA / cm². 2 This significantly reduces the ideal effect of selective emitter structures.

[0004] To date, there is no suitable technical solution for the selective emitter of solar cells based on an ultrathin silicon oxide / heavily doped polycrystalline silicon structure. The challenges are as follows: Due to severe parasitic absorption in heavily doped polycrystalline silicon, significant parasitic absorption will occur if the polycrystalline silicon film thickness is increased to more than 20 nm. However, in order to block the penetration of metal paste, the polycrystalline silicon thickness usually needs to reach more than 100 nm. Therefore, it is not feasible to prepare a complete polycrystalline silicon film. Instead, patterned polycrystalline silicon film preparation is required, while removing polycrystalline silicon films in other areas by etching. However, existing technologies are difficult to achieve selective etching of polycrystalline silicon films. This is because alkaline solutions are usually used to etch polycrystalline silicon films, but due to fluctuations in polycrystalline silicon film thickness and batch-to-batch quality of chemicals, it is difficult to achieve highly consistent polycrystalline silicon film etching every time. If not handled properly, it is easy to cause over-etching or under-etching, thereby reducing product yield. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to propose a polycrystalline silicon thin film with a novel structure to solve the problem of difficult-to-control etching process, thereby realizing a selective contact structure based on an ultrathin silicon oxide / heavily doped polycrystalline silicon structure to reduce recombination losses in the metal electrode contact area.

[0006] To achieve the aforementioned objective, the first aspect of the present invention provides a stacked structure for selective contact, comprising a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate, wherein a second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front metal electrode.

[0007] Furthermore, the material of the anti-etching layer is silicon oxide or silicide resistant to alkali etching, and the thickness of the anti-etching layer is 1-10 nm.

[0008] Furthermore, the anti-etching layer is also doped with any one or more of oxygen, nitrogen, and carbon.

[0009] Furthermore, the dielectric layer is made of silicon oxide, and the thickness of the dielectric layer is less than or equal to 3 nm.

[0010] Furthermore, the material of the first heavily doped polycrystalline silicon layer is polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicide, and the thickness of the first heavily doped polycrystalline silicon layer is 2-20 nm.

[0011] Furthermore, the material of the second heavily doped polycrystalline silicon layer is polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicide, and the thickness of the second heavily doped polycrystalline silicon layer is 30-300 nm.

[0012] Furthermore, the substrate is n-type crystalline silicon or p-type crystalline silicon.

[0013] Furthermore, the p-type doped atoms in the first and second heavily doped polysilicon layers include boron, and the concentration of the doped atoms is 1E18-5E20 cm⁻¹. -3 Alternatively, the p-type doped atoms in the first and second heavily doped polysilicon layers may include boron, phosphorus, arsenic, or antimony, and the concentration of the doped atoms may be 1E19-1E21 cm⁻¹. -3 .

[0014] Compared with the prior art, the stacked structure of the present invention has the following advantages:

[0015] The dielectric layer and the first heavily doped polysilicon layer are essential for the ultrathin silicon oxide / heavily doped polysilicon structure, used to achieve surface passivation and selective carrier collection. The first heavily doped polysilicon layer is relatively thin, used to provide field passivation effect and carrier collection, while reducing parasitic absorption by reducing thickness. The anti-etching layer is used to block or slow down alkaline etching, thereby protecting the first heavily doped polysilicon layer and the silicon wafer surface. The second heavily doped polysilicon layer is relatively thick, mainly used to block the penetration of metal paste and protect the underlying material.

[0016] This stacked structure primarily addresses the challenge of controlling the etching process by adding an etch-resistant layer. The principle is as follows: alkaline solutions exhibit strong etching selectivity for polysilicon and silicon oxide films; that is, the etching rate for polysilicon is very high, while the etching rate for alkali-resistant silicon oxide or silicides is extremely low. This allows the etching process to be largely halted once the etch-resistant layer is reached, thus protecting the area below the etch-resistant layer. Of course, the integrity of the etch-resistant layer is inevitably compromised during heat treatment, resulting in some etching below the etch-resistant layer. However, the presence of a dielectric layer still blocks alkaline etching, effectively protecting the pn junction region. This allows for a fabrication process that fully deposits polysilicon films, forms locally patterned protected areas, and etches away the remaining non-patterned polysilicon films.

[0017] A second aspect of the present invention provides a front-side structure for a battery, including a substrate, wherein the front side of the substrate is provided with the aforementioned stacked structure facing selective contact, and a front-side metal electrode is bonded to a second heavily doped polysilicon layer of the stacked structure.

[0018] A third aspect of the present invention provides a method for preparing a front-side structure of a battery, comprising the following steps:

[0019] S1. Prepare a dielectric layer on the front side of the substrate;

[0020] S2. Prepare a first silicide layer on the dielectric layer;

[0021] S3. Prepare an anti-etching layer on the first silicide layer;

[0022] S4. Prepare a second silicide layer on the etch-resistant layer;

[0023] S5. High-temperature annealing treatment crystallizes the silicide layer and activates the doped atoms;

[0024] S6. Apply an alkali-resistant material to the area where the electrode needs to be prepared to form a protective layer;

[0025] S7. Etching: Use a strong alkaline solution to etch away the heavily doped second silicide layer in the unprotected area;

[0026] S8. Clean and remove the protective layer;

[0027] S9. Deposit an antireflection layer on the etched silicon wafer surface;

[0028] S10. A front metal electrode is prepared on the remaining second silicide layer. After sintering and annealing, the front metal electrode and the second silicide layer form good contact and a selective emitter is formed.

[0029] The battery front structure and preparation method of the present invention have the following beneficial effects:

[0030] Applying an ultrathin silicon oxide / heavily doped polycrystalline silicon structure to the front of the battery can passivate the contact between the metal electrode and the silicon substrate, avoid the existence of high recombination regions, reduce carrier recombination, and selective etching avoids the effects of parasitic light absorption in thicker polycrystalline silicon; maintain carrier collection efficiency, thereby improving the open-circuit voltage, fill factor and conversion efficiency of the battery.

[0031] The region where the ultrathin silicon oxide / heavily doped polysilicon structure contacts the metal is heavily doped, which reduces the sheet resistance of the region and reduces the contact resistance with the metal electrode to a certain extent. Other regions are etched away to form a high sheet resistance, which reduces the recombination of incident light in the lightly doped region, thereby further reducing front recombination.

[0032] After using a surface alkali-resistant coating for protection combined with wet chemical etching, the process steps are simple and a selective emitter is formed. During etching, the double-layer ultrathin silicon oxide / heavily doped polysilicon structure can effectively avoid damage caused by excessive etching, and maintain a low contact resistivity while reducing carrier recombination damage in the metal electrode contact area.

[0033] This avoids the use of expensive dry etching equipment and methods such as laser etching, both of which would cause additional surface damage, thus improving product yield. Attached Figure Description

[0034] Figure 1 This is a flowchart illustrating the fabrication process of the front structure of the battery in an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram of the structure of a solar cell in an embodiment of the present invention.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1-Substrate, 2-Diffusion layer, 3-Dielectric layer, 4-First doped polysilicon layer, 5-Etching resistance layer, 6-Second doped polysilicon layer, 7-Antireflection layer, 8-Front metal electrode, 9-Protective layer, 10-Back silicon oxide layer, 11-Back doped polysilicon layer, 12-Back metal electrode. Detailed Implementation

[0038] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of the present invention, and are not intended to limit the parameter range described in the present invention. Reasonable variations derived therefrom are still within the protection scope of the claims of the present invention.

[0039] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0040] Embodiments of the present invention provide a stacked structure for selective contact, comprising a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate. A second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front metal electrode. The dielectric layer and the first heavily doped polysilicon layer are essential for the ultrathin silicon oxide / heavily doped polysilicon structure, used to achieve surface passivation and selective carrier collection. The first heavily doped polysilicon layer provides field passivation and carrier collection. The etch-resistant layer blocks or slows down alkaline etching, protecting the first heavily doped polysilicon layer and the silicon wafer surface. The second heavily doped polysilicon layer forms good contact with the metal electrode.

[0041] Furthermore, the thickness of the stacked structure is limited, with the dielectric layer thickness less than or equal to 3 nm to reduce parasitic absorption; the thickness of the first doped polysilicon layer is 2-20 nm; the thickness of the anti-etching layer is 1-10 nm, which can prevent alkaline etching and protect the first doped polysilicon layer and the silicon wafer surface; the thickness of the second doped polysilicon layer is 30-300 nm, which can block the penetration of metal paste and protect the underlying material.

[0042] In some embodiments, the silicon substrate is n-type crystalline silicon, and the p-type dopant atoms contained in the doped polycrystalline silicon layer include, but are not limited to, boron, with a dopant concentration of 1E18-5E20 cm⁻¹. -3 .

[0043] In some embodiments, the silicon substrate is p-type crystalline silicon, and the n-type dopant atoms contained in the doped polycrystalline silicon layer include, but are not limited to, phosphorus, arsenic, and antimony, with a dopant concentration of 1E19-1E21 cm⁻¹. -3 .

[0044] In some embodiments, the dielectric layer is made of silicon oxide; the first and second doped polycrystalline silicon layers are made of polycrystalline silicon, doped polycrystalline silicon, or polycrystalline silicides, such as carbon-doped polycrystalline silicon, polycrystalline silicon carbide, nitrogen-doped polycrystalline silicon, polycrystalline silicon nitride, oxygen-doped polycrystalline silicon, polycrystalline silicon oxide, etc.; the etching-resistant layer is made of alkaline-resistant silicon oxide or silicides, and its microstructure can be amorphous, microcrystalline, or nanocrystalline. During annealing, defects may also be generated in the etching-resistant layer, thereby forming conductive channels without affecting the transport of charge carriers.

[0045] Furthermore, the etch-resistant layer is doped with one or more of oxygen, nitrogen, and carbon. This doping modification of the etch-resistant layer results in superior conductivity without significantly affecting carrier transport.

[0046] Embodiments of the present invention also provide a battery front structure and a method for fabricating the same. The battery front structure includes a substrate, and the front side of the substrate is provided with the above-mentioned stacked structure facing selective contact. A front metal electrode is bonded to the second heavily doped polycrystalline silicon layer of the stacked structure.

[0047] Combination Figure 1 As shown, the method for fabricating the front structure of the battery includes the following steps:

[0048] S0. Low-concentration diffusion is performed on silicon substrate 1 to form diffusion layer 2, and a lightly doped pn junction is prepared.

[0049] S1. Prepare a dielectric layer 3 with a thickness of less than or equal to 3 nm on the front diffusion layer 2 of substrate 1;

[0050] S2. Prepare a first silicide layer with a thickness of 2-20 nm on the dielectric layer 3;

[0051] S3. Prepare an etch-resistant layer 5 with a thickness of 1-10 nm on the first silicide layer;

[0052] S4. Prepare a second silicide layer with a thickness of 30-300 nm on the anti-etching layer 5;

[0053] S5. High-temperature annealing treatment, with a treatment temperature of 800-1000℃ and a time of 10-90min, to crystallize the silicide layer film and activate the doped atoms;

[0054] S6. Apply an alkali-resistant material to the area where the electrode needs to be prepared to form a protective layer 9;

[0055] S7. Etching: Use a strong alkaline solution to etch away the heavily doped second silicide layer in the unprotected area. The etching can stop at the anti-etching layer 5 without further damaging the silicon substrate 1.

[0056] S8. Clean and remove the protective layer; 9.

[0057] S9. Deposit an antireflection layer 7 on the etched silicon wafer surface;

[0058] S10. A front metal electrode 8 is prepared on the remaining second silicide layer. After sintering and annealing, the front metal electrode 8 forms good contact with the second silicide layer and forms a selective emitter.

[0059] In some embodiments, the preparation methods of the dielectric layer and the etch-resistant layer can be selected from any of the following: wet chemical oxidation, high-temperature oxidation, ozone oxidation, plasma-assisted oxidation, plasma-assisted atomic layer deposition, plasma reactive deposition, etc.

[0060] In some embodiments, the preparation of the first and second doped polysilicon layers preferably employs plasma-enhanced chemical vapor deposition (PECVD) combined with in-situ doping. Alternatively, low-pressure chemical vapor deposition (LPCVD) combined with in-situ / secondary doping, or other physical vapor deposition (PVD) methods such as magnetron sputtering combined with in-situ / secondary doping can be used to prepare the thin film precursor.

[0061] Combination Figure 2 As shown, this is a crystalline silicon solar cell with the aforementioned front-side structure, comprising a substrate 1. The front side of the substrate 1 has a diffusion layer 2, on which a dielectric layer 3, a first heavily doped polycrystalline silicon layer 4, and an etch-resistant layer 5 are sequentially stacked. A second heavily doped polycrystalline silicon layer 6 is disposed in a portion of the etch-resistant layer 5, and a front-side metal electrode 8 is bonded to the second heavily doped polycrystalline silicon layer 6. An anti-reflection layer 7 is disposed in other areas. On the back side of the substrate 1, a back-side silicon oxide layer 10, a back-side doped polycrystalline silicon layer 11, and a back-side metal electrode 12 are sequentially stacked. This crystalline silicon solar cell has an ultra-thin silicon oxide / heavily doped polycrystalline silicon structure on both the front and back sides, eliminating contact between the metal electrode and the crystalline silicon substrate 1, while simultaneously forming a pn junction and a selective emitter.

[0062] The present invention will be described in detail below through specific embodiments.

[0063] Example 1

[0064] A method for fabricating an N-type crystalline silicon solar cell includes the following steps: texturing an N-type silicon wafer using conventional methods, performing low-concentration boron diffusion to control the sheet resistance to 125-135 Ω / sq; removing BSG and polishing the back side; fabricating a first ultrathin silicon oxide layer with a thickness of 1.5 nm on both sides of the silicon wafer using PECVD in-situ oxidation; then fabricating a first boron-doped amorphous silicon layer with a thickness of 15 nm on both sides using PECVD; fabricating a second silicon oxide layer with a thickness of 3 nm on the front side; and then simultaneously fabricating boron-doped amorphous silicon with a thickness of 70 nm on both sides; and proceeding further... Annealing at 880℃ for 30 minutes forms polycrystalline silicon. Using screen printing, an alkali-resistant protective layer slightly wider than the actual width of the metal electrode is prepared on the front side to protect the area where the metal electrode will be prepared. The entire back side is protected with an alkali-resistant protective layer. Then, KOH solution is used to selectively etch the unprotected amorphous silicon area. After etching, the protective layer is removed by cleaning. An 80nm thick SiNx layer is deposited on the surface using PECVD for repassivation and antireflection. Then, metal electrodes are printed on the polycrystalline silicon on the front side and the back side, and the metal electrodes are sintered to form good contact.

[0065] Comparative Example 1

[0066] A method for preparing an N-type crystalline silicon solar cell includes the following steps: texturing an N-type silicon wafer using conventional methods, diffusion of low-concentration boron, and controlling the sheet resistance to be 125-135 Ω / sq; removing BSG and polishing the back side; preparing an ultrathin silicon oxide layer with a thickness of 1.5 nm on the back side; then preparing 75 nm boron-doped amorphous silicon on the back side using PECVD, passivating and antireflection treatment of the surface using 80 nm silicon nitride, printing metal electrodes with the same pattern as in Example 1 on the polycrystalline silicon front side and the back side, and sintering the metal electrodes.

[0067] Performance tests were conducted on two groups of samples prepared in Example 1 and Comparative Example 1. The tests included: overall passivation effect (J). 0,total ), passivation effect of metal contact region containing polycrystalline silicon-oxygen selective emitter (J) 0,met and contact resistivity (ρ) c,met Shear resistance (R) of the metal contact area sq ) and passivation effect (J 0,pass The test results are shown in Table 1 below.

[0068] Table 1. Performance test results of the samples from Example 1 and Comparative Example 1

[0069]

[0070] The data from Example 1 and Comparative Example 1 show that Example 1 uses a stacked selective emitter structure, which reduces the sheet resistance of the electrode contact area to 80-90 Ω / sq, ensuring contact between the electrode and the battery, significantly reducing the recombination current density (J0,met) in the metal electrode area, thereby reducing the overall recombination current density (J0,total), reducing recombination, and improving battery efficiency.

[0071] Example 2

[0072] A method for fabricating N-type crystalline silicon solar cells includes the following steps: texturing an N-type silicon wafer using conventional methods, followed by low-concentration boron diffusion to control the sheet resistance to 130-140 Ω / sq; removing BSG and polishing the back side; fabricating a first ultrathin silicon oxide layer with a thickness of 1.6 nm on both the front and back sides of the silicon wafer using PECVD in-situ oxidation; then fabricating a first boron-doped amorphous silicon layer with a thickness of 18 nm on the front side using PECVD; and again fabricating a second silicon oxide layer with a thickness of 8 nm on the front side using the same method. Simultaneously, a 100 nm thick silicon oxide layer is fabricated on both the front and back sides. Boron-doped amorphous silicon was annealed at 890°C for 30 minutes to form polycrystalline silicon. An alkali-resistant protective layer, slightly wider than the actual width of the metal electrode, was prepared on the front side using screen printing technology to protect the area where the metal electrode would be fabricated. The entire back side was protected with an alkali-resistant protective layer. Subsequently, the unprotected amorphous silicon areas were selectively etched using KOH solution. After etching, the protective layer was cleaned and removed. The next step involved depositing a 75nm thick SiNx layer on the front side using PECVD for re-passivation and anti-reflection. Metal electrodes were then printed on the polycrystalline silicon on the front side and the back side, followed by sintering.

[0073] Comparative Example 2

[0074] A method for preparing an N-type crystalline silicon solar cell includes the following steps: texturing an N-type silicon wafer using conventional methods, performing low-concentration boron diffusion, and controlling the sheet resistance to be 100-110 Ω / sq; removing BSG and polishing the back side; preparing an ultrathin silicon oxide layer on the back side of the silicon wafer using PECVD in-situ oxidation, and depositing a 115 nm phosphorus-doped amorphous silicon thin film on the back side; annealing at 890 °C for 30 min to form polycrystalline silicon; passivating and antireflection treatment of the front surface of the cell using 75 nm silicon nitride; printing metal electrodes with the same pattern as in Example 2 on the front polycrystalline silicon and the back side, and sintering the metal electrodes.

[0075] Electrical performance tests were conducted on the two groups of samples prepared in Example 2 and Comparative Example 2. The tests included: open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and battery conversion efficiency (Eff). The test results are shown in Table 2 below.

[0076] Table 2. Electrical performance test results of samples from Example 2 and Comparative Example 2.

[0077]

[0078]

[0079] The data comparison shows that, compared with the crystalline silicon cell of Comparative Example 2, the cell in Example 2 adopts a selective emitter structure, which improves the open-circuit voltage (Voc) and short-circuit current density (Jsc). At the same time, due to the good contact of the electrode contact area, the high fill factor (FF) of the cell is also guaranteed. Therefore, the cell conversion efficiency (Eff) is significantly improved.

[0080] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A laminated structure oriented towards selective contact, characterized in that, The device comprises a dielectric layer, a first heavily doped polysilicon layer, and an etch-resistant layer sequentially stacked on the front side of a substrate. A second heavily doped polysilicon layer is disposed on the etch-resistant layer in the region corresponding to the front metal electrode. The thickness of the first heavily doped polysilicon layer is 2-20 nm, and the thickness of the second heavily doped polysilicon layer is 30-300 nm. The etch-resistant layer is made of alkaline-resistant silicon oxide or silicide, and its thickness is 1-10 nm. The etch-resistant layer is also doped with any one or more of oxygen, nitrogen, and carbon. The dielectric layer is made of silicon oxide, and its thickness is less than or equal to 3 nm.

2. The laminated structure oriented towards selective contact according to claim 1, characterized in that, The substrate is either n-type crystalline silicon or p-type crystalline silicon.

3. The laminated structure oriented towards selective contact according to claim 2, characterized in that, The p-type doped atoms in the first and second heavily doped polysilicon layers include boron, and the concentration of the doped atoms is 1E18-5E20 cm⁻¹. -3 Alternatively, the n-type doped atoms in the first and second heavily doped polysilicon layers include boron, phosphorus, arsenic, or antimony, and the concentration of the doped atoms is 1E19-1E21 cm⁻¹. -3 .

4. A battery front structure, characterized in that, The substrate includes a front side having a stacked structure for selective contact as described in any one of claims 1-3, wherein a front metal electrode is bonded to a second heavily doped polysilicon layer of the stacked structure.

5. A method for preparing the front structure of a battery as described in claim 4, characterized in that, Includes the following steps: S1. Prepare a dielectric layer on the front side of the substrate; S2. Prepare a first silicide layer on the dielectric layer; S3. Prepare an anti-etching layer on the first silicide layer; S4. Prepare a second silicide layer on the etch-resistant layer; S5. High-temperature annealing treatment crystallizes the silicide layer and activates the doped atoms; S6. Apply an alkali-resistant material to the area where the electrode needs to be prepared to form a protective layer; S7. Etching: Use a strong alkaline solution to etch away the heavily doped second silicide layer in the unprotected area; S8. Clean and remove the protective layer; S9. Deposit an antireflection layer on the etched silicon wafer surface; S10. A front metal electrode is prepared on the remaining second silicide layer. After sintering and annealing, the front metal electrode and the second silicide layer form good contact and a selective emitter is formed.

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