Semiconductor device

Abstract

A semiconductor device includes a substrate, a first magnetic tunnel junction structure, a second magnetic tunnel junction structure, and an interconnect structure. The first magnetic tunnel junction structure, the second magnetic tunnel junction structure, and the interconnect structure are disposed on the substrate. The interconnect structure is between the first magnetic tunnel junction structure and the second magnetic tunnel junction structure in a first horizontal direction, and the interconnect structure includes a first metal interconnect and a second metal interconnect. The second metal interconnect is disposed on and contacts the first metal interconnect. A material composition of the second metal interconnect is different than a material composition of the first metal interconnect.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a semiconductor device having a magnetic tunnel junction (MTJ) structure. Background Technology

[0002] Data storage devices used in electronic products are basically of two types: non-volatile and volatile. Magnetic random access memory (MRAM) is a type of non-volatile memory technology. Unlike current standard memory devices, MRAM uses magnetism to store data instead of using electric charge. Typically, an MRAM cell consists of a data layer and a reference layer. The data layer is made of a magnetic material, and its magnetization can be switched between two opposing states by an applied magnetic field, thereby storing binary information. The reference layer can be made of a magnetic material, and its magnetization can be locked so that the magnetic field applied to the data layer and partially penetrating the reference layer is insufficient to switch the magnetization in the reference layer. During a read operation, the resistance of the MRAM cell differs when the magnetization directions of the data layer and the reference layer are the same or different, thus allowing the identification of the magnetic polarity of the data layer.

[0003] The distance between adjacent MRAM cells decreases as the storage cell density increases, and excessively close MRAM cell setups can cause problems in the manufacturing process and / or structure, requiring improvement through design adjustments. Summary of the Invention

[0004] The present invention provides a semiconductor device that utilizes a first metal interconnect and a second metal interconnect formed on the first metal interconnect to form an interconnect structure between two magnetic tunneling junction structures, thereby improving problems such as short circuits between the interconnect structure and the magnetic tunneling junction structure caused by the close proximity of the magnetic tunneling junction structures.

[0005] An embodiment of the present invention provides a semiconductor device including a substrate, a first magnetic tunneling junction (MTJ) structure, a second magnetic tunneling junction structure, and an interconnect structure. The first magnetic tunneling junction structure, the second magnetic tunneling junction structure, and the interconnect structure are disposed on the substrate, and the interconnect structure is located between the first magnetic tunneling junction structure and the second magnetic tunneling junction structure in a first horizontal direction. The interconnect structure includes a first metal interconnect and a second metal interconnect. The second metal interconnect is disposed on and in contact with the first metal interconnect. The material composition of the second metal interconnect is different from that of the first metal interconnect.

[0006] Another embodiment of the present invention provides a semiconductor device including a substrate, a first magnetic tunneling junction (MTJ) structure, a second magnetic tunneling junction structure, an interconnect structure, a third metal interconnect, and a fourth metal interconnect. The first magnetic tunneling junction structure, the second magnetic tunneling junction structure, and the interconnect structure are disposed on the substrate, and the interconnect structure is located between the first and second magnetic tunneling junction structures in a first horizontal direction. The interconnect structure includes a first metal interconnect and a second metal interconnect. The second metal interconnect is disposed on and contacts the first metal interconnect. The third metal interconnect is disposed on and contacts the first magnetic tunneling junction structure. The fourth metal interconnect is disposed on and contacts the second magnetic tunneling junction structure. The second metal interconnect extends along the first horizontal direction, and the third and fourth metal interconnects each extend along a second horizontal direction. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0008] Figure 2 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0009] Figures 3 to 6 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein...

[0010] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0011] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0012] Figure 6 for Figure 5 A diagram illustrating the subsequent situation.

[0013] Explanation of main component symbols

[0014] 10 base

[0015] 11 Dielectric layer

[0016] 21 Dielectric layer

[0017] 22 Metal interconnects

[0018] 23 Stop Layer

[0019] 30 First intermetallic dielectric layer

[0020] 40 Metal interconnects

[0021] 40A Fifth Metal Interconnect

[0022] 40B Sixth Metal Interconnect

[0023] 40C First Metal Interconnect

[0024] 41 Barrier Layer

[0025] 42 Metal Layer

[0026] 50 Magnetic tunnel junction structure

[0027] 50A First Magnetic Tunneling Structure

[0028] 50B Second Magnetic Tunneling Structure

[0029] 51 First Electrode

[0030] 52 Locked Layer

[0031] 53 First Barrier Layer

[0032] 54 Free Layer

[0033] 55 Second Barrier Layer

[0034] 56 Second electrode

[0035] 61 Cap layer

[0036] 62 Second intermetallic dielectric layer

[0037] 63 Ultra-low dielectric constant dielectric layer

[0038] 70 Metal interconnects

[0039] 70A Third Metal Interconnect

[0040] 70B Fourth Metal Interconnect

[0041] 72 Second Metal Interconnect

[0042] 74 Metal interconnects

[0043] 74A Contact Hole Conductor

[0044] 74B trench conductor

[0045] 100 Semiconductor Devices

[0046] BS bottom surface

[0047] BS1 bottom surface

[0048] BS2 bottom surface

[0049] BS3 bottom surface

[0050] CS interconnect structure

[0051] D1 First Direction

[0052] D2 Second Direction

[0053] D3 third direction

[0054] OP opening

[0055] R1 First District

[0056] R2 Second District

[0057] R3 Third District

[0058] TS upper surface

[0059] TS1 upper surface

[0060] TS2 upper surface

[0061] TS3 upper surface

[0062] W1 width

[0063] W2 width

[0064] WL character line Detailed Implementation

[0065] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0066] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0067] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0068] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0069] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term to include etching.

[0070] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0071] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 includes a substrate 10, a first magnetic tunneling junction (MTJ) structure 50A, a second magnetic tunneling junction structure 50B, and an interconnect structure CS. The first magnetic tunneling junction structure 50A, the second magnetic tunneling junction structure 50B, and the interconnect structure CS are disposed on the substrate 10, and the interconnect structure CS is in a first horizontal direction (e.g., Figure 1The first direction (D1) shown is located between the first magnetic tunneling junction structure 50A and the second magnetic tunneling junction structure 50B. The interconnect structure CS includes a first metal interconnection 40C and a second metal interconnection 72. The second metal interconnection 72 is disposed on and in contact with the first metal interconnection 40C. The material composition of the second metal interconnection 72 is different from that of the first metal interconnection 40C. By using the first metal interconnection 40C and the second metal interconnection 72 on the first metal interconnection 40C to form the interconnect structure CS between the two magnetic tunneling junction structures, the related manufacturing process problems that may be caused when the interconnect structure between the two magnetic tunneling junction structures is a single metal interconnection can be improved. For example, the problem of electrical short circuit between the interconnect structure and the metal interconnection corresponding to the magnetic tunneling junction structure can be caused, thus improving the manufacturing yield.

[0072] In some embodiments, the substrate 10 may be in its thickness direction (e.g. Figure 1 The third direction D3 shown has an upper surface TS and a bottom surface B opposite to each other. The first magnetic tunneling junction structure 50A, the second magnetic tunneling junction structure 50B, and the interconnection structure CS described above can be disposed on one side of the upper surface TS, but are not limited thereto. A horizontal direction substantially orthogonal to the third direction D3 (e.g., the first direction D1 and...) Figure 1 The second direction (D2) shown may be generally parallel to the upper surface TS and / or the bottom surface BS of the substrate 10, but is not limited thereto. Furthermore, the distance in the third direction (D3) between a component at a relatively high position in the vertical direction (e.g., the third direction D3) and / or between a component and the bottom surface BS of the substrate 10 may be greater in the third direction (D3) than the distance in the third direction (D3) between a component at a relatively low position in the third direction (D3) and / or between a component and the bottom surface BS of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface BS of the substrate 10 in the third direction (D3) than the upper part or top of that component. Another component above a component may be considered relatively far from the bottom surface BS of the substrate 10 in the third direction (D3), and another component below a component may be considered relatively close to the bottom surface BS of the substrate 10 in the third direction (D3), but is not limited thereto.

[0073] Further, in some embodiments, the semiconductor device 100 may also include a third metal interconnect 70A, a fourth metal interconnect 70B, a fifth metal interconnect 40A, and a sixth metal interconnect 40B. The third metal interconnect 70A is disposed on and in contact with the first magnetic tunneling junction structure 50A, the fourth metal interconnect 70B is disposed on and in contact with the second magnetic tunneling junction structure 50B, the fifth metal interconnect 40A is disposed below and in contact with the first magnetic tunneling junction structure 50A, and the sixth metal interconnect 40B is disposed below and in contact with the second magnetic tunneling junction structure 50B. In other words, the third metal interconnect 70A and the fifth metal interconnect 40A can be disposed above and below the first magnetic tunneling junction structure 50A respectively in the third direction D3 and are directly connected to the first magnetic tunneling junction structure 50A, while the fourth metal interconnect 70B and the sixth metal interconnect 40B can be disposed above and below the second magnetic tunneling junction structure 50B respectively in the third direction D3 and are directly connected to the second magnetic tunneling junction structure 50B. Furthermore, the first metal interconnect 40C in the interconnect structure CS can be disposed between the fifth metal interconnect 40A and the sixth metal interconnect 40B in the first direction D1, while the second metal interconnect 72 in the interconnect structure CS can be disposed between the third metal interconnect 70A and the fourth metal interconnect 70B in the first direction D1.

[0074] In some embodiments, the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B may be formed together using the same manufacturing process. Therefore, the material composition of the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B may be the same as each other, but this is not a limitation. In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may be formed together using the same manufacturing process. Therefore, the material composition of the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may be the same as each other, but this is not a limitation. In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may be substantially disposed on the same plane. Therefore, a bottom surface BS3 of the first metal interconnect 40C, a bottom surface BS1 of the fifth metal interconnect 40A, and a bottom surface BS2 of the sixth metal interconnect 40B may be substantially coplanar. Furthermore, since the first metal interconnect 40C and the second metal interconnect 72 in the interconnect structure CS are directly connected to each other without an MTJ structure, the bottom surface of the second metal interconnect 72 may be lower than the bottom surface of the third metal interconnect 70A and the bottom surface of the fourth metal interconnect 70B in the third direction D3. In some embodiments, the upper part of the first metal interconnect 40C may be reduced due to the manufacturing process, so the upper surface TS3 of the first metal interconnect 40C and the bottom surface of the second metal interconnect 72 may be slightly lower than the upper surface TS1 of the fifth metal interconnect 40A and the upper surface TS2 of the sixth metal interconnect 40B in the third direction D3, but this is not a limitation. In addition, in some embodiments, the bottom width of the second metal interconnect 72 (e.g. Figure 1 The width W2 shown may be greater than the top width of the first metal interconnect 40C (e.g., Figure 1 The width W1 shown in the figure reduces the negative impact on the electrical connection between the second metal interconnect 72 and the first metal interconnect 40C when alignment misalignment occurs due to variations in the manufacturing process, but is not limited thereto.

[0075] In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may each be considered as a via conductor extending primarily in a vertical direction (e.g., third direction D3), while the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B may each be considered as a trench conductor extending primarily in a horizontal direction. In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may each include a barrier layer 41 and a metal layer 42, but are not limited thereto. The barrier layer 41 may include titanium (Ti), titanium nitride (TiN), or other suitable barrier materials, while the metal layer 42 may include tungsten (W), aluminum (Al), titanium-aluminum alloy (TiAl), or other suitable metallic materials. In some embodiments, the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B may each include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer. Since the third metal interconnect 70A and the fourth metal interconnect 70B are respectively disposed on the MTJ structure and the barrier layer can be used to avoid the negative impact of metal layer diffusion on the MTJ structure, the metal layers in the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B can use metal materials with low resistivity but potential diffusion concerns (e.g., copper), but are not limited thereto. In contrast, since the metal layer 42 in the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B will directly contact the MTJ structure, the metal layer 42 is not suitable to be formed of copper, and the material composition of the second metal interconnect 72 may therefore be different from the material composition of the first metal interconnect 40C. For example, the metal layer 42 mentioned above may be tungsten, and the corresponding barrier layer 41 may be titanium, titanium nitride, or / and a stack of these two materials, while the metal layer in the second metal interconnect 72 may be copper, and the corresponding barrier layer may be tantalum nitride (TaN) or other suitable barrier materials.

[0076] In some embodiments, substrate 10 may include a semiconductor substrate or a non-semiconductor substrate. The semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, while the non-semiconductor substrate may include a glass substrate, a plastic substrate, or a ceramic substrate, but is not limited thereto. For example, when substrate 10 includes a semiconductor substrate, multiple silicon-based field-effect transistors (not shown) may be formed on the semiconductor substrate as needed, along with a dielectric layer covering the silicon-based field-effect transistors (e.g., [insert dielectric layer here]). Figure 1The dielectric layer 11 and dielectric layer 21 shown are followed by a metal interconnect 22, and then the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B described above are formed. In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B may be electrically connected to a portion of the metal interconnect 22, and may be electrically connected downwards to the silicon-based field-effect transistor described above through a portion of the metal interconnect 22, but this is not a limitation. In some embodiments, each metal interconnect 22 may also be considered as a trench conductor extending primarily in the horizontal direction. Furthermore, in some embodiments, the substrate 10 may include a first region R1 and a second region R2, wherein the first region R1 may be considered as a memory cell region on which an MTJ structure is disposed, and the second region R2 located between two adjacent first regions R1 may be considered as a region corresponding to a character line. Therefore, the metal interconnect 22 disposed on the second region R2 and electrically connected to the first metal interconnect 40C may include a character line WL, but this is not a limitation.

[0077] In some embodiments, the semiconductor device 100 may further include a stop layer 23, a first inter-metal dielectric (IMD) layer 30, a capping layer 61, a second inter-metal dielectric layer 62, an ultra-low dielectric constant (ULK) dielectric layer 63, and an opening OP. The first inter-metal dielectric layer 30 may be disposed on the substrate 10 and located on the dielectric layer 21, while the stop layer 23 may be disposed between the first inter-metal dielectric layer 30 and the dielectric layer 21. The capping layer 61 may be disposed on the first magnetic tunneling junction structure 50A, the second magnetic tunneling junction structure 50B, and the first inter-metal dielectric layer 30, while the second inter-metal dielectric layer 62 may be disposed on the capping layer 61. The opening OP may be disposed on the first metal interconnect 40C and penetrate the second inter-metal dielectric layer 62 and the capping layer 61 in a third direction D3, while the second metal interconnect 72 may be disposed in the opening OP. In some embodiments, an ultra-low dielectric constant layer 63 may be disposed on the second intermetallic dielectric layer 62 and in the opening OP, and at least a portion of the ultra-low dielectric constant layer 63 may be located between the second metal interconnect 72 and the second intermetallic dielectric layer 62 in the first direction D1, but is not limited thereto. In some embodiments, the first intermetallic dielectric layer 30 and the stop layer 23 may be horizontally surrounding the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B, the capping layer 61 may be located on the sidewalls of the first magnetic tunneling junction structure 50A and the second magnetic tunneling junction structure 50B, and the second intermetallic dielectric layer 62 may be horizontally surrounding a portion of the third metal interconnect 70A and the fourth metal interconnect 70B, but is not limited thereto.

[0078] In some embodiments, the second metal interconnect 72 may penetrate the ultra-low dielectric layer 63 in the opening OP in the third direction D3, while the third metal interconnect 70A and the fourth metal interconnect 70B may respectively penetrate the second inter-metal dielectric layer 62 and the ultra-low dielectric layer 63 on the first magnetic tunneling junction structure 50A and the second inter-metal dielectric layer 62 and the ultra-low dielectric layer 63 on the second magnetic tunneling junction structure 50B in the third direction D3. Furthermore, in some embodiments, the substrate 10 may further include a third region R3, and the semiconductor device 100 may further include a metal interconnect 74 disposed on the third region R3 and electrically connected to the metal interconnect 22 on the third region R3. The third region R3 may be considered a logic region, but is not limited thereto. In some embodiments, the metal interconnect 74 may include a contact hole conductor 74A and a trench conductor 74B interconnected to form a dual damascene structure, but is not limited thereto. In some embodiments, a single damascene or other suitable structure of the metal interconnect 74 formed on the third region R3 may also be used, depending on design requirements.

[0079] In some embodiments, the structure of the metal interconnect 22 may be similar to that of the second metal interconnect 72, including a barrier layer (not shown) and a metal layer (not shown), but is not limited thereto. The dielectric layer 11, dielectric layer 21, first intermetallic dielectric layer 30, and second intermetallic dielectric layer 62 may each include silicon oxide, a low dielectric constant dielectric material, or other suitable dielectric materials, while the ultra-low dielectric constant dielectric layer 63 may include a dielectric material with a dielectric constant lower than 2.7, such as benzocyclclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methylsilesquioxane), silicon oxyhydrocarbon (SiOC-H), porous dielectric materials, or other suitable dielectric materials. The stop layer 23 may include a nitrogen-doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or other suitable insulating materials, while the capping layer 61 may include silicon nitride or other dielectric materials different from the first intermetallic dielectric layer 30 and the second intermetallic dielectric layer 62. Thus, the capping layer 61 can be used as an etch stop layer, but is not limited thereto.

[0080] In some embodiments, the semiconductor device 100 may include a plurality of metal interconnects 40, a plurality of magnetic tunneling junction structures 50, and a plurality of metal interconnects 70. Each magnetic tunneling junction structure 50 may be correspondingly disposed and electrically connected to one metal interconnect 40 and one metal interconnect 70, wherein two adjacent magnetic tunneling junction structures 50 may be respectively regarded as the first magnetic tunneling junction structure 50A and the second magnetic tunneling junction structure 50B described above, two metal interconnects 40 may be respectively regarded as the fifth metal interconnect 40A and the sixth metal interconnect 40B described above, and two metal interconnects 70 may be respectively regarded as the third metal interconnect 70A and the fourth metal interconnect 70B described above.

[0081] In some embodiments, each magnetic tunneling junction structure 50 may include a first electrode 51, a pinned layer 52, a first barrier layer 53, a free layer 54, a second barrier layer 55, and a second electrode 56 sequentially stacked on a third direction D3, but is not limited thereto. In some embodiments, the magnetic tunneling junction structure 50 may also include a stacked structure of materials different from those described above and / or other material layers as needed. In some embodiments, the first electrode 51 and the second electrode 56 may include metallic materials such as tantalum (Ta), platinum (Pt), ruthenium (Ru), composite layers or alloys of the above materials, or other suitable conductive materials. The pinned layer 52 may include an antiferromagnetic layer and a reference layer. The antiferromagnetic layer may include antiferromagnetic materials such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), cobalt / platinum (Co / Pt) composite layers, or other suitable antiferromagnetic materials. The reference layer in the free layer 54 and the locking layer 52 may include a ferromagnetic material, such as iron, cobalt, nickel, cobalt-iron (CoFe) alloy, cobalt-iron-boron (CoFeB) or other suitable ferromagnetic materials. The first barrier layer 53 and the second barrier layer 55 may include an insulating material, such as magnesium oxide (MgO), aluminum oxide or other suitable insulating materials. In some embodiments, the material layers in the magnetic tunneling junction structure 50 described above may be formed using a deposition process such as sputtering, but are not limited thereto.

[0082] Please see Figure 1 and Figure 2 . Figure 2 The illustration is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. In some embodiments, Figure 2 It can be regarded as a drawing Figure 1 The diagram shows the top view of the first region R1 and the second region R2, but does not show the third region R3, although this is not a limitation. Figure 2 and Figure 1 As shown, in some embodiments, the second metal interconnect 72 may extend along a first horizontal direction (e.g., first direction D1), and the third metal interconnect 70A and the fourth metal interconnect 70B may each extend along a second horizontal direction (e.g., second direction D2), and the first direction D1 may be substantially orthogonal to the second direction D2, but is not limited thereto. In some embodiments, the character line WL may extend along the second direction D2 and be arranged parallel to the metal interconnect 70, and the character line WL may be arranged corresponding to multiple interconnect structures CS, thereby reducing the negative impact of forming a single large and deep second metal interconnect 72 on adjacent metal interconnects 70 and / or magnetic tunnel junction structures 50, such as the loading effect when corresponding to etching trenches, but is not limited thereto. Therefore, the extension direction of the second metal interconnect 72 in the interconnect structure CS may be different from the extension direction of the metal interconnect 70. In some embodiments, the length of the second metal interconnect 72 in the first direction D1 is greater than the length of the second metal interconnect 72 in the second direction D2, and the length of the metal interconnect 70 in the second direction D2 is greater than the length of the metal interconnect 70 in the first direction D1. Furthermore, in some embodiments, the length of the first metal interconnect 40C in the first direction D1 may be less than the length of the second metal interconnect 72 in the first direction D1, and the length of the first metal interconnect 40C in the first direction D1 may be substantially equal to the length of the first metal interconnect 40C in the second direction D2, but is not limited thereto.

[0083] Please see Figures 3 to 6 as well as Figure 1 . Figures 3 to 6 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 The following is a diagram illustrating the situation, and Figure 1 It can be regarded as a drawing Figure 6 The following is a schematic diagram of the situation, but it is not limited to this. For example... Figure 1As shown, the method for fabricating the semiconductor device 100 in this embodiment may include the following steps: A first magnetic tunneling junction structure 50A, a second magnetic tunneling junction structure 50B, and an interconnect structure CS are formed on a substrate 10. The interconnect structure CS is located between the first magnetic tunneling junction structure 50A and the second magnetic tunneling junction structure 50B in a first direction D1. The interconnect structure CS includes a first metal interconnect 40C and a second metal interconnect 72. The second metal interconnect 72 is disposed on and in contact with the first metal interconnect 40C. The material composition of the second metal interconnect 72 is different from the material composition of the first metal interconnect 40C. In addition, a third metal interconnect 70A and a fourth metal interconnect 70B may be formed on the substrate 10. The third metal interconnect 70A is disposed on and in contact with the first magnetic tunneling junction structure 50A. The fourth metal interconnect 70B is disposed on and in contact with the second magnetic tunneling junction structure 50B. The second metal interconnect 72 extends along the first direction D1, and the third metal interconnect 70A and the fourth metal interconnect 70B extend along the second direction D2, respectively.

[0084] Further explanation: The method for fabricating the semiconductor device in this embodiment may include, but is not limited to, the following steps. First, as... Figure 3As shown, a dielectric layer 11, a dielectric layer 21, a metal interconnect 22, a stop layer 23, a first intermetallic dielectric layer 30, a metal interconnect 40, a first metal interconnect 40C, a magnetic tunneling junction structure 50, and a capping layer 61 are formed on a substrate 10. In some embodiments, the magnetic tunneling junction structure 50 can be formed by patterning the required material layers in the magnetic tunneling junction structure 50 using an etching process, and this etching process may include reactive ion etching (RIE) and / or ion beam etching (IBE) processes, but is not limited thereto. Due to the characteristics of the ion beam etching process, a portion of the first intermetallic dielectric layer 30 may be removed during the fabrication process of forming the magnetic tunneling junction structure 50, such that the upper surface of the remaining first intermetallic dielectric layer 30 may include a recessed surface, such as a concave arcuate surface. In some embodiments, the first metal interconnect 40C, the fifth metal interconnect 40A, and the sixth metal interconnect 40B can be formed together using the same material and fabrication process. The first inter-metal dielectric layer 30 located between the fifth metal interconnect 40A and the sixth metal interconnect 40B will have a relatively high upper surface due to the influence of the first metal interconnect 40C. Therefore, the upper surface of the first inter-metal dielectric layer 30 located between the fifth metal interconnect 40A and the sixth metal interconnect 40B can be higher than the recessed surface of the first inter-metal dielectric layer 30 in other regions (e.g., the first inter-metal dielectric layer 30 on the third region R3), but is not limited thereto. Furthermore, the capping layer 61 can be conformally formed on the first inter-metal dielectric layer 30, the magnetic tunneling junction structure 50, and the first metal interconnect 40C.

[0085] Then, as Figure 4 As shown, a second intermetallic dielectric layer 62 can be formed on the capping layer 61. In some embodiments, the second intermetallic dielectric layer 62 can be fabricated using an etch-back process to reduce its thickness, but this is not a limitation. Subsequently, as... Figure 5 As shown, a portion of the second inter-metal dielectric layer 62 and capping layer 61 can be removed to form an opening OP, and the opening OP exposes the first metal interconnect 40C. In some embodiments, a portion of the first metal interconnect 40C is removed by the fabrication process (e.g., etching process) that forms the opening OP, such that the upper surface TS3 of the first metal interconnect 40C is slightly lower than the upper surface TS1 of the fifth metal interconnect 40A and the upper surface TS2 of the sixth metal interconnect 40B in the third direction D3. Furthermore, the second inter-metal dielectric layer 62 and capping layer 61 on the third region R3 can be removed to expose the first inter-metal dielectric layer 30 on the third region R3. Then, as... Figure 6As shown, an ultra-low dielectric constant dielectric layer 63 is formed, which can be formed in the opening OP, on the second intermetallic dielectric layer 62, and on the first intermetallic dielectric layer 30 on the third region R3.

[0086] In some embodiments, the ultra-low dielectric layer 63 can be fabricated using an etch-back process to reduce its thickness, but this is not a limitation. Furthermore, due to the shape of the magnetic tunneling junction structure 50, the surface of the ultra-low dielectric layer 63 is less likely to be smooth. However, compared to the case where the first metal interconnect 40C is not formed, the surface height difference of the ultra-low dielectric layer 63 can be improved by the presence of the first metal interconnect 40C. For example, without the first metal interconnect 40C, the bottom surface of the opening corresponding to the second region R2 will have a similar height to the surface of the first intermetallic dielectric layer 30 on the third region R3 in the third direction D3. This situation will affect the surface of the subsequently formed ultra-low dielectric layer 63, resulting in a larger surface height difference.

[0087] Then, as Figure 6 and Figure 1 As shown, metal interconnects 70, 72, and 74 can be formed. In some embodiments, metal interconnects 70, 72, and 74 can be formed together using the same material and the same fabrication process, but this is not a limitation. For example, trenches corresponding to the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B can be formed first, such as trenches penetrating the ultra-low dielectric layer 63 on the first metal interconnect 40C and trenches penetrating the ultra-low dielectric layer 63, the second intermetallic dielectric layer 62, and the capping layer 61 on the magnetic tunnel junction structure 50. Then, the corresponding metal material is filled into the trenches, and a chemical mechanical polishing process is performed on the metal material to remove some of the metal material, thereby forming the second metal interconnect 72, the third metal interconnect 70A, and the fourth metal interconnect 70B. In the aforementioned chemical mechanical polishing (CMP) process, the surface flatness of the ultra-low dielectric layer 63 affects the CMP process. For example, if the surface height difference of the ultra-low dielectric layer 63 is too large, it may cause metal material residue in the ultra-low dielectric layer 63, resulting in an electrical connection between the second metal interconnect 72 and the metal interconnect 70, which are designed to be electrically separated. Therefore, the interconnect structure CS formed between the two magnetic tunneling junction structures 50 by the first metal interconnect 40C and the second metal interconnect 72 can reduce the surface height difference of the ultra-low dielectric layer 63, thereby improving the semiconductor device manufacturing yield.

[0088] In summary, in the semiconductor device of the present invention, an interconnect structure can be formed between two magnetic tunneling junction structures using a first metal interconnect and a second metal interconnect, thereby improving problems such as electrical connection between the interconnect structure and the magnetic tunneling junction structure caused by the close proximity of the magnetic tunneling junction structures, and thus improving the manufacturing yield of the semiconductor device.

[0089] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Base; A first magnetic tunnel junction structure is disposed on the substrate; A second magnetic tunnel junction structure is disposed on the substrate; An interconnect structure is disposed on the substrate and located in a first horizontal direction between the first magnetic tunneling junction structure and the second magnetic tunneling junction structure, the first horizontal direction being parallel to the upper surface of the substrate, wherein the interconnect structure includes: First metal interconnect; and A second metal interconnect is disposed on and in contact with the first metal interconnect, wherein the material composition of the second metal interconnect is different from that of the first metal interconnect; A fifth metal interconnect is disposed below and in contact with the first magnetic tunneling junction structure; and The sixth metal interconnect is disposed below and in contact with the second magnetic tunneling junction structure, wherein the first metal interconnect is located between the fifth metal interconnect and the sixth metal interconnect in the first horizontal direction, and the first metal interconnect, the fifth metal interconnect and the sixth metal interconnect are formed together by the same material and manufacturing process.

2. The semiconductor device of claim 1, further comprising: A third metal interconnect is disposed on and in contact with the first magnetic tunnel junction structure; as well as A fourth metal interconnect is disposed on and in contact with the second magnetic tunneling junction structure, wherein the material composition of the second metal interconnect, the material composition of the third metal interconnect, and the material composition of the fourth metal interconnect are the same as each other.

3. The semiconductor device of claim 2, wherein the second metal interconnect extends along the first horizontal direction, and the third metal interconnect and the fourth metal interconnect extend along a second horizontal direction, the second horizontal direction being parallel to the upper surface of the substrate.

4. The semiconductor device of claim 3, wherein the first horizontal direction is orthogonal to the second horizontal direction.

5. The semiconductor device of claim 1, wherein the bottom surface of the first metal interconnect, the bottom surface of the fifth metal interconnect, and the bottom surface of the sixth metal interconnect are coplanar.

6. The semiconductor device of claim 1, wherein the upper surface of the first metal interconnect is lower than the upper surface of the fifth metal interconnect and the upper surface of the sixth metal interconnect in the thickness direction of the substrate.

7. The semiconductor device of claim 1, further comprising: A first intermetallic dielectric layer is disposed on the substrate, wherein the first intermetallic dielectric layer surrounds the first metal interconnect; A capping layer is disposed on the first magnetic tunneling junction structure, the second magnetic tunneling junction structure, and the first intermetallic dielectric layer; A second intermetallic dielectric layer is disposed on the capping layer; as well as An opening is formed in the first metal interconnect and extends through the second intermetallic dielectric layer and the capping layer, wherein the second metal interconnect is disposed in the opening.

8. The semiconductor device of claim 7, further comprising: An ultra-low dielectric constant dielectric layer is disposed on the second intermetallic dielectric layer and in the opening, wherein at least a portion of the ultra-low dielectric constant dielectric layer is located between the second metal interconnect and the second intermetallic dielectric layer in the first horizontal direction.

9. A semiconductor device, comprising: Base; A first magnetic tunnel junction structure is disposed on the substrate; A second magnetic tunnel junction structure is disposed on the substrate; An interconnect structure is disposed on the substrate and located in a first horizontal direction between the first magnetic tunneling junction structure and the second magnetic tunneling junction structure, wherein the interconnect structure includes: First metal interconnect; and A second metal interconnect is disposed on and in contact with the first metal interconnect; A third metal interconnect is disposed on and in contact with the first magnetic tunnel junction structure; A fourth metal interconnect is disposed on and in contact with the second magnetic tunneling junction structure, wherein the second metal interconnect extends along the first horizontal direction, and the third metal interconnect and the fourth metal interconnect extend along the second horizontal direction respectively, wherein the first horizontal direction is parallel to the upper surface of the substrate, and the second horizontal direction is parallel to the upper surface of the substrate. A fifth metal interconnect is disposed below and in contact with the first magnetic tunneling junction structure; and The sixth metal interconnect is disposed below and in contact with the second magnetic tunneling junction structure, wherein the first metal interconnect is located between the fifth metal interconnect and the sixth metal interconnect in the first horizontal direction, and the first metal interconnect, the fifth metal interconnect and the sixth metal interconnect are formed together by the same material and manufacturing process.

10. The semiconductor device of claim 9, wherein the first horizontal direction is orthogonal to the second horizontal direction.

11. The semiconductor device of claim 9, wherein the material composition of the second metal interconnect, the material composition of the third metal interconnect, and the material composition of the fourth metal interconnect are the same as each other.

12. The semiconductor device of claim 9, wherein the bottom surface of the first metal interconnect, the bottom surface of the fifth metal interconnect, and the bottom surface of the sixth metal interconnect are coplanar.

13. The semiconductor device of claim 9, wherein an upper surface of the first metal interconnect is lower in the thickness direction of the substrate than the upper surface of the fifth metal interconnect and an upper surface of the sixth metal interconnect.

14. The semiconductor device of claim 9, further comprising: A first intermetallic dielectric layer is disposed on the substrate, wherein the first intermetallic dielectric layer surrounds the first metal interconnect; A capping layer is disposed on the first magnetic tunneling junction structure, the second magnetic tunneling junction structure, and the first intermetallic dielectric layer; A second intermetallic dielectric layer is disposed on the capping layer; as well as An opening is formed in the first metal interconnect and extends through the second intermetallic dielectric layer and the capping layer, wherein the second metal interconnect is disposed in the opening.

15. The semiconductor device of claim 14, further comprising: An ultra-low dielectric constant dielectric layer is disposed on the second intermetallic dielectric layer and in the opening, wherein at least a portion of the ultra-low dielectric constant dielectric layer is located between the second metal interconnect and the second intermetallic dielectric layer in the first horizontal direction.

16. The semiconductor device of claim 9, wherein the material composition of the second metal interconnect is different from that of the first metal interconnect, and the bottom width of the second metal interconnect is greater than the top width of the first metal interconnect.

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