Electrostatic discharge protection circuit

Abstract

The present invention provides an electrostatic discharge protection circuit comprising a first transistor, a second transistor, a capacitor, a voltage divider circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail, with the bulk of the second transistor coupled to the control terminal of the first transistor. The capacitor is coupled between the first power rail and the control terminal of the second transistor. The voltage divider circuit is coupled between the control terminal of the second transistor and the second power rail, and has a voltage divider output terminal coupled to the bulk of the second transistor. The first diode is coupled between the voltage divider output terminal and the second power rail.

Description

Technical Field

[0001] The present invention relates to an electrostatic discharge protection circuit, and in particular to an electrostatic discharge protection circuit capable of improving electrostatic discharge protection capability. Background Art

[0002] Conventional knowledge suggests that to protect integrated circuits from damage caused by electrostatic discharge (ESD), ESD protection circuits are typically incorporated into integrated circuits to provide a path for the ESD current to escape and prevent damage to circuit components. Power clamp circuits are often installed between power rails to serve as ESD protection circuits.

[0003] During electrostatic discharge (ESD), positive or negative voltage pulses may be generated between the power rails of an integrated circuit (IC). ESD protection circuits must effectively create current discharge paths to protect the IC. Existing circuits often configure circuit components to accommodate the various voltage pulse states encountered during ESD to provide current discharge paths. This approach often requires additional circuit components and wastes circuit layout area. Summary of the Invention

[0004] The present invention is directed to an electrostatic discharge protection circuit, which can reduce circuit layout area and enhance electrostatic discharge protection capability.

[0005] According to an embodiment of the present invention, an electrostatic discharge protection circuit includes a first transistor, a second transistor, a capacitor, a voltage divider circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail, and the bulk of the second transistor is coupled to the control terminal of the first transistor. The capacitor is coupled between the first power rail and the control terminal of the second transistor. The voltage divider circuit is coupled between the control terminal of the second transistor and the second power rail, and has a voltage divider output terminal coupled to the bulk of the second transistor. The first diode is coupled between the voltage divider output terminal and the second power rail.

[0006] As described above, the present invention forms a diode between the bulk of the second transistor and the capacitor-resistor network used to provide a bias voltage to the control terminal of the second transistor. This diode provides a path to instantly turn on the first transistor when a negative voltage pulse is generated, quickly providing a discharge path for electrostatic discharge current, and effectively improving the electrostatic discharge protection capability. In this embodiment, the diode can be formed by the materials of the resistor (N-type) and the substrate (P-type) in the integrated circuit, eliminating the need for additional layout arrangements and saving circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0008] Figure 1 is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention;

[0009] Figure 2 For the present invention Figure 1 A cross-sectional view of the layout structure of the resistor R2 and the diode D1 in the embodiment;

[0010] Figure 3A as well as Figure 3B Schematic diagram of electrostatic discharge protection operation of an electrostatic discharge protection circuit according to an embodiment of the present invention;

[0011] Figure 4 is a circuit diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention;

[0012] Figure 5 For the present invention Figure 4 A top view of a partial layout structure of an electrostatic discharge protection circuit 400 according to an embodiment.

[0013] Explanation of Figure Numbers

[0014] 100, 300, 400: electrostatic discharge protection circuit;

[0015] 110, 410: voltage divider circuit;

[0016] 210: Well area;

[0017] 211, 212, 221: doped regions;

[0018] 220: base;

[0019] BK: block;

[0020] C1: capacitor;

[0021] D1, D2: diodes;

[0022] DOE: divided voltage output terminal;

[0023] G1: gate;

[0024] GND: ground voltage;

[0025] M1, M2: transmission conductors;

[0026] ND1~ND3: doping area;

[0027] NW: N-type well area;

[0028] PATH1~PATH4: path;

[0029] PS1: negative pulse voltage;

[0030] PS2: positive pulse voltage;

[0031] PWR1, PWR2: power rails;

[0032] R1, R2: resistors;

[0033] SUB: base;

[0034] T1, T2 transistors;

[0035] VDD: power supply voltage;

[0036] VIA1~VIA5: connecting windows. DETAILED DESCRIPTION

[0037] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0038] Please refer to Figure 1 , Figure 1 This is a schematic diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention. The electrostatic discharge protection circuit 100 includes transistors T1, T2, a capacitor C1, a voltage divider circuit 110, and a diode D1. Transistor T1 is coupled between a first power rail PWR1 and a second power rail PWR2. Transistor T2 is coupled between a first power rail PWR1 and a second power rail PWR2. The bulk of transistor T2 is coupled to the control terminal of transistor T1. In this embodiment, transistor T1 is a bipolar junction transistor (BJT), and transistor T2 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In detail, transistor T1 can be an NPN bipolar transistor, and transistor T2 can be an N-type metal-oxide-semiconductor field-effect transistor.

[0039] In this embodiment, the first power rail PWR1 may be used to receive a power voltage, and the second power rail PWR2 may be used to receive a ground voltage.

[0040] In addition, capacitor C1 is coupled between the first power rail PWR1 and the control terminal of transistor T2, where the control terminal of transistor T2 is its gate terminal. A voltage divider circuit 110 is coupled between the control terminal of transistor T2 and the second power rail PWR2. The voltage divider circuit 110 has a voltage divider output terminal DOE coupled to the bulk of transistor T2. In this embodiment, the voltage divider circuit 110 includes resistors R1 and R2. One end of resistor R1 is coupled to the control terminal of transistor T2, and the other end of resistor R1 is coupled to the voltage divider output terminal DOE. One end of resistor R2 is coupled to the voltage divider output terminal DOE, and the other end of resistor R2 is coupled to the second power rail PWR2.

[0041] An anode of the diode D1 is coupled to the second power rail PWR2 , and a cathode of the diode D1 is coupled to the divided voltage output terminal DOE, and is further coupled to the bulk of the transistor T2 via the divided voltage output terminal DOE.

[0042] In this embodiment, capacitor C1 and voltage divider circuit 110 are used to divide the positive pulse voltage generated by electrostatic discharge (ESD) on the first power rail PWR1. This voltage divider generates a bias voltage at the divided voltage output terminal DOE to turn on transistor T1. Turning on transistor T1 creates a current dissipation path, thereby achieving ESD protection.

[0043] On the other hand, when a negative pulse voltage is generated on the first power rail PWR1 due to electrostatic discharge (ESD), diode D1 is turned on in response to the negative pulse voltage and provides a bias voltage to turn on transistor T1. Similarly, turning on transistor T1 creates a current discharge path, achieving ESD protection.

[0044] Please refer to the following Figure 1 as well as Figure 2 , Figure 2 For the present invention Figure 1 A cross-sectional view of the layout structure of resistor R2 and diode D1 in an embodiment. The electrostatic discharge protection circuit 100 is disposed in an integrated circuit. The integrated circuit comprises a substrate 220 and a well 210. The well 210 is disposed within the substrate 220. The well 210 includes doped regions 211 and 212. In this embodiment, the substrate 220 may be a P-type substrate, the well may be an N-type well, and both doped regions 211 and 212 may be N+-type doped regions.

[0045] In this embodiment, the resistor R2 can be used as an N-type well region and formed between the doped regions 211 and 212. By coupling the doped region 211 to the divided voltage output terminal DOE and coupling the doped region 212 to the second power rail PWR2, the Figure 1circuit architecture.

[0046] On the other hand, substrate 220 further includes a doped region 221. Doped region 221 can be a P+-type doped region and coupled to the second power rail PWR2. Thus, the PN junction formed by substrate 220 and well region 210 can construct a diode D1. Furthermore, the anode of diode D1 can be coupled to the second power rail PWR2 via doped region 221, while the cathode of diode D1 can be coupled to the divided voltage output terminal DOE via doped region 212.

[0047] From the above description, it is clear that the diode D1 in this embodiment can be formed by the parasitic effect generated by the layout of the resistor R2, and does not require additional layout area. Therefore, the layout area of the ESD protection circuit 100 of the embodiment of the present invention can be effectively reduced.

[0048] Please refer to the following Figure 3A as well as Figure 3B , Figure 3A as well as Figure 3B FIG. 1 is a schematic diagram of the electrostatic discharge protection action of the electrostatic discharge protection circuit according to an embodiment of the present invention. Figure 3A In the present invention, ESD protection circuit 300 has the same circuit architecture as ESD protection circuit 100, and the relevant details are not repeated here. When a negative pulse voltage PS1 is generated between the first power rail PWR1 and the second power rail PWR2 due to ESD, diode D1 can be turned on by the negative pulse voltage PS1, and a path PATH1 is generated between the negative pulse voltage PS1, diode D1, and the control terminal (base) of transistor T1. Through path PATH1, a bias voltage VB can be provided to the control terminal of transistor T1 in response to the negative pulse voltage PS1, turning on transistor T1. In this way, transistor T1 provides a current discharge path PATH2 for ESD protection.

[0049] On the other hand, when a positive pulse voltage PS2 is generated between the first power rail PWR1 and the second power rail PWR2 due to electrostatic discharge (ESD), the capacitor-resistor network formed by capacitor C1 and resistors R1 and R2 generates a bias voltage VB at the divided voltage output terminal DOE based on the positive pulse voltage PS2. The bias voltage VB is then provided to the control terminal of transistor T1 via path PATH3, turning on transistor T1 and providing a current discharge path PATH4 for ESD protection.

[0050] Please refer to the following Figure 4 , Figure 4This is a circuit diagram of an electrostatic discharge protection circuit according to another embodiment of the present invention. The electrostatic discharge protection circuit 400 includes transistors T1 and T2, a capacitor C1, a voltage divider circuit 410, and diodes D1 and D2. Transistor T1 is coupled between the first power rail PWR1 and the second power rail PWR2. Transistor T2 is coupled between the first power rail PWR1 and the second power rail PWR2. The bulk of transistor T2 is coupled to the control terminal of transistor T1. In this embodiment, transistor T1 is a bipolar transistor, and transistor T2 can be a metal oxide semiconductor field effect transistor. In detail, transistor T1 can be an NPN bipolar transistor, and transistor T2 can be an N-type metal oxide semiconductor field effect transistor.

[0051] In addition, capacitor C1 is coupled between the first power rail PWR1 and the control terminal of transistor T2, wherein the control terminal of transistor T2 is a gate terminal. The voltage divider circuit 410 is coupled between the control terminal of transistor T2 and the second power rail PWR2. The voltage divider circuit 410 has a voltage divider output terminal DOE to couple to the bulk of transistor T2. In this embodiment, the voltage divider circuit 410 includes resistors R1 and R2. One end of the resistor R1 is coupled to the control terminal of transistor T2, and the other end of the resistor R1 is coupled to the voltage divider output terminal DOE. One end of the resistor R2 is coupled to the voltage divider output terminal DOE, and the other end of the resistor R2 is coupled to the second power rail PWR2. The first power rail PWR1 and the second power rail PWR2 receive the power supply voltage VDD and the ground voltage GND, respectively.

[0052] In this embodiment, the anode of diode D1 is coupled to the second power rail PWR2, and the cathode of diode D1 is coupled to the divided voltage output terminal DOE, and is coupled to the bulk of transistor T2 through the divided voltage output terminal DOE. Furthermore, unlike the previous embodiment, the ESD protection circuit 400 of this embodiment further includes a diode D2. The anode of diode D2 is coupled to the divided voltage output terminal DOE, and the cathode of diode D2 is coupled to the control terminal of transistor T2, i.e., the gate of transistor T2.

[0053] Please refer to the following Figure 5 , Figure 5 For the present invention Figure 4A top view of a partial layout structure of the electrostatic discharge protection circuit 400 of an embodiment. In which, the first plate of the capacitor C1 is electrically connected to the first power rail PWR1 through a plurality of connection windows VIA2. The first power rail PWR1 is used to receive the power supply voltage VDD. The second plate of the capacitor C1 can be electrically connected to the gate G1 of the transistor T2 through a plurality of connection windows VIA3 and the transmission wire M1. In addition, the second plate of the capacitor C1 is electrically connected to the N-type well region NW through the transmission wire M2. There are a plurality of doped regions ND1 to ND3 in the N-type well region, wherein a resistor R1 can be formed between the doped regions ND1 to ND2, and a resistor R2 can be formed between the doped regions ND2 to ND3. A voltage divider output terminal DOE can also be provided on the doped region ND2.

[0054] Furthermore, an N-type well region NW is disposed within the substrate SUB. The substrate SUB is electrically connected to a second power rail PWR2 via a plurality of connection windows VIA4. The second power rail PWR2 receives a ground voltage GND. The substrate SUB is a P-type substrate and forms a PN junction with the N-type well region NW, creating diodes D1 and D2. This means that, in the present invention, diodes D1 and D2 do not require additional layout, effectively reducing the required circuit area.

[0055] Furthermore, the bulk BK of transistor T2 is electrically connected to the divided voltage output terminal DOE via multiple connections VIA1. The first terminal (drain) of transistor T2 is electrically coupled to the first power rail PWR1 via multiple connections VIA6, while the second terminal (source) of transistor T2 is electrically coupled to the second power rail PWR2 via multiple connections VIA5. The control terminal (base) of transistor T1 is embedded within the bulk of transistor T2 and electrically coupled to the divided voltage output terminal DOE via multiple connections VIA1. The first terminal (collector) of transistor T1 is embedded within the first terminal (drain) of transistor T2 and electrically coupled to the first power rail PWR1 via multiple connections VIA6. The second terminal (emitter) of transistor T1 is embedded within the second terminal (source) of transistor T2 and electrically coupled to the second power rail PWR2 via multiple connections V1A5. Therefore, transistor T1 does not require additional layout space, effectively reducing the overall circuit area.

[0056] Based on the above, the electrostatic discharge protection circuit proposed in the present invention can effectively enhance the protection capability against electrostatic discharge phenomena caused by negative pulse voltage by providing a reverse biased diode between the block of the metal oxide semiconductor field effect transistor and the second power rail without occupying additional layout area, thereby improving the reliability of the integrated circuit.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electrostatic discharge protection circuit, characterized in that: include: A first transistor coupled between a first power rail and a second power rail; a second transistor coupled between the first power rail and the second power rail, wherein a bulk of the second transistor is coupled to a control terminal of the first transistor; a capacitor coupled between the first power rail and the control terminal of the second transistor; a voltage divider circuit coupled between the control terminal of the second transistor and the second power rail, and having a voltage divider output terminal coupled to the bulk of the second transistor; as well as A first diode is coupled between the divided voltage output terminal and the second power rail. The voltage divider circuit comprises: a first resistor, a first end of which is coupled to the control end of the second transistor, and a second end of which is coupled to the divided voltage output end; as well as A second resistor is coupled between the divided voltage output terminal and the second power rail, the second resistor being formed by a well region of a first conductive type, the well region being disposed in a substrate having a second conductive type, the well region having a first doped region and a second doped region, the second resistor being formed between the first doped region and the second doped region, the first doped region being coupled to the bulk of the second transistor, and the second doped region being coupled to the second power rail.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that: A third doping region is defined in the substrate. The third doping region is coupled to the second power rail. The third doping region and the first doping region form the first diode.

3. The electrostatic discharge protection circuit according to claim 1, wherein: Also includes: The second diode is coupled between the bulk of the second transistor and the divided voltage output terminal.

4. The electrostatic discharge protection circuit according to claim 1, wherein: The first transistor is a bipolar transistor, and the second transistor is a metal oxide semiconductor field effect transistor.

5. The electrostatic discharge protection circuit according to claim 1, wherein: When a negative pulse voltage occurs between the first power rail and the second power rail, the negative pulse voltage passes through the first diode to turn on the first transistor, thereby providing a current discharge path for electrostatic discharge protection.

6. The electrostatic discharge protection circuit according to claim 1, wherein: When a positive pulse voltage occurs between the first power rail and the second power rail, the capacitor and the voltage divider circuit generate a bias voltage at the divided voltage output terminal according to the positive pulse voltage, and turn on the first transistor according to the bias voltage, thereby providing a current discharge path for electrostatic discharge protection by turning on the first transistor.

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