Output stage circuit and operational amplifier
By introducing cascaded transistor modules into the output stage circuit of the operational amplifier to share the current path voltage, the problem of the withstand voltage limitation of PMOS and NMOS is solved, and an output stage circuit with high output swing and good linearity is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RIGOL TECHNOLOGIES (BEIJING) INC
- Filing Date
- 2022-08-23
- Publication Date
- 2026-06-02
Smart Images
Figure CN115378381B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog circuits, and in particular to an output stage circuit and an operational amplifier. Background Technology
[0002] Operational amplifiers (op-amps) are common basic modules in analog circuits, offering high amplification. An op-amp is an integrated circuit containing multiple amplification stages. Its input stage provides differential voltage signals, featuring high input resistance and zero-point drift suppression; the output stage connects to the load, exhibiting strong load-driving capability and low output resistance. Operational amplifiers have a wide range of applications.
[0003] Output stage circuits typically include a PMOS transistor and an NMOS transistor. However, the voltage ratings of PMOS and NMOS transistors are limited, and the output voltage swing in practical circuits is often restricted by the voltage ratings of these transistors. This results in limitations in the entire circuit, making it difficult to achieve a high output swing using low-voltage PMOS and NMOS transistors. In addition, the linearity of MOS devices is also constrained. Summary of the Invention
[0004] In view of this, the present application provides an output stage circuit and an operational amplifier to solve at least one problem existing in the prior art.
[0005] In a first aspect, one embodiment of this application provides an output stage circuit applied to an operational amplifier, comprising:
[0006] A first input terminal and a second input terminal are used for connection with the input stage circuit; the input stage circuit and the output stage circuit are used together in the operational amplifier, and the input stage circuit is used to provide differential voltage signals to the first input terminal and the second input terminal;
[0007] The output terminal used to provide the output signal;
[0008] First power node for connecting to the first power source;
[0009] A second power node for connecting a second power source; wherein, the power supply voltage exists between the first power node and the second power node;
[0010] A first transistor is connected in a pull-up current path; wherein the pull-up current path extends from the first power node to the output terminal; the gate of the first transistor is connected to the first input terminal;
[0011] A second transistor is connected in a pull-down current path; wherein the pull-down current path extends from the output terminal to the second power supply node; the gate of the second transistor is connected to the second input terminal;
[0012] A cascaded transistor module is cascaded perpendicularly to the first transistor in the pull-up current path, and / or cascaded perpendicularly to the second transistor in the pull-down current path.
[0013] In conjunction with a first aspect of this application, in an alternative embodiment, the cascaded transistor module includes a first cascaded transistor module, the first cascaded transistor module including at least a third transistor and a fourth transistor.
[0014] In conjunction with the first aspect of this application, in an optional embodiment, it further includes:
[0015] A first bias circuit is used to transmit a first bias signal to the gate of the third transistor, and the first bias circuit is connected between the power supply voltage and the ground terminal.
[0016] In conjunction with the first aspect of this application, in an optional embodiment, the first cascaded transistor module is vertically cascaded with the first transistor in the pull-up current path;
[0017] The source of the third transistor is connected to the drain of the first transistor;
[0018] The first bias circuit is connected between the power supply voltage and the ground terminal, and includes: one end of the first bias circuit is connected to the third power supply node, and the other end of the first bias circuit is connected to the ground terminal; the third power supply node is independent of the first power supply node.
[0019] In conjunction with the first aspect of this application, in an optional embodiment, it further includes:
[0020] A second bias circuit is used to transmit a second bias signal to the gate of the fourth transistor, and the second bias circuit is connected between the output terminal and the ground terminal.
[0021] In conjunction with the first aspect of this application, in an optional embodiment, the first cascaded transistor module is vertically cascaded with the first transistor in the pull-up current path;
[0022] The cascaded transistor module further includes: a second cascaded transistor module, which is cascaded perpendicularly to the second transistor in the pull-down current path; the second cascaded transistor module is different from the first cascaded transistor module.
[0023] In conjunction with the first aspect of this application, in an alternative embodiment, the second cascaded transistor module includes a bipolar junction transistor.
[0024] In conjunction with the first aspect of this application, in an optional embodiment, it further includes:
[0025] A third bias circuit is used to transmit a third bias signal to the gate of the transistor included in the second cascaded transistor module. The third bias circuit includes a bias transistor, which, together with the transistor included in the second cascaded transistor module, forms a current mirror structure.
[0026] In conjunction with the first aspect of this application, in an optional embodiment, it further includes:
[0027] A third bias circuit is used to transmit a third bias signal to the gate of the transistor included in the second cascaded transistor module, the third bias circuit being connected between the second power supply node and the ground terminal.
[0028] In conjunction with the first aspect of this application, in an alternative embodiment,
[0029] Corresponding to the first cascaded transistor module being vertically cascaded with the first transistor in the pull-up current path, the device structure and withstand voltage of the third transistor, the fourth transistor, and the first transistor are all the same;
[0030] Corresponding to the first cascaded transistor module and the second transistor being vertically cascaded in the pull-down current path, the third transistor, the fourth transistor, and the second transistor have the same device structure and withstand voltage.
[0031] In conjunction with the first aspect of this application, in an alternative embodiment, the cascaded transistor module includes a second cascaded transistor module, the second cascaded transistor module including a bipolar junction transistor.
[0032] In conjunction with the first aspect of this application, in an optional embodiment, the cascaded transistor module further includes: a first cascaded transistor module, the first cascaded transistor module including a MOS transistor;
[0033] The second cascaded transistor module is vertically cascaded in one of the pull-up current path and the pull-down current path, and the first cascaded transistor module is vertically cascaded in the other of the pull-up current path and the pull-down current path.
[0034] In conjunction with the first aspect of this application, in an optional embodiment, the voltage rating of the bipolar junction transistor included in the second cascaded transistor module is greater than the voltage rating of the MOS transistor included in the first cascaded transistor module.
[0035] In conjunction with the first aspect of this application, in an optional embodiment, the number of MOS transistors included in the first cascaded transistor module is greater than the number of bipolar junction transistors included in the second cascaded transistor module.
[0036] In conjunction with the first aspect of this application, in an alternative embodiment, the second cascaded transistor module includes a first bipolar junction transistor;
[0037] The output stage circuit further includes a third bias circuit for transmitting a third bias signal to the gate of the first bipolar junction transistor. The third bias circuit includes a second bipolar junction transistor, and the second bipolar junction transistor and the first bipolar junction transistor form a current mirror structure.
[0038] In conjunction with the first aspect of this application, in an alternative embodiment, the third bias circuit is connected between the second power node and the ground terminal.
[0039] In conjunction with the first aspect of this application, in an optional embodiment, the third bias circuit further includes:
[0040] The fifth resistor is connected between the ground terminal and the collector of the second bipolar junction transistor; the second bipolar junction transistor is an NPN bipolar junction transistor, and the base and collector of the second bipolar junction transistor are shorted.
[0041] The sixth resistor is connected between the emitter of the second bipolar junction transistor and the second power supply node.
[0042] Secondly, one embodiment of this application provides an operational amplifier, including:
[0043] An input stage circuit for providing a differential voltage signal, and an output stage circuit as described in any of the foregoing embodiments.
[0044] The output stage circuit and operational amplifier provided in this application embodiment improve the output voltage swing of the output stage circuit by setting up a cascaded transistor module that is vertically cascaded with the first transistor in the pull-up current path and / or vertically cascaded with the second transistor in the pull-down current path. This allows the output stage circuit to share the voltage in the pull-up current path with the first transistor and / or share the voltage in the pull-down current path with the second transistor. In this way, the output voltage swing of the output stage circuit is improved without changing the first transistor and the second transistor.
[0045] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0046] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0047] Figure 1 This is a schematic diagram of the operational amplifier structure in related technologies;
[0048] Figure 2 This is a block diagram of an operational amplifier.
[0049] Figure 3 This is a block diagram of the input stage circuit.
[0050] Figure 4 This is a schematic diagram of the output stage circuit provided in one embodiment of this application;
[0051] Figure 5 This is a schematic diagram of the output stage circuit provided in another embodiment of this application;
[0052] Figure 6 This is a schematic diagram of the output stage circuit provided in another embodiment of the present application;
[0053] Figure 7 This is a schematic diagram of the output stage circuit provided in another embodiment of this application. Detailed Implementation
[0054] To make the technical solutions and beneficial effects of the present invention more apparent and understandable, the technical solutions in the embodiments of this application are clearly and completely described below by listing specific examples. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0056] It is understood that the terms “first,” “second,” etc., as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor. When “first” is described, it does not imply the necessary presence of a “second”; and when “second” is discussed, it does not imply the necessary presence of a first element, component, region, layer, or portion. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms unless the context clearly indicates otherwise. “A plurality” means two or more, unless otherwise explicitly specified. It should also be understood that the term “comprising,” when used in this specification, identifies the presence of the stated feature but does not exclude the presence or addition of one or more other features. As used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0057] It is understood that in the context of this application, "connection" means that there is an electrical signal or data transmission between the connected end and the connected end, which can be understood as "electrical connection", "communication connection", etc. In the context of this application, "A and B are directly connected" means that there are no other components between A and B except for wires.
[0058] Figure 1 This is a schematic diagram of an operational amplifier in related technologies. As shown, the operational amplifier 100 includes an input stage circuit 110 and an output stage circuit 120. The output stage circuit 120 mainly consists of a PMOS transistor M1 and an NMOS transistor M2. When the differential voltage provided by the input stage circuit 110 is small, the NMOS transistor M2 operates, the PMOS transistor M1 is cut off, and the output voltage is close to the VSS level. When the differential voltage provided by the input stage circuit 110 is large, the PMOS transistor M1 operates, the NMOS transistor M2 is cut off, and the output voltage is close to the VCC level. However, under a given process, the voltage withstand capability of NMOS and PMOS devices is limited. Assuming the output voltage is near VCC (i.e., near the positive power rail voltage), then the NMOS transistor M2 will withstand a voltage of VCC-VSS. In actual circuits, the VCC-VSS voltage is required to be less than the voltage withstand capability of the NMOS transistor M2. This results in a limitation in the entire circuit, namely, the voltage of the power rail cannot exceed the voltage withstand capability of the device. This limitation has drawbacks in practical applications. For example, if you want to use a 1.8V MOS device to implement a rail-to-rail circuit with an output amplitude of 3.3V, Figure 1 The solutions shown in the related technologies cannot be implemented. In addition, the linearity of MOS devices will also be limited.
[0059] This application provides an output stage circuit for an operational amplifier, the structure of which can be referred to... Figure 2 As shown in the figure, the operational amplifier 100 includes an input stage circuit 110 and an output stage circuit 120. The input stage circuit 110 provides a differential voltage signal to the first and second input terminals of the output stage circuit 120; the output stage circuit 120 is connected to the load and outputs a voltage with a certain swing. This swing can be rail-to-rail, meaning the output voltage range covers the vicinity of the negative power supply (close to VSS level) to the vicinity of the positive power supply (close to VCC level), or it can be any voltage range greater than the device's withstand voltage. Thus, it can be understood that the output stage circuit 120 provided in this embodiment is, for example, a rail-to-rail output stage circuit; while the input stage circuit 110 mainly implements rail-to-rail input.
[0060] Please refer to Figure 3 The input stage circuit 110 of the operational amplifier 100 may include a differential input circuit and a Class AB control circuit. It should be understood that this is only an illustrative example, and the specific implementation of the input stage circuit 110 is related to the function it is intended to achieve. Those skilled in the art can set it according to the actual situation, and no specific limitation is made here.
[0061] Next, please refer to Figures 4 to 7 The output stage circuit 120 provided in this application embodiment may include: a first input terminal and a second input terminal for connection to the input stage circuit 110; an output terminal for providing an output signal; a first power node for connecting a first power supply (refer to the location of VCC in the figure); a second power node for connecting a second power supply (refer to the location of VSS in the figure); wherein the power supply voltage exists between the first power node and the second power node; a first transistor M1 connected in a pull-up current path; wherein the pull-up current path extends from the first power node to the output terminal; the gate of the first transistor M1 is connected to the first input terminal; a second transistor M2 connected in a pull-down current path; wherein the pull-down current path extends from the output terminal to the second power node; the gate of the second transistor M2 is connected to the second input terminal.
[0062] The output stage circuit 120 may also include: a cascaded transistor module (see reference). Figures 4-7 (M10 and M20). The cascaded transistor module is cascaded vertically with the first transistor M1 in the pull-up current path, and / or cascaded vertically with the second transistor M2 in the pull-down current path.
[0063] Understandably, by setting up cascaded transistor modules that are vertically cascaded with the first transistor M1 in the pull-up current path and / or vertically cascaded with the second transistor M2 in the pull-down current path, the voltage in the pull-up current path is shared with the first transistor M1 and / or the voltage in the pull-down current path is shared with the second transistor M2. Thus, without changing the first transistor M1 and the second transistor M2, the output voltage swing of the output stage circuit 120 can be improved more effectively, while also ensuring good linearity. Furthermore, it can be understood that although... Figures 4 to 7 The diagram shows a case where cascaded transistor modules are set in both the pull-up current path and the pull-down current path, but it is clear that setting cascaded transistor modules in either the pull-up current path or the pull-down current path is also effective.
[0064] As one possible implementation, the cascaded transistor module includes a first cascaded transistor module M10. For example... Figure 4 As shown, the first cascaded transistor module M10 is vertically cascaded with the first transistor M1 in the pull-up current path; or, as... Figure 5 As shown, the first cascaded transistor module M10 and the second transistor M2 are vertically cascaded in the pull-down current path; or, as... Figure 6 As shown, a first cascaded transistor module M10 is configured both vertically cascaded with the first transistor M1 in the pull-up current path and vertically cascaded with the second transistor M2 in the pull-down current path. Furthermore, the first cascaded transistor module M10 includes at least a third transistor M3 and a fourth transistor M4.
[0065] By setting up the first cascaded transistor module M10, at least two transistors (i.e., the third transistor M3 and the fourth transistor M4) are added to either the pull-up current path or the pull-down current path. The added at least two transistors are vertically cascaded with the first transistor M1 and / or the second transistor M2 to share the voltage in the current path. In this way, without changing the first transistor M1 and the second transistor M2, the output voltage swing of the output stage circuit 120 can be improved more effectively, while ensuring good linearity.
[0066] Furthermore, with Figure 4 The structure in the illustrated embodiment is given as an example. Figure 4The output stage circuit 120 shown includes a first bipolar junction transistor (BJT) M5 vertically cascaded with the second transistor M2 in the pull-down current path. Assuming the output stage circuit 120 outputs a minimum voltage, this voltage should be greater than VSS by one VDS2 and one VCE5, i.e., equal to VSS + VDS2 + VCE5. Here, VDS2 is the voltage between the drain and source of the second transistor M2, and VCE5 is the voltage between the collector and emitter of the first BJT M5. Understandably, this voltage should be as small as possible, as a smaller voltage indicates a larger negative swing in the circuit. At this point, the maximum voltage that M1, M3, and M4 can withstand should be VCC - VDS2 - VCE5 - VSS. Considering the vertically cascaded configuration of the three transistors M1, M3, and M4, assuming these three transistors have the same withstand voltage, then VCC - VDS2 - VCE5 - VSS theoretically can reach three times the transistor's withstand voltage. Therefore, when VCC and VSS are twice the device withstand voltage, it is safe under any swing.
[0067] The following example illustrates this. Assume VCC is 1.8V, VSS is -1.8V, and the circuit uses devices with a 1.8V withstand voltage. Then, when the output is close to -1.8V, the maximum withstand voltage of M1, M3, and M4 cascaded vertically is 5.4V, making the circuit absolutely safe. Thus, theoretically, a 3.6V output swing can be easily achieved using 1.8V withstand voltage devices, thereby more effectively improving the output voltage swing of the output stage circuit 120.
[0068] In a specific application, the output voltage range is -2.1V to +2.1V; the withstand voltages of M1, M3, and M4 are 3.3V; the positive supply voltage VCC is 3.3V, and the negative supply voltage VSS is -3.3V. Therefore, transistors with a withstand voltage of 3.3V can be used as the main body of the output stage circuit to achieve a 4.2V swing output with harmonic performance above -70dBc within the op-amp band, thus achieving high harmonic performance in a high-swing circuit. The number of transistors included in the first cascaded transistor module M10 mainly depends on the relationship between the output voltage range and the device withstand voltage. For example, if the minimum output voltage is -2.1V and the positive supply voltage VCC is 3.3V, then the maximum withstand voltage of the vertically cascaded M1, M3, and M4 needs to reach 5.4V; therefore, at least two transistors are required, meaning the first cascaded transistor module M10 must include at least the third transistor M3 and the fourth transistor M4. Considering the margin design for practical applications, three transistors are the safest option. That is, the first cascaded transistor module M10 can include three or more transistors. For example, the first cascaded transistor module M10 can include a third transistor M3 and a fourth transistor M4, as well as another transistor vertically cascaded with the third transistor M3 and the fourth transistor M4. Ensuring that the output remains within the saturation region across the entire output range is crucial when using three transistors.
[0069] The first cascaded transistor module M10 includes transistors that can be MOSFETs, and all of them can be MOSFETs. For example... Figure 4 As shown, the first transistor M1 is a PMOS transistor, and the transistors in the first cascaded transistor module M10, which is vertically cascaded with the first transistor M1, are also PMOS transistors. That is, the third transistor M3 and the fourth transistor M4 are both PMOS transistors.
[0070] The source of the first transistor M1 is connected to the first power supply node, the drain of the first transistor M1 is connected to the source of the third transistor M3, the drain of the third transistor M3 is connected to the source of the fourth transistor M4, and the drain of the fourth transistor M4 is connected to the output terminal. Here, the connections between the transistors, as well as the connection between the source of the first transistor M1 and the first power supply node, and the connection between the drain of the fourth transistor M4 and the output terminal, can all be direct connections.
[0071] As an optional implementation, the output stage circuit 120 further includes a first bias circuit 123 for transmitting a first bias signal to the gate of the third transistor M3, the first bias circuit 123 being connected between the power supply voltage and the ground terminal.
[0072] The first bias circuit 123 connected to the third transistor M3 can be configured as a fixed voltage divider, meaning that the bias of the third transistor M3 does not follow the output voltage change. The reason for doing so is related to actual requirements.
[0073] For example, the first bias circuit 123 may further include: a first resistor R1 connected between the third power supply node and the gate of the third transistor M3; and a second resistor R2 connected between the gate of the third transistor M3 and the ground terminal.
[0074] For further information, please refer to the following: Figure 4 The first cascaded transistor module M10 is vertically cascaded with the first transistor M1 in the pull-up current path; the source of the third transistor M3 is connected to the drain of the first transistor M1; the first bias circuit M123 is connected between the power supply voltage and the ground terminal, specifically including: one end of the first bias circuit 123 is connected to the third power supply node (please refer to the third power supply node). Figure 4 In the first bias circuit 123, one end of the first bias circuit 123 is connected to the ground terminal; the third power supply node is independent of the first power supply node. In other words, VCC and VC2V are two independently operating power supplies that can be controlled independently.
[0075] In the first bias circuit 123, the bias voltage is obtained by dividing the power supply and ground terminals, which are independent of the output power rail. The advantage of doing so is that the power supply rejection ratio of the positive power supply of the output stage will be better.
[0076] As an optional implementation, the output stage circuit 120 further includes a second bias circuit 124 for transmitting a second bias signal to the gate of the fourth transistor M4, the second bias circuit 124 being connected between the output terminal and the ground terminal.
[0077] Understandably, when the output approaches the power rail, the circuit nonlinearity intensifies, leading to a deterioration in the circuit's harmonic performance. In this embodiment, the second bias circuit 124 is connected between the output terminal and the ground terminal, thereby generating a bias that is linked to the output voltage. As the output voltage changes, the bias voltage can fluctuate up and down. In this way, when the output approaches the power rail voltage, the operating state of the bias transistor can automatically and adaptively adjust, improving the circuit's harmonic performance.
[0078] The second bias circuit 124 uses a voltage divider between the ground terminal and the output voltage to obtain bias, which is a very simple and superior method. Specifically, when the output voltage is at 0V under normal conditions, no current flows through this bias branch, and no static power is generated. When the output voltage is +2.1V, the current in the bias branch flows from the output terminal to the ground terminal (see ground terminal reference). Figure 4The second bias circuit 124 contains GND, and as the output voltage increases, the voltage of the second bias signal also increases. After the bias voltage increases, the balanced overdrive voltage VOV of the fourth transistor M4 will decrease (the balanced overdrive voltage is equal to VGS-Vth; where VGS is the gate voltage minus the source voltage of the transistor, and Vth is the threshold voltage of the transistor). By selecting an appropriate resistor divider, it can be ensured that the fourth transistor M4 is just in the saturation region, that is, VDS4 equals VOV. At this time, the voltage drop occupied by the fourth transistor M4 in the circuit is minimal, and M1, M3 and M4 are all in the saturation region, with the highest linearity and optimal harmonic performance. When the output voltage is -2.1V, the current in the bias branch flows from the ground terminal to the output terminal; the output short-circuit current increases, and the operational amplifier's load-carrying capacity increases. In addition, when the bias voltage is less than GND, the fourth transistor M4 is in a state with a large balanced overdrive voltage. At this time, since the drain voltage VD of the fourth transistor is -2.1V, VDS4 is also large, just enough to keep it in the saturation region. In this way, the problem of poor operational amplifier linearity and harmonic performance caused by vertically cascaded transistors falling into the linear region under large swing is overcome.
[0079] For example, the second bias circuit 124 may further include: a third resistor R3 connected between the ground terminal and the gate of the fourth transistor M4; and a fourth resistor R4 connected between the gate of the fourth transistor M4 and the output terminal.
[0080] As an optional implementation, the cascaded transistor module further includes: a second cascaded transistor module M20. For example... Figure 5 As shown, the second cascaded transistor module M20 is vertically cascaded with the first transistor M1 in the pull-up current path; or, as... Figure 4 As shown, the second cascaded transistor module M20 and the second transistor M2 are vertically cascaded in the pull-down current path; or, as... Figure 7 As shown, a second cascaded transistor module M20 is set in the pull-up current path perpendicularly to the first transistor M1, and also in the pull-down current path perpendicularly to the second transistor M2.
[0081] For example, the second cascaded transistor module M20 is vertically cascaded in one of the pull-up current path and the pull-down current path, and the first cascaded transistor module M10 is vertically cascaded in the other of the pull-up current path and the pull-down current path.
[0082] Please continue to refer to this. Figure 4Optionally, the first cascaded transistor module M20 is vertically cascaded with the first transistor M1 in the pull-up current path; the second cascaded transistor module M20 is vertically cascaded with the second transistor M2 in the pull-down current path; the second cascaded transistor module M20 is different from the first cascaded transistor module M10. Thus, different adjustment effects are achieved for the pull-up current path and the pull-down current path.
[0083] Optionally, the second cascaded transistor module includes a bipolar junction transistor (BJT).
[0084] Optionally, the bipolar junction transistor (BJT) included in the second cascaded transistor module M20 has a higher voltage rating than the MOSFET included in the first cascaded transistor module M10. Understandably, in BICMOS (Bipolar CMOS technology, which integrates CMOS and bipolar devices on the same chip), it is common for BJTs to have better voltage ratings than MOSFETs. Therefore, using BJTs with higher voltage ratings can extend the safe operating area of the circuit.
[0085] For example, the bipolar junction transistor included in the second cascaded transistor module M20 has a voltage rating of, for example, 6V, and the MOSFET included in the first cascaded transistor module M10 has a voltage rating of, for example, 3.3V.
[0086] Optionally, the first cascaded transistor module M10 includes a greater number of MOSFETs than the second cascaded transistor module M20 includes a greater number of bipolar junction transistors. This saves on component usage, reduces costs, and lowers the weight and size of the circuit structure while meeting application requirements.
[0087] As an optional implementation, the output stage circuit 120 further includes a third bias circuit 125 for transmitting a third bias signal to the gate of the transistors included in the second cascaded transistor module M20. The third bias circuit 125 includes a bias transistor, and the bias transistor and the transistors included in the second cascaded transistor module M20 form a current mirror structure. The main function of the current mirror structure is to accurately mirror the current.
[0088] For example, the second cascaded transistor module M20 includes a first bipolar junction transistor M5; the third bias circuit 125 includes a second bipolar junction transistor M6, and the second bipolar junction transistor M6 and the first bipolar junction transistor M5 form a current mirror structure.
[0089] By using a current mirror structure of a bipolar junction transistor for biasing, it can be equivalent to an ideal current source with a large output impedance. Therefore, even if the VCE of the first bipolar junction transistor M5 changes greatly, its current change is not significant, and it has almost no effect on the voltage across the second transistor M2. Thus, when the output reaches its minimum value, the second transistor M2 can still fall well in the saturation region, resulting in good linearity.
[0090] Optionally, the third bias circuit 125 is connected between the second power supply node and the ground terminal. In this way, the bias of the second cascaded transistor module M20 is set to a fixed voltage, the reason for which depends on actual requirements. Taking the second cascaded transistor module M20 and the second transistor M2 vertically cascaded in the pull-down current path as an example, in practical applications, it is not necessary for the output voltage to be closer to the negative power rail. Therefore, sufficient margin is left for the second cascaded transistor module M20, and the third bias circuit 125 of the second cascaded transistor module M20 does not follow the output voltage change.
[0091] Please continue to refer to this. Figure 4 For example, the third bias circuit 125 may further include: a fifth resistor R5 connected between the ground terminal and the collector of the second bipolar junction transistor M6; the second bipolar junction transistor M6 is an NPN bipolar junction transistor, and the base and collector of the second bipolar junction transistor M6 are shorted; and a sixth resistor R6 connected between the emitter of the second bipolar junction transistor M6 and the second power supply node.
[0092] Optionally, the first bias circuit 123, the second bias circuit 124, and the third bias circuit 125 are all different. Specifically, three different bias generation circuits are used in the output stage circuit 120, and these three bias generation circuits are implemented in three different ways.
[0093] As an optional implementation, corresponding to the first cascaded transistor module M10 and the first transistor M1, which are vertically cascaded in the pull-up current path, the third transistor M3, the fourth transistor M4, and the first transistor M1 have the same device structure and voltage rating. For example, the third transistor M3, the fourth transistor M4, and the first transistor M1 are all PMOS transistors, and their voltage ratings are all the same. It is understood that the third transistor M3, the fourth transistor M4, and the first transistor M1 can be completely identical transistors.
[0094] Furthermore, corresponding to the first cascaded transistor module M10 and the second transistor M2 being vertically cascaded in the pull-down current path, the device structures and voltage ratings of the third transistor M3, the fourth transistor M4, and the second transistor M2 are identical. For example, the third transistor M3, the fourth transistor M4, and the second transistor M2 are all NMOS transistors, and their voltage ratings are all the same. It is understandable that the third transistor M3, the fourth transistor M4, and the second transistor M2 can be completely identical transistors.
[0095] Based on this, the present application also provides an operational amplifier 100, which includes: an input stage circuit 110 for providing a differential voltage signal, and an output stage circuit 120 as described in any of the foregoing embodiments.
[0096] The operational amplifier 100 provided in this application embodiment can be applied to an oscilloscope analog front-end chip.
[0097] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of the present invention that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of the present invention and do not limit the scope of protection of this patent.
Claims
1. An output stage circuit used in an operational amplifier, characterized in that, include: A first input terminal and a second input terminal are used for connection with the input stage circuit; the input stage circuit and the output stage circuit are used together in the operational amplifier, and the input stage circuit is used to provide differential voltage signals to the first input terminal and the second input terminal; The output terminal used to provide the output signal; First power node for connecting to the first power source; A second power node for connecting a second power source; wherein, the power supply voltage exists between the first power node and the second power node; A first transistor is connected in a pull-up current path; wherein the pull-up current path extends from the first power node to the output terminal; the gate of the first transistor is connected to the first input terminal; A second transistor is connected in a pull-down current path; wherein the pull-down current path extends from the output terminal to the second power supply node; the gate of the second transistor is connected to the second input terminal; A cascaded transistor module is cascaded perpendicularly to the first transistor in the pull-up current path, and / or cascaded perpendicularly to the second transistor in the pull-down current path.
2. The output stage circuit according to claim 1, characterized in that, The cascaded transistor module includes a first cascaded transistor module, which includes at least a third transistor and a fourth transistor.
3. The output stage circuit according to claim 2, characterized in that, Also includes: A first bias circuit is used to transmit a first bias signal to the gate of the third transistor, and the first bias circuit is connected between the power supply voltage and the ground terminal.
4. The output stage circuit according to claim 3, characterized in that, The first cascaded transistor module is vertically cascaded with the first transistor in the pull-up current path; The source of the third transistor is connected to the drain of the first transistor; The first bias circuit is connected between the power supply voltage and the ground terminal, including: one end of the first bias circuit is connected to the third power supply node, and the other end of the first bias circuit is connected to the ground terminal; The third power node is independent of the first power node.
5. The output stage circuit according to claim 2 or 3, characterized in that, Also includes: A second bias circuit is used to transmit a second bias signal to the gate of the fourth transistor, and the second bias circuit is connected between the output terminal and the ground terminal.
6. The output stage circuit according to claim 2, characterized in that, The first cascaded transistor module is vertically cascaded with the first transistor in the pull-up current path; The cascaded transistor module further includes: a second cascaded transistor module, which is cascaded perpendicularly to the second transistor in the pull-down current path; the second cascaded transistor module is different from the first cascaded transistor module.
7. The output stage circuit according to claim 6, characterized in that, The second cascaded transistor module includes bipolar junction transistors.
8. The output stage circuit according to claim 6 or 7, characterized in that, Also includes: A third bias circuit is used to transmit a third bias signal to the gate of the transistor included in the second cascaded transistor module. The third bias circuit includes a bias transistor, which, together with the transistor included in the second cascaded transistor module, forms a current mirror structure.
9. The output stage circuit according to claim 6 or 7, characterized in that, Also includes: A third bias circuit is used to transmit a third bias signal to the gate of the transistor included in the second cascaded transistor module, the third bias circuit being connected between the second power supply node and the ground terminal.
10. The output stage circuit according to claim 2, characterized in that, Corresponding to the first cascaded transistor module being vertically cascaded with the first transistor in the pull-up current path, the device structure and withstand voltage of the third transistor, the fourth transistor, and the first transistor are all the same; Corresponding to the first cascaded transistor module and the second transistor being vertically cascaded in the pull-down current path, the third transistor, the fourth transistor, and the second transistor have the same device structure and withstand voltage.
11. The output stage circuit according to claim 1, characterized in that, The cascaded transistor module includes a second cascaded transistor module, which includes a bipolar junction transistor.
12. The output stage circuit according to claim 11, characterized in that, The cascaded transistor module further includes: a first cascaded transistor module, wherein the first cascaded transistor module includes a MOS transistor; The second cascaded transistor module is vertically cascaded in one of the pull-up current path and the pull-down current path, and the first cascaded transistor module is vertically cascaded in the other of the pull-up current path and the pull-down current path.
13. The output stage circuit according to claim 12, characterized in that, The bipolar junction transistor included in the second cascaded transistor module has a higher voltage rating than the MOS transistor included in the first cascaded transistor module.
14. The output stage circuit according to claim 13, characterized in that, The number of MOS transistors included in the first cascaded transistor module is greater than the number of bipolar junction transistors included in the second cascaded transistor module.
15. The output stage circuit according to claim 11, characterized in that, The second cascaded transistor module includes a first bipolar junction transistor; The output stage circuit further includes a third bias circuit for transmitting a third bias signal to the gate of the first bipolar junction transistor. The third bias circuit includes a second bipolar junction transistor, and the second bipolar junction transistor and the first bipolar junction transistor form a current mirror structure.
16. The output stage circuit according to claim 15, characterized in that, The third bias circuit is connected between the second power node and the ground terminal.
17. The output stage circuit according to claim 16, characterized in that, The third bias circuit also includes: The fifth resistor is connected between the ground terminal and the collector of the second bipolar junction transistor; the second bipolar junction transistor is an NPN bipolar junction transistor, and the base and collector of the second bipolar junction transistor are shorted. The sixth resistor is connected between the emitter of the second bipolar junction transistor and the second power supply node.
18. An operational amplifier, characterized in that, include: An input stage circuit for providing a differential voltage signal, and an output stage circuit as described in any one of claims 1-17.