Level conversion circuit, voltage measurement device, and voltage measurement method

Abstract

A level conversion circuit, a voltage measurement device and a voltage measurement method. The level conversion circuit comprises a current mirror circuit unit, an output circuit unit, a voltage dividing circuit unit, an output terminal and an input terminal, the input terminal is used for receiving an input voltage, the output terminal is used for providing an output voltage, the current mirror circuit unit comprises a first terminal connected with a first power supply voltage, a second terminal connected with the output terminal and a third terminal connected with the voltage dividing circuit unit, the current mirror circuit unit is configured to provide a mirror current at the second terminal and the third terminal, the output circuit unit is connected between a second power supply voltage and the output terminal and receives the input voltage from the input terminal, the output circuit unit is configured to provide the output voltage at the output terminal under the control of the input voltage and based on the control of the second power supply voltage, and the voltage dividing circuit is connected between the second power supply voltage and the third terminal of the current mirror circuit unit. The method can improve the precision of level conversion.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a level conversion circuit, a voltage measuring device, and a voltage measuring method. Background Technology

[0002] With the continuous development of semiconductor technology, chips integrate multiple circuit modules, each with multiple voltage domains. To meet the level requirements of these multiple circuit modules, level conversion is often necessary. Furthermore, to ensure the chip operates normally, it is essential to monitor the voltages of various critical nodes within the chip. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a level conversion circuit, including: a current mirror circuit unit, an output circuit unit, a voltage divider circuit unit, an output terminal, and an input terminal. The input terminal is used to receive an input voltage, and the output terminal is used to provide an output voltage. The current mirror circuit unit includes a first terminal connected to a first power supply voltage, a second terminal connected to the output terminal, and a third terminal connected to the voltage divider circuit unit. The current mirror circuit unit is configured to provide a mirrored current at the second terminal and the third terminal. The output circuit unit is connected between a second power supply voltage and the output terminal and receives the input voltage from the input terminal. The output circuit unit is configured to provide an output voltage at the output terminal based on the control of the second power supply voltage under the control of the input voltage. The voltage divider circuit voltage is connected between the second power supply voltage and the third terminal of the current mirror circuit unit.

[0004] For example, in a level conversion circuit provided in an embodiment of this disclosure, the current mirror circuit unit includes a first transistor and a second transistor. The gate of the first transistor is connected to the gate of the second transistor. The gate of the first transistor is connected to the first terminal of the first transistor and they are both connected to the voltage divider circuit unit. The second terminal of the first transistor is connected to the first terminal. The second terminal of the second transistor is connected to the first terminal. The first terminal of the second transistor is connected to the second terminal. The first transistor and the second transistor have the same specifications.

[0005] For example, in a level conversion circuit provided in an embodiment of this disclosure, the output circuit unit includes a third transistor, the gate of which is connected to the input terminal to receive the input voltage, the second terminal of which is connected to the output terminal, and the first terminal of which is connected to the second power supply voltage.

[0006] For example, in a level conversion circuit provided in an embodiment of this disclosure, the voltage divider circuit unit includes a fourth transistor, the gate of the fourth transistor and the first terminal of the fourth transistor are connected to the second power supply voltage, and the second terminal of the fourth transistor is connected to the third terminal of the current mirror circuit unit.

[0007] For example, in a level conversion circuit provided in one embodiment of this disclosure, the first transistor and the fourth transistor have the same specifications.

[0008] For example, in a level conversion circuit provided in one embodiment of this disclosure, a reference voltage generation unit is further included, configured to provide a reference voltage, wherein one of a first power supply voltage and a second power supply voltage is the reference voltage.

[0009] For example, in a level conversion circuit provided in one embodiment of this disclosure, the reference voltage generation unit includes a bandgap voltage reference circuit, wherein the bandgap voltage reference circuit provides the reference voltage.

[0010] For example, in a level conversion circuit provided in an embodiment of this disclosure, the reference voltage generation unit further includes a unity-gain buffer, wherein the first end of the unity-gain buffer is connected to the bandgap voltage reference circuit, and the second end of the unity-gain buffer is connected to the first end of the current mirror circuit unit.

[0011] For example, in a level conversion circuit provided in an embodiment of this disclosure, the first power supply voltage is the reference voltage, and the current mirror circuit unit, the output circuit unit and the voltage divider circuit unit each include at least one transistor, and each of the at least one transistor is a P-type metal-oxide-semiconductor field-effect transistor.

[0012] For example, in a level conversion circuit provided in an embodiment of this disclosure, the second power supply voltage is the reference voltage, and the current mirror circuit unit, the output circuit unit, and the voltage divider circuit unit each include at least one transistor, and each of the at least one transistor is an N-type metal-oxide-semiconductor field-effect transistor.

[0013] At least one embodiment of this disclosure provides a voltage measuring device, including: a voltage measurement generation unit and a signal processing unit. The voltage measurement generation unit includes a level conversion circuit, an input voltage receiving terminal, and a voltage measurement output terminal as described in any of the above embodiments. The input voltage receiving terminal is used to receive an input voltage from an input voltage signal terminal. The voltage measurement output terminal is connected to the signal processing unit. The level conversion circuit is connected to the input voltage receiving terminal and configured to receive the input voltage and provide an output voltage to the voltage measurement output terminal. The signal processing unit includes a first signal receiving terminal and a second signal receiving terminal. The first signal receiving terminal is connected to the voltage measurement output terminal to receive the output voltage. The second signal receiving terminal is used to receive a reference voltage. The signal processing unit is configured to output a measurement result of the output voltage based on the reference voltage.

[0014] For example, in a voltage measuring device provided in an embodiment of this disclosure, the voltage measurement generation unit includes a first level conversion circuit and a second level conversion circuit. The voltage measurement generation unit also includes a first switch unit, a second switch unit, and a third switch unit. The first level conversion circuit is connected to the voltage measurement output terminal through the first switch unit, and the second level conversion circuit is connected to the voltage measurement output terminal through the second switch unit. The voltage measurement output terminal is also connected to the input voltage signal terminal through the third switch unit. The first level conversion circuit and the second level conversion circuit also receive the reference voltage. The first power supply voltage connected to the first level conversion circuit is the reference voltage, and the second power supply voltage connected to the second level conversion circuit is the reference voltage.

[0015] For example, in a voltage measuring device provided in one embodiment of this disclosure, a first switching unit, a second switching unit, and a third switching unit are configured to respond to a control signal. When the input voltage is within the voltage measurement range of the signal processing unit, the control signal controls the first switching unit to disconnect the measured voltage output terminal from the first level conversion circuit, the second switching unit to disconnect the second level conversion circuit from the measured voltage output terminal, and the third switching unit to connect the input voltage signal terminal to the measured voltage output terminal. When the input voltage is less than the minimum value of the voltage measurement range of the signal processing unit, the control signal controls the first switching unit to connect the measured voltage output terminal to the first level conversion circuit, the second switching unit to disconnect the second level conversion circuit from the measured voltage output terminal, and the third switching unit to disconnect the input voltage signal terminal from the measured voltage output terminal. When the input voltage is greater than the maximum value of the voltage measurement range of the signal processing unit, the control signal controls the first switching unit to disconnect the measured voltage output terminal from the first level conversion circuit, the second switching unit to connect the second level conversion circuit to the measured voltage output terminal, and the third switching unit to disconnect the input voltage signal terminal from the measured voltage output terminal.

[0016] For example, in a voltage measuring device provided in one embodiment of this disclosure, the signal processing unit includes a digital-to-analog converter.

[0017] At least one embodiment of this disclosure provides a voltage measurement method applied to the voltage measurement device provided in the above embodiments. The voltage measurement method includes: in response to receiving an input voltage at an input voltage receiving terminal, comparing the input voltage with the voltage measurement range of the signal processing unit to obtain a comparison result; generating the control signal based on the comparison result; controlling the opening or closing of the first switching unit, the second switching unit, and the third switching unit according to the control signal; and measuring the output voltage provided by the measurement voltage output terminal by the signal processing unit and outputting the measurement result. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1 A block diagram of a level conversion circuit provided in at least one embodiment of the present disclosure is shown;

[0020] Figure 2 The circuit structure of a level conversion circuit provided in at least one embodiment of the present disclosure is shown;

[0021] Figure 3 The circuit structure of a level conversion circuit provided in at least one embodiment of the present disclosure is shown;

[0022] Figure 4 A schematic block diagram of a voltage measuring device provided in at least one embodiment of the present disclosure is shown;

[0023] Figure 5 A schematic diagram of the circuit structure of a voltage measuring device provided in at least one embodiment of this disclosure is shown; and

[0024] Figure 6 A flowchart of a voltage measurement method provided by at least one embodiment of the present disclosure is shown. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0027] In a chip, multiple circuit modules often operate at different voltage domains. For example, when these modules communicate via a bus, some may use a 3V voltage domain while others use a 5V voltage domain. Level shifting circuits can switch between high and low voltage levels, enabling better communication between these modules. Furthermore, level shifting circuits can also perform impedance conversion and even provide isolation and filtering. Therefore, level shifting units play a crucial role in chips. However, due to factors such as temperature, power supply voltage, and manufacturing process errors, the conversion accuracy of level shifting units is relatively low.

[0028] At least one embodiment of this disclosure provides a level conversion circuit, a voltage measuring device, and a voltage measuring method. The level conversion circuit method includes: a current mirror circuit unit, an output circuit unit, a voltage divider circuit unit, an output terminal, and an input terminal. The input terminal is used to receive an input voltage, and the output terminal is used to provide an output voltage. The current mirror circuit unit includes a first terminal connected to a first power supply voltage, a second terminal connected to the output terminal, and a third terminal connected to the voltage divider circuit unit. The current mirror circuit unit is configured to provide a mirrored current at the second and third terminals. The output circuit unit is connected between a second power supply voltage and the output terminal and receives the input voltage from the input terminal. The output circuit unit is configured to provide an output voltage at the output terminal based on the control of the second power supply voltage under the control of the input voltage. The voltage divider circuit voltage is connected between the second power supply voltage and the third terminal of the current mirror circuit unit. This method can improve the accuracy of level conversion.

[0029] At least one embodiment of this disclosure provides a voltage measuring device, including: a voltage measurement generation unit and a signal processing unit. The voltage measurement generation unit includes a level conversion circuit, an input voltage receiving terminal, and a voltage measurement output terminal, as described in any of the above embodiments. The input voltage receiving terminal receives an input voltage from an input voltage signal terminal. The voltage measurement output terminal is connected to the signal processing unit. The level conversion circuit is connected to the input voltage receiving terminal and configured to receive the input voltage and provide an output voltage to the voltage measurement output terminal. The signal processing unit includes a first signal receiving terminal and a second signal receiving terminal. The first signal receiving terminal is connected to the voltage measurement output terminal to receive the output voltage. The second signal receiving terminal receives a reference voltage. The signal processing unit is configured to output a measurement result of the output voltage based on the reference voltage. This voltage measuring device can improve the voltage measurement range of the signal processing unit.

[0030] Figure 1 A block diagram of a level conversion circuit 100 provided in at least one embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, the level conversion circuit 100 includes a current mirror circuit unit 101, a voltage divider circuit unit 102, an output circuit unit 103, an output terminal Pout, and an input terminal Pin.

[0032] The input terminal Pin is used to receive the input voltage Vin, and the output terminal Pout is used to provide the output voltage Vout.

[0033] The current mirror circuit unit 101 includes a first terminal P1 connected to the first power supply voltage V1, a second terminal P2 connected to the output terminal Pout, and a third terminal P3 connected to the voltage divider circuit unit 102. The current mirror circuit unit 101 is configured to provide a mirrored current to the second terminal P2 and the third terminal P3.

[0034] Voltage divider circuit 102 is connected between the second power supply voltage V2 and the third terminal P3 of current mirror circuit unit 101.

[0035] Output circuit unit 103 is connected between the second power supply voltage V2 and the output terminal Pout, and receives the input voltage Vin from the input terminal Pin. Output circuit unit 103 is configured to provide an output voltage Vout at the output terminal Pout under the control of the second power supply voltage V2, controlled by the input voltage Vin.

[0036] The level conversion circuit mirrors the current through a current mirror circuit unit, making the current flowing through the voltage divider circuit unit 102 and the output circuit unit 103 the same, thereby reducing the influence of errors such as temperature and process, and effectively improving the level conversion accuracy.

[0037] Figure 2The circuit structure 200 of a level conversion circuit 100 provided in at least one embodiment of the present disclosure is shown.

[0038] like Figure 2 As shown, in circuit structure 200, the current mirror circuit unit 101 includes a first transistor M1 and a second transistor M2. The first transistor M1 and the second transistor M2 have the same specifications.

[0039] In the embodiments disclosed herein, "same specifications" refers to two transistors having identical physical parameters such as channel aspect ratio and threshold voltage. For example, the two transistors can be the same type of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For example, the first transistor M1 and the second transistor M2 have identical physical parameters such as channel aspect ratio and threshold voltage. For example, the first transistor M1 and the second transistor M2 can both be P-type MOSFETs (hereinafter referred to as P-type transistors) or N-type MOSFETs (hereinafter referred to as N-type transistors).

[0040] like Figure 2 As shown, in circuit structure 200, the gate of the first transistor M1 is connected to the gate of the second transistor M2. The gate M1 of the first transistor and its first terminal are connected and jointly connected to the voltage divider circuit unit 102. The second terminal of the first transistor M1 is connected to its first terminal P1. The second terminal of the second transistor M2 is connected to its first terminal P1, and its first terminal and second terminal P2 are connected. The first terminal P1 is connected to the first power supply voltage V1.

[0041] For example, the first transistor M1 is a P-type transistor, with its first electrode being the drain and its second electrode being the source. Figure 2 As shown, the gate and drain of the P-type transistor are connected together to form a diode. After the gate and drain of the P-type transistor are connected together, they are connected to the voltage divider circuit unit 102 through the third terminal. The source of the P-type transistor is connected to the first terminal P1.

[0042] The gate and drain of the first transistor M1 are connected together, and the gate of the first transistor M1 is connected together with the gate of the second transistor M2, forming a current mirror structure.

[0043] In some embodiments of this disclosure, the second transistor M2 has the same specifications as the first transistor M1; therefore, if the first transistor is a P-type transistor, then the second transistor M2 is also a P-type transistor. If the second transistor M2 is a P-type transistor, then the first electrode of the second transistor M2 is the drain of the P-type transistor, and the second electrode of the second transistor M2 is the source of the P-type transistor. Figure 2 As shown, the source of the second transistor M2 is connected to the first terminal P1, and the drain of the second transistor M2 is connected to the output terminal Pout through the second terminal P2.

[0044] In some embodiments of this disclosure, the output circuit unit 103 may include a third transistor M3. The gate of the third transistor M3 is connected to the input terminal Pin to receive the input voltage Vin, the second terminal of the third transistor M3 is connected to the output terminal Pout, and the first terminal of the third transistor M3 is connected to the second power supply voltage V2.

[0045] In some embodiments of this disclosure, the third transistor M3 can be either a P-type transistor or an N-type transistor.

[0046] In some embodiments of this disclosure, such as Figure 2 As shown, the voltage divider circuit unit 102 includes a fourth transistor M4. The gate of the fourth transistor M4 and the first terminal of the fourth transistor M4 are connected to the second power supply voltage V2, and the second terminal of the fourth transistor M4 is connected to the third terminal P3 of the current mirror circuit unit 101.

[0047] The gate of the fourth transistor M4 is connected to the first terminal of the fourth transistor M4, so that the fourth transistor M4 also forms a diode, the same as the first transistor M1. This reduces the influence of temperature, process and other factors on the voltage division between the first transistor M1 and the fourth transistor M4, thus providing level conversion accuracy.

[0048] In some embodiments of this disclosure, the first transistor M1 and the fourth transistor M4 have the same specifications. Please refer to the description above for the meaning of "same specifications". Having the same specifications for the first transistor M1 and the fourth transistor M4 ensures that the voltage drop across them is the same, thereby reducing the influence of temperature, process, etc., and improving the accuracy of level conversion.

[0049] exist Figure 2 In the example shown, if the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M3 are all P-type transistors, then the second power supply voltage V2 is less than the first power supply voltage V1, so that the current direction is from the first terminal P1 to the node P4.

[0050] For example, the second power supply voltage can be grounded.

[0051] In some embodiments of this disclosure, such as Figure 1 As shown, the level conversion circuit 100 may further include a reference voltage generation unit 104. The reference voltage generation unit 104 is configured to provide a reference voltage Vref, wherein one of the first power supply voltage V1 and the second power supply voltage V2 is the reference voltage.

[0052] exist Figure 1 and Figure 2 In the example, the first power supply voltage V1 is the reference voltage Vref. In other embodiments of this disclosure, the second power supply voltage is used as the reference voltage Vref; please refer to [reference needed]. Figure 3 Examples.

[0053] For example, in Figure 2 The circuit structure 200 shown may include a reference voltage generation unit 104 in addition to the current mirror circuit unit 101, the output circuit unit 103, and the voltage divider circuit unit 102. The reference voltage generation unit 104 provides a reference voltage Vref, that is, the first terminal P1 receives the reference voltage Vref from the reference voltage generation unit 104.

[0054] like Figure 2 As shown, the reference voltage generation unit 104 includes a bandgap voltage reference circuit BG_vref. The bandgap voltage reference circuit BG_vref provides a reference voltage Vref. The reference voltage generated by the bandgap voltage reference circuit BG_vref does not change with subsequent circuits (i.e., current mirror circuit unit 101, output circuit unit 103, and voltage divider circuit unit 102), thereby providing a highly stable and accurate reference voltage Vref.

[0055] like Figure 2 As shown, the bandgap voltage reference circuit BG_vref is connected to the power supply voltage Vdd to receive the power supply voltage Vdd and provide a reference voltage Vref. Using the bandgap voltage reference circuit BG_vref to provide the reference voltage Vref can reduce the error caused by the power supply voltage, because the reference voltage Vref provided by the bandgap voltage reference circuit BG_vref is a parameter that does not change with temperature, process, or power supply voltage.

[0056] like Figure 2 As shown, the reference voltage generation unit 104 also includes a unity-gain buffer 114. The first terminal of the unity-gain buffer 114 is connected to the bandgap voltage reference circuit BG_vref, and the second terminal of the unity-gain buffer 114 is connected to the first terminal P1 of the current mirror circuit unit 101.

[0057] The unity-gain buffer 114 receives the reference voltage Vref provided by the bandgap voltage reference circuit BG_vref and provides the reference voltage Vref to the current mirror circuit unit 101.

[0058] The unity-gain buffer 114 can isolate the bandgap voltage reference circuit BG_vref from subsequent circuits, thereby further ensuring that the bandgap voltage reference circuit BG_vref provides a highly stable and accurate reference voltage Vref.

[0059] like Figure 2 As shown, for example, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all identical P-type transistors. The first transistor M1 and the fourth transistor M4 are connected in the form of diodes. The first transistor M1 and the fourth transistor M4 form a voltage divider, therefore Vref = Vgs1 + Vgs4. Vgs1 and Vgs4 represent the gate-source voltages of the first transistor M1 and the fourth transistor M4, respectively.

[0060] Since the first transistor M1 and the fourth transistor M4 have the same specifications, Vgs1 = Vgs4 = Vref / 2.

[0061] The first transistor M1 and the second transistor M2 mirror the currents, therefore Id1 = Id2, Vgs2 = Vgs1, and Vgs2 = Vgs3. Id1 and Id2 represent the currents flowing through the first transistor M1 and the second transistor M2, respectively. Vgs2 represents the gate-source voltage of the second transistor M2, and Vgs3 represents the gate-source voltage of the third transistor M3. This ensures that Vin and Vout differ by the gate-source voltage of the third transistor M3, therefore Vout = Vin + Vgs3 = Vin + Vref / 2.

[0062] Therefore, Vout is only related to the reference voltage Vref and the input Vin, eliminating the influence of errors caused by temperature, process, etc., and effectively improving the level conversion accuracy. Furthermore, in Figure 2 In the circuit structure 200, the output voltage Vout is greater than the input voltage Vin. Therefore, the circuit structure 200 plays a role in boosting the voltage.

[0063] In some embodiments of this disclosure, the second power supply voltage V2 is a reference voltage Vref, and the current mirror circuit unit 101, the output circuit unit 103, and the voltage divider circuit unit 102 each include at least one transistor, and each of the at least one transistor can be an N-type metal-oxide-semiconductor field-effect transistor.

[0064] Figure 3 The circuit structure 300 of a level conversion circuit 100 provided in at least one embodiment of the present disclosure is shown.

[0065] like Figure 3 As shown, in circuit structure 300, the current mirror circuit unit 101 includes a first transistor M'1 and a second transistor M'2. The first transistor M'1 and the second transistor M'2 have the same specifications.

[0066] The gate of the first transistor M'1 is connected to the gate of the second transistor M'2. The gate M'1 of the first transistor is connected to its first terminal and is also connected to the voltage divider circuit unit 102. The second terminal of the first transistor M'1 is connected to its first terminal P1. The second terminal of the second transistor M'2 is connected to its first terminal P1, and its first terminal and second terminal P2 are connected. The first terminal P1 is connected to the first power supply voltage V'1.

[0067] For example, the first transistor M'1 is an N-type transistor, with its first electrode being the drain and its second electrode being the source. Figure 3 As shown, the gate and drain of the N-type transistor are connected together to form a diode. After the gate and drain of the N-type transistor are connected together, they are connected to the voltage divider circuit unit 102 through the third terminal. The source of the N-type transistor is connected to the first terminal P1.

[0068] The gate and drain of the first transistor M'1 are connected together, and the gate of the first transistor M'1 is connected together with the gate of the second transistor M'2, forming a current mirror structure.

[0069] In some embodiments of this disclosure, the second transistor M'2 has the same specifications as the first transistor M'1; therefore, if the first transistor M'1 is an N-type transistor, then the second transistor M'2 is also an N-type transistor. Figure 2 As shown, the source of the second transistor M'2 is connected to the first terminal P1, and the drain of the second transistor M'2 is connected to the output terminal P'out through the second terminal P2.

[0070] In some embodiments of this disclosure, the output circuit unit 103 may include a third transistor M'3. The gate of the third transistor M'3 is connected to the input terminal P'in to receive the input voltage Vin, the second terminal of the third transistor M'3 is connected to the output terminal P'out, and the first terminal of the third transistor M'3 is connected to the second power supply voltage V'2.

[0071] exist Figure 3 In the example, the third transistor M'3 is an N-type transistor.

[0072] In some embodiments of this disclosure, such as Figure 3 As shown, the voltage divider circuit unit 102 includes a fourth transistor M'4. The gate of the fourth transistor M'4 and the first terminal of the fourth transistor M'4 are connected to the second power supply voltage V'2, and the second terminal of the fourth transistor M'4 is connected to the third terminal P3 of the current mirror circuit unit 101.

[0073] The gate of the fourth transistor M'4 is connected to the first terminal of the fourth transistor M'4, so that the fourth transistor M'4 also forms a diode, the same as the first transistor M'1. This reduces the influence of temperature, process and other factors on the voltage division between the first transistor M'1 and the fourth transistor M'4, thus providing level conversion accuracy.

[0074] In some embodiments of this disclosure, the first transistor M'1 and the fourth transistor M'4 have the same specifications. Having the same specifications for the first transistor M'1 and the fourth transistor M'4 ensures that the voltage drop across them is the same, thereby reducing the influence of temperature, process, etc., and improving the accuracy of level conversion.

[0075] exist Figure 3 In the example shown, if the first transistor M'1, the second transistor M'2, the third transistor M'3, and the fourth transistor M'3 are all N-type transistors, then the second power supply voltage V'2 is greater than the first power supply voltage V'1, so that the current direction is from node P'4 to the first terminal P1.

[0076] For example, the first power supply voltage V'1 can be grounded.

[0077] like Figure 3 As shown, in addition to the current mirror circuit unit 101, the output circuit unit 103, and the voltage divider circuit unit 102, the circuit structure 300 may also include a reference voltage generation unit 104. The reference voltage generation unit 104 is configured to provide a reference voltage Vref, and the second power supply voltage V'2 is the reference voltage Vref.

[0078] For example, in Figure 3 As shown, the reference voltage generation unit 104 provides the reference voltage Vref, that is, node P'4 receives the reference voltage Vref from the reference voltage generation unit 104.

[0079] exist Figure 3 In the example, except that the reference voltage generation unit 104 provides the reference voltage Vref to node P4, the other features are the same as... Figure 2 The reference voltage generation unit 104 in the circuit structure is the same; please refer to the above. Figure 2 Description of circuit structure 200.

[0080] like Figure 2As shown, for example, the first transistor M'1, the second transistor M'2, the third transistor M'3, and the fourth transistor M'4 are all identical N-type transistors. The first transistor M'1 and the fourth transistor M'4 are connected in the form of diodes. The first transistor M'1 and the fourth transistor M'4 form a voltage divider, therefore Vref = Vgs'1 + Vgs'4. Vgs'1 and Vgs'4 represent the gate-source voltages of the first transistor M'1 and the fourth transistor M'4, respectively.

[0081] Since the first transistor M'1 and the fourth transistor M'4 have the same specifications, Vgs'1 = Vgs'4 = Vref / 2.

[0082] The first transistor M'1 and the second transistor M'2 mirror the currents, therefore Id'1 = Id'2, Vgs'2 = Vgs'1, and Vgs'2 = Vgs'3. Id'1 and Id'2 represent the currents flowing through the first transistor M'1 and the second transistor M'2, respectively. Vgs'2 represents the gate-source voltage of the second transistor M'2, and Vgs'3 represents the gate-source voltage of the second transistor M'3. This ensures that Vin and Vout differ by the gate-source voltage of the third transistor M'3, therefore Vout = Vin - Vgs'3 = Vin - Vref / 2.

[0083] Therefore, Vout is only related to the reference voltage Vref and the input Vin, eliminating the influence of errors caused by temperature, process, etc., and effectively improving the level conversion accuracy. Furthermore, in Figure 3 In the circuit structure 300, the output voltage Vout is less than the input voltage Vin. Therefore, the circuit structure 300 plays a role in voltage reduction.

[0084] Figure 2 and Figure 3 Examples of circuit structures for boost level conversion circuits and buck level conversion circuits are provided. It should be understood that this disclosure does not limit the boost level conversion circuit to... Figure 2 The circuit structure and buck level conversion circuit shown are as follows: Figure 3 The circuit structure shown is illustrated. For example, the multiple transistors in a boost level conversion circuit can be N-type and P-type transistors, or all of them can be N-type transistors, and do not necessarily have to be... Figure 2 The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 shown are all P-type transistors. Using transistors of the same specification for the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can eliminate the influence of errors such as temperature and process, and effectively improve the level conversion accuracy.

[0085] Another aspect of this disclosure provides a voltage measuring device. Figure 4A schematic block diagram of a voltage measuring device 400 provided in at least one embodiment of the present disclosure is shown.

[0086] like Figure 4 As shown, the voltage measuring device 400 includes a voltage generation unit 401 and a signal processing unit 402.

[0087] The voltage measurement generation unit 401 includes a level conversion circuit 411, an input voltage receiving terminal In1, and a voltage measurement output terminal Out1 provided in any of the foregoing embodiments. For example, the level conversion circuit 411 may be... Figure 2 The level conversion circuit shown and / or Figure 3 The level conversion circuit shown.

[0088] The input voltage receiving terminal In1 is used to receive the input voltage Vin from the input voltage signal terminal In2, and the measured voltage output terminal Out1 is connected to the signal processing unit 402.

[0089] The level conversion circuit 411 is connected to the input voltage receiving terminal In1 and configured to receive the input voltage Vin. The level conversion circuit 411 is also connected to the measurement voltage output terminal Out1 to provide the output voltage Vout to the measurement voltage output terminal Out1.

[0090] The signal processing unit 402 includes a first signal receiving terminal 412 and a second signal receiving terminal 422. The first signal receiving terminal 412 is connected to the measured voltage output terminal Out1 to receive the output voltage Vout. The second signal receiving terminal 422 is used to receive a reference voltage Vref. The signal processing unit 402 is configured to output the measurement result of the output voltage Vout based on the reference voltage Vref.

[0091] For example, the bandgap voltage reference circuit BG_vref provides a reference voltage Vref to the signal processing unit 402.

[0092] The voltage measuring device includes a level conversion circuit 411. Therefore, when the input voltage Vin is outside the voltage measurement range of the signal processing unit, the level conversion circuit 411 can be used to convert the input voltage Vin into an output voltage Vout that is within the voltage measurement range. The signal processing unit then measures the output voltage Vout to obtain the measurement result, and subsequently, the measurement result of the input voltage Vin. Thus, this voltage measuring device can improve the voltage measurement range of the signal processing unit.

[0093] For example, the voltage measurement range of the signal processing unit 402 is [a, b], when the level conversion circuit 411 is Figure 2In the level conversion circuit shown, level conversion circuit 411 can boost the input voltage, so that voltage measuring device 400 can use signal processing unit 402 to measure input voltages smaller than the minimum value a in the voltage measurement range. a and b are both greater than 0, for example.

[0094] For example, when the level conversion circuit 411 is Figure 3 When the level conversion circuit shown is used, the level conversion circuit 411 can step down the input voltage, so that the voltage measuring device 400 can use the signal processing unit 402 to measure the input voltage that is greater than the maximum value b in the voltage measurement range.

[0095] like Figure 4 As shown, the bandgap voltage reference circuit BG_vref not only provides a reference voltage Vref to the signal processing unit 402, but also provides a reference voltage to the level conversion circuit 411. For example, the circuit diagram is as follows: Figure 2 For example, the reference voltage Vref is used as the first supply voltage. Another example is the circuit diagram... Figure 3 For example, the reference voltage Vref is used as the second supply voltage.

[0096] Figure 5 A schematic diagram of the circuit structure 500 of a voltage measuring device 400 provided in at least one embodiment of the present disclosure is shown.

[0097] like Figure 5 As shown, in the circuit structure 500, the voltage measurement generation unit 401 includes a first level conversion circuit 501 and a second level conversion circuit 502.

[0098] The voltage measurement generation unit 401 also includes a first switching unit s1, a second switching unit s2, and a third switching unit s3. The first switching unit s1, the second switching unit s2, and the third switching unit s3 can be, for example, a single-pole single-throw switch, a transistor, a MOSFET, etc.

[0099] The first level conversion circuit 501 is connected to the measured voltage output terminal Out1 via the first switching unit s1. The second level conversion circuit 502 is connected to the measured voltage output terminal Out1 via the second switching unit s2. The measured voltage output terminal Out1 is also connected to the input voltage signal terminal In2 via the third switching unit s3.

[0100] The first level conversion circuit 501 and the second level conversion circuit 502 also receive a reference voltage Vref. The first power supply voltage V1 connected to the first level conversion circuit 501 is the reference voltage Vref, and the second power supply voltage V2 connected to the second level conversion circuit 502 is the reference voltage Vref.

[0101] In this embodiment, the first level conversion circuit 501 can be Figure 2 the circuit structure shown. As Figure 2 shown, the first power supply voltage V1 is the reference voltage Vref, and the first level conversion circuit 501 is used to boost the input voltage Vin. The second level conversion circuit 502 can be Figure 3 the circuit structure shown. As Figure 3 shown, the second power supply voltage V'2 is the reference voltage Vref, and the second level conversion circuit 502 is used to step down the input voltage Vin.

[0102] In the circuit structure 500, the first switch unit s1, the second switch unit s2, and the third switch unit s3 are configured to respond to a control signal. The control signal comes from a control device such as a processor, for example.

[0103] In the case where the input voltage Vin is within the voltage measurement range [a, b] of the signal processing unit 402, the control signal is used to control the first switch unit s1 to disconnect the measurement voltage output terminal Out1 from the first level conversion circuit 501, the second switch unit s2 to disconnect the second level conversion circuit 502 from the measurement voltage output terminal Out1, and the third switch unit s3 to connect the input voltage signal terminal In2 to the measurement voltage output terminal Out1.

[0104] For example, the first switch unit s1, the second switch unit s2, and the third switch unit s3 are single-pole single-throw switches. If a < Vin < b, then the first switch unit s1 is disconnected, the second switch unit s2 is disconnected, and the third switch unit s3 is closed.

[0105] For another example, the first switch unit s1, the second switch unit s2, and the third switch unit s3 are MOSFET transistors. If a < Vin < b, then the first switch unit s1 is cut off, the second switch unit s2 is cut off, and the third switch unit s3 is turned on.

[0106] In the case where the input voltage Vin is less than the minimum value a of the voltage measurement range of the signal processing unit 402, the control signal is used to control the first switch unit s1 to connect the measurement voltage output terminal Out1 to the first level conversion circuit 501, the second switch unit s2 to disconnect the second level conversion circuit 502 from the measurement voltage output terminal Out1, and the third switch unit s3 to disconnect the input voltage signal terminal In2 from the measurement voltage output terminal Out1.

[0107] For example, the first switch unit s1, the second switch unit s2, and the third switch unit s3 are single-pole single-throw switches. If Vin < a, then the first switch unit s1 is closed, the second switch unit s2 is disconnected, and the third switch unit s3 is disconnected.

[0108] For another example, the first switching unit s1, the second switching unit s2, and the third switching unit s3 are MOSFET transistors. If Vin < a, the first switching unit s1 is turned on, the second switching unit s2 is turned off, and the third switching unit s3 is turned off.

[0109] In a case where the input voltage Vin is greater than the maximum value b of the voltage measurement range of the signal processing unit 402, the control signal is used to control the first switching unit s1 to disconnect the measurement voltage output terminal Out1 from the first level conversion circuit 501, the second switching unit s2 to connect the second level conversion circuit 502 to the measurement voltage output terminal Out1, and the third switching unit s3 to disconnect the input voltage signal terminal In2 from the measurement voltage output terminal Out1.

[0110] For example, the first switching unit s1, the second switching unit s2, and the third switching unit s3 are single-pole single-throw switches. If Vin > b, the first switching unit s1 is disconnected, the second switching unit s2 is closed, and the third switching unit s3 is disconnected.

[0111] For another example, the first switching unit s1, the second switching unit s2, and the third switching unit s3 are MOSFET transistors. If Vin > b, the first switching unit s1 is turned off, the second switching unit s2 is turned on, and the third switching unit s3 is turned off.

[0112] Figure 5 The illustrated embodiment includes a first level conversion circuit 501 for boosting and a second level conversion voltage 502 for bucking. Thus, by controlling the first switching unit s1, the second switching unit s2, and the third switching unit s3, the input voltage Vin can be boosted, bucked, or left unprocessed, so that the input voltage Vin can be flexibly converted into the voltage measurement range of the signal processing unit 402, improving the voltage measurement range of the voltage measurement device. The voltage measurement device not only increases the measurable voltage range but also solves the error effects introduced by temperature, process, and power supply voltage, effectively ensuring the measurement accuracy and achieving a wider application range.

[0113] In some embodiments of the present disclosure, the signal processing unit 402 may be a mode conversion unit (Analog-to-digital converter, ADC).

[0114] As Figure 5 shown, the voltage measurement device 500 may further include a reference voltage generation unit 403. The reference voltage generation unit 403 provides a reference voltage Vref to the second signal receiving terminal 422. The reference voltage generation unit 403 is similar to the reference voltage generation unit 104 in Figure 2 and Figure 3 , and reference may be made to the above description.

[0115] exist Figure 5 In the example, the reference voltage generation unit 403 provides a reference voltage Vref not only to the second signal receiver 422, but also to the first level conversion circuit 501 and the second level conversion circuit 502. That is, in Figure 5 In the example, the same reference voltage generation unit 403 is used to provide a reference voltage Vref to the second signal receiver 422, the first level conversion circuit 501, and the second level conversion circuit 502. Using the same reference voltage generation unit 403 to provide the reference voltage Vref to the second signal receiver 422, the first level conversion circuit 501, and the second level conversion circuit 502 simplifies the circuit and reduces the cost of the voltage measurement device.

[0116] In other embodiments of this disclosure, the reference voltage generating unit that provides a reference voltage to the second signal receiving terminal 422 may be different from the reference voltage generating unit that provides a reference voltage to the first level conversion circuit 501 and the second level conversion circuit 502.

[0117] For example, the output voltage Vout is compared with the reference voltage signal and Vref by the ADC to obtain a digitized coefficient k, k = Vout / Vref. Therefore, based on k output from the ADC's output terminal Out2 and the reference voltage Vref, the output voltage Vout = k × Vref can be calculated. After obtaining the output voltage Vout, according to Vout = Vin - Vref / 2 or Vout = Vin + Vref / 2, Vin = Vout + Vref / 2 or Vin = Vout - Vref / 2 can be further obtained, thus realizing the measurement of the input voltage Vin.

[0118] Figure 6 A flowchart of a voltage measurement method provided by at least one embodiment of the present disclosure is shown.

[0119] This voltage measurement method is applied to the voltage measurement device provided in any of the above embodiments.

[0120] like Figure 6 As shown, the voltage measurement method may include steps S10 to S40.

[0121] Step S10: In response to receiving the input voltage at the input voltage receiving terminal, compare the input voltage with the voltage measurement range of the signal processing unit to obtain the comparison result.

[0122] Step S20: Generate a control signal based on the comparison result.

[0123] Step S30: Control the disconnection or connection of the first switch unit, the second switch unit, and the third switch unit according to the control signal.

[0124] Step S40: The signal processing unit measures the output voltage and outputs the measurement result.

[0125] This voltage measurement method can generate a control signal based on the comparison result between the input voltage and the voltage measurement range, and then use the control signal to control the generation of an output voltage within the voltage measurement range according to the input voltage, thereby realizing the measurement of the input voltage. This method not only increases the measurable voltage range but also solves the error effects introduced by temperature, process, and power supply voltage, effectively ensuring the measurement accuracy and achieving a wider application range.

[0126] For step S10, for example, in Figure 5 the example of the input voltage receiving terminal In1 receives the input voltage Vin.

[0127] For example, the input voltage Vin is simultaneously sent to a comparator or a processor to use the comparator or the processor to compare the magnitude of the input voltage Vin with the voltage measurement range of the signal processing unit.

[0128] For step S20, for example, the processor generates a control signal for controlling the first switch unit s1, the second switch unit s2, and the third switch unit s3 according to the comparison result.

[0129] For step S30, for example, the voltage measurement range is [a, b]. If a < Vin < b, the first switch unit s1 is disconnected, the second switch unit s2 is disconnected, and the third switch unit s3 is connected. If Vin < a, the first switch unit s1 is connected, the second switch unit s2 is disconnected, and the third switch unit s3 is disconnected. If Vin > b, the first switch unit s1 is disconnected, the second switch unit s2 is connected, and the third switch unit s3 is disconnected.

[0130] For step S40, for example, the ADC measures the output voltage Vout, and the measurement result is output from the output terminal Out2 of the ADC.

[0131] The measurement result is, for example, a digital coefficient k, where k = Vout / Vref. According to the digital coefficient k and the reference voltage Vref, the output voltage Vout = k × Vref can be calculated. After obtaining the output voltage Vout, according to Vout = Vin - Vref / 2 or Vout = Vin + Vref / 2, Vin = Vout + Vref / 2 or Vin = Vout - Vref / 2 can be further obtained, thereby realizing the measurement of the input voltage Vin.

[0132] It should be noted that in the embodiments of this disclosure, each step of the voltage measurement method corresponds to the aforementioned voltage measurement device. For details on the voltage measurement method, please refer to the relevant description of the voltage measurement device, which will not be repeated here.

[0133] The following points need to be explained:

[0134] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0135] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0136] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A level conversion circuit, comprising: The circuit consists of a current mirror unit, an output circuit unit, a voltage divider circuit unit, and output and input terminals. The input terminal is used to receive the input voltage, and the output terminal is used to provide the output voltage. The current mirror circuit unit includes a first terminal connected to a first power supply voltage, a second terminal connected to the output terminal, and a third terminal connected to the voltage divider circuit unit. The current mirror circuit unit is configured to provide a mirrored current at the second terminal and the third terminal. The output circuit unit is connected between the second power supply voltage and the output terminal, and receives the input voltage from the input terminal. The output circuit unit is configured to provide an output voltage at the output terminal based on the control of the second power supply voltage under the control of the input voltage. The voltage divider circuit is connected between the second power supply voltage and the third terminal of the current mirror circuit unit; The current mirror circuit unit includes a first transistor and a second transistor. The gate of the first transistor is connected to the gate of the second transistor, the gate of the first transistor is connected to the first terminal of the first transistor, and both are connected to the voltage divider circuit unit. The second terminal of the first transistor is connected to the first terminal. The second terminal of the second transistor is connected to the first terminal, and the first terminal of the second transistor is connected to the second terminal. The first transistor and the second transistor have the same specifications; The voltage divider circuit unit includes a fourth transistor. The gate of the fourth transistor and the first terminal of the fourth transistor are connected to the second power supply voltage, and the second terminal of the fourth transistor is connected to the third terminal of the current mirror circuit unit.

2. The level conversion circuit according to claim 1, wherein, The output circuit unit includes a third transistor. The gate of the third transistor is connected to the input terminal to receive the input voltage, the second terminal of the third transistor is connected to the output terminal, and the first terminal of the third transistor is connected to the second power supply voltage.

3. The level conversion circuit according to claim 1, wherein, The first transistor and the fourth transistor have the same specifications.

4. The level conversion circuit according to claim 1 further includes: The reference voltage generation unit is configured to provide a reference voltage. Wherein, one of the first power supply voltage and the second power supply voltage is the reference voltage.

5. The level conversion circuit according to claim 4, wherein, The reference voltage generating unit includes a bandgap voltage reference circuit, wherein the bandgap voltage reference circuit provides the reference voltage.

6. The level conversion circuit according to claim 5, wherein, The reference voltage generating unit further includes a unity-gain buffer, wherein the first end of the unity-gain buffer is connected to the bandgap voltage reference circuit, and the second end of the unity-gain buffer is connected to the first end of the current mirror circuit unit.

7. The level conversion circuit according to claim 4, wherein, The first power supply voltage is the reference voltage. The current mirror circuit unit, the output circuit unit, and the voltage divider circuit unit each include at least one transistor, and each of the at least one transistor is a P-type metal-oxide-semiconductor field-effect transistor.

8. The level conversion circuit according to claim 4, wherein, The second power supply voltage is the reference voltage. The current mirror circuit unit, the output circuit unit, and the voltage divider circuit unit each include at least one transistor, and each of the at least one transistor is an N-type metal-oxide-semiconductor field-effect transistor.

9. A voltage measuring device, comprising: Voltage generation unit and signal processing unit. The voltage measurement generation unit includes a level conversion circuit, an input voltage receiving terminal, and a voltage measurement output terminal as described in any one of claims 1 to 8. The input voltage receiving terminal is used to receive the input voltage from the input voltage signal terminal, and the measured voltage output terminal is connected to the signal processing unit. The level conversion circuit is connected to the input voltage receiving terminal and configured to receive the input voltage and provide an output voltage to the measured voltage output terminal. The signal processing unit includes a first signal receiving terminal and a second signal receiving terminal. The first signal receiving terminal is connected to the measured voltage output terminal to receive the output voltage. The second signal receiving terminal is used to receive a reference voltage, and the signal processing unit is configured to output the measurement result of the output voltage based on the reference voltage.

10. The voltage measuring device according to claim 9, wherein, The voltage measurement generation unit includes a first level conversion circuit and a second level conversion circuit. The voltage measurement generation unit further includes a first switching unit, a second switching unit, and a third switching unit. The first level conversion circuit is connected to the measured voltage output terminal through the first switching unit. The second level conversion circuit is connected to the measured voltage output terminal through the second switching unit. The measured voltage output terminal is also connected to the input voltage signal terminal via the third switching unit. The first level conversion circuit and the second level conversion circuit also receive the reference voltage. The first power supply voltage connected to the first level conversion circuit is the reference voltage, and the second power supply voltage connected to the second level conversion circuit is the reference voltage.

11. The voltage measuring device according to claim 10, wherein, The first switching unit, the second switching unit, and the third switching unit are configured to respond to control signals. Wherein, when the input voltage is within the voltage measurement range of the signal processing unit, the control signal is used to control the first switching unit to disconnect the connection between the measured voltage output terminal and the first level conversion circuit, the second switching unit to disconnect the connection between the second level conversion circuit and the measured voltage output terminal, and the third switching unit to connect the input voltage signal terminal and the measured voltage output terminal; In the case where the input voltage is less than the minimum value of the voltage measurement range of the signal processing unit, the control signal is used to control the first switching unit to turn on the measured voltage output terminal and the first level conversion circuit, the second switching unit to disconnect the second level conversion circuit and the measured voltage output terminal, and the third switching unit to disconnect the input voltage signal terminal and the measured voltage output terminal. In the case where the input voltage is greater than the maximum value of the voltage measurement range of the signal processing unit, the control signal is used to control the first switching unit to disconnect the connection between the measured voltage output terminal and the first level conversion circuit, the second switching unit to connect the second level conversion circuit and the measured voltage output terminal, and the third switching unit to disconnect the connection between the input voltage signal terminal and the measured voltage output terminal.

12. The voltage measuring device according to claim 9, wherein, The signal processing unit includes an analog-to-digital conversion unit.

13. A voltage measurement method, applied to the voltage measuring device of claim 10, the voltage measurement method comprising: In response to receiving the input voltage at the input voltage receiving terminal, the input voltage is compared with the voltage measurement range of the signal processing unit to obtain a comparison result; Based on the comparison results, a control signal is generated; According to the control signal, the first switch unit, the second switch unit, and the third switch unit are controlled to open or close. as well as The signal processing unit measures the output voltage provided by the measurement voltage output terminal and outputs the measurement result.

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