A power state monitoring and thermal protection circuit based on FPGA

Abstract

The utility model discloses a power state monitoring and thermal protection circuit based on FPGA, including analog signal acquisition module, AD signal conversion module, level conversion module, logic discrimination module, power module and reset module, analog signal acquisition module and AD signal conversion module's analog signal input electric connection, AD signal conversion module's digital signal output respectively with level conversion module's input electric connection, level conversion module's output respectively with logic discrimination module's parallel data input pin electric connection, power module and logic discrimination module's auxiliary power input pin, kernel power input pin, I / O power input pin electric connection, reset module and logic discrimination module's reset pin and configuration complete pin electric connection. The utility model can solve the technical problem of the existing fixed threshold's thermal protection circuit technology lack of dynamic analysis ability to temperature variation trend, and easy to produce the misoperation or protection lag.

Description

Technical Field

[0001] This utility model belongs to the field of circuit technology, and more specifically, relates to a power status monitoring and thermal protection circuit based on FPGA. Background Technology

[0002] With the increasing complexity and integration of power electronic devices, power status monitoring and thermal protection have become crucial for ensuring system stability and reliability. During actual system operation, power modules are susceptible to load fluctuations and changes in ambient temperature, leading to abnormal power voltage and current, or localized overheating, which can cause system failures or even hardware damage. Power status monitoring can collect and monitor key power parameters (such as current, voltage, and temperature), effectively identifying abnormal and faulty states, ensuring stable system operation within safe thresholds, and thus preventing equipment damage due to power abnormalities or overheating. Simultaneously, thermal protection circuits, by monitoring system temperature changes and implementing dynamic protection strategies, can prevent device aging and thermal breakdown caused by heat accumulation or localized overheating, significantly extending equipment lifespan. Therefore, designing effective power status monitoring and thermal protection circuits has significant engineering and practical value for improving the robustness, reliability, and safety of power electronic systems and extending equipment lifespan.

[0003] There are four main existing power supply status monitoring and thermal protection technologies: fixed-threshold thermal protection circuit technology, analog circuit monitoring technology, microcontroller (MCU) monitoring technology, and application-specific integrated circuit (ASIC) monitoring technology. Fixed-threshold thermal protection circuit technology monitors the system power supply temperature using a fixed-threshold temperature switch, a thermistor circuit, and a threshold comparator, triggering protection when the temperature exceeds a set value. Analog circuit detection technology monitors parameters such as voltage, current, and temperature of the system power supply using analog circuits, detecting signals exceeding preset thresholds using comparators and analog multiplexers. Microcontroller (MCU) monitoring technology acquires sensor data through the microcontroller's built-in ADC module and uses software algorithms to determine and control the status of parameters such as voltage, current, and temperature of the system power supply. ASIC monitoring technology uses specially designed ASIC chips to monitor and protect the power supply based on parameters such as voltage, current, and temperature.

[0004] However, the existing power status monitoring and thermal protection circuit technologies still have some significant drawbacks:

[0005] 1. Fixed threshold thermal protection circuit technology relies excessively on fixed temperature switches, thermistor circuits, and threshold comparators, lacks the ability to dynamically analyze temperature change trends, and is prone to malfunctions or protection delays.

[0006] 2. Analog circuit monitoring technology requires separate design of analog signal conditioning and digital control modules, resulting in a large system footprint and weak anti-interference capability.

[0007] 3. Microcontroller (MCU) monitoring technology is limited by the serial processing capability of MCU when facing parallel acquisition of multiple parameters, resulting in high response delay and difficulty in meeting the real-time protection requirements of power supply systems.

[0008] 4. Application-specific integrated circuit (ASIC) monitoring technology has fixed functions, making it difficult to adapt to diverse application scenarios. It also has a long development cycle, high customization costs, lack of flexibility, and cannot support algorithm optimization or function iteration. Utility Model Content

[0009] To address the aforementioned deficiencies or improvement needs of existing technologies, this utility model provides a power status monitoring and thermal protection circuit based on FPGA. Its purpose is to solve the technical problems of existing fixed-threshold thermal protection circuits, which rely excessively on fixed temperature switches, thermistor circuits, and threshold comparators, lacking dynamic analysis capabilities for temperature change trends and prone to malfunctions or protection lag; existing microcontroller monitoring technologies and analog circuit monitoring technologies, which suffer from large system footprint and weak anti-interference capabilities; existing microcontroller monitoring technologies, which are limited by the serial processing capabilities of MCUs when facing multi-parameter parallel acquisition, resulting in high response delays and difficulty in meeting the real-time protection requirements of power systems; and existing application-specific integrated circuit (ASIC) monitoring technologies, which have fixed functions, are difficult to adapt to diverse application scenarios, have long development cycles, high customization costs, lack flexibility, and cannot support algorithm optimization or functional iteration.

[0010] To achieve the above objectives, according to one aspect of this utility model, a power status monitoring and thermal protection circuit based on FPGA is provided, including an analog signal acquisition module, an A / D signal conversion module, a level conversion module, a logic discrimination module, a power supply module, and a reset module, wherein the analog signal acquisition module and the analog signal input terminal of the A / D signal conversion module are electrically connected;

[0011] The digital signal output terminals of the A / D signal conversion module are electrically connected to the input terminals of the level conversion module.

[0012] The output of the level conversion module is electrically connected to the parallel data input pin of the logic discrimination module.

[0013] The auxiliary power input pin, core power input pin, and I / O power input pin of the power module and the logic discrimination module are electrically connected;

[0014] The reset pin and configuration completion pin of the reset module and logic discrimination module are electrically connected.

[0015] Preferably, the analog signal acquisition module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a first operational amplifier, a second operational amplifier, a third operational amplifier, a first diode, a second diode, a third diode, a first power supply, a second power supply, and a third power supply;

[0016] One end of the first resistor, the second resistor, and the third resistor are electrically connected to the non-inverting input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier, respectively, and the other end of the first resistor, the second resistor, and the third resistor are electrically connected to the third power supply.

[0017] One end of the first capacitor, the second capacitor, and the third capacitor are electrically connected to the positive power input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier, respectively, and the other end of the first capacitor, the second capacitor, and the third capacitor are electrically connected to the ground wire.

[0018] One end of the fourth, fifth, and sixth resistors is electrically connected to the output terminals of the first, second, and third operational amplifiers, respectively, and the other end of the fourth, fifth, and sixth resistors is electrically connected to the negative terminals of the first, second, and third diodes, respectively.

[0019] The positive terminals of the first diode, the second diode, and the third diode are electrically connected to the ground wire, respectively.

[0020] The first power supply is electrically connected to the positive power input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier;

[0021] The second power supply is electrically connected to the negative power supply input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier.

[0022] Preferably, the resistance values ​​of the first resistor, the second resistor, and the third resistor are all 10 kΩ, and the selected thermistors are SDNT1005X103F3950FTF.

[0023] The capacitance values ​​of the first, second, and third capacitors are all 0.1 microfarads, and the selected capacitors are model 104100NF100N.

[0024] The fourth, fifth, and sixth resistors all have a resistance of 51 ohms, and the selected resistors are model 181251R.

[0025] The first operational amplifier, the second operational amplifier, and the third operational amplifier are operational amplifiers of model TL064CNSR.

[0026] The first diode, the second diode, and the third diode are selected as LSSPD-6-2P-0 diodes;

[0027] The first and second power supplies are both RID-125-1515 power supplies.

[0028] The third power supply is an adjustable power supply of model MS152D;

[0029] Preferably, the A / D signal conversion module includes a first analog-to-digital converter, a seventh resistor, an eighth resistor, a ninth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first capacitor, a second capacitor, and a fourth power supply;

[0030] The input terminal of the first analog-to-digital converter is electrically connected to the analog signal acquisition module, and the output terminal is electrically connected to the input terminal of the level conversion module.

[0031] One end of the seventh resistor is electrically connected to the operating mode control pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply.

[0032] One end of the eighth resistor is electrically connected to the RANGE pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply.

[0033] One end of the ninth resistor is electrically connected to the ADC voltage source reference select pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply.

[0034] One end of the fourth capacitor is connected to the +3.3V power supply, and the other end is connected to the ground wire;

[0035] One end of the fifth, sixth, and seventh capacitors is electrically connected to the fourth power supply, and the other end is electrically connected to the ground wire.

[0036] One end of the eighth capacitor is electrically connected to the decoupling pin of the first analog-to-digital converter, and the other end is electrically connected to the ground pin of the first analog-to-digital converter.

[0037] One end of the first capacitor is electrically connected to the reference voltage capacitor pin of the first analog-to-digital converter, and the other end is electrically connected to the ground wire.

[0038] One end of the second capacitor is electrically connected to the reset pin of the first analog-to-digital converter, and the other end is electrically connected to ground.

[0039] Preferably, the resistance values ​​of the seventh, eighth, and ninth resistors are 4.7 kΩ, and the resistors are ATD4701 type.

[0040] The fourth, fifth, sixth, and seventh capacitors all have a capacitance of 0.1 microfarads and are selected as capacitors with the model number 104100NF100N.

[0041] The eighth capacitor has a capacitance of 1 microfarad and is a 5KBFZFN# capacitor.

[0042] The first and second capacitors are 16V 10UF capacitors.

[0043] The fourth power supply used is an MS152D adjustable power supply;

[0044] The first analog-to-digital converter used is the AD7606BSTZ-6.

[0045] Preferably, the level conversion module includes a ninth capacitor, a tenth capacitor, and a first bidirectional bus driver;

[0046] One end of the ninth and tenth capacitors is electrically connected to the +3.3V power supply, and the other end is electrically connected to the ground wire;

[0047] The input terminal of the first bidirectional bus driver is electrically connected to the digital signal output terminal of the A / D signal conversion module, and the output terminal is electrically connected to the parallel data input pin of the logic discrimination module.

[0048] The capacitance values ​​of the ninth and tenth capacitors are both 0.1 microfarads, and the capacitors selected are model 104100NF100N.

[0049] The first bidirectional bus driver selected is a bidirectional bus driver with model number 74LCX16245MTDX.

[0050] Preferably, the logic discrimination module uses an FPGA chip with the model number XC6SL-2CSG324I.

[0051] Preferably, the power module includes an eleventh capacitor, a twelfth capacitor, a fifth power supply, and a sixth power supply.

[0052] One end of the eleventh capacitor is connected to the fifth power supply, and the other end is connected to the ground wire.

[0053] One end of the twelfth capacitor is connected to the sixth power supply, and the other end is connected to the ground wire.

[0054] The auxiliary power input pin, core power input pin, and I / O power input pin of the fifth power supply and logic discrimination module are electrically connected.

[0055] The eleventh and twelfth capacitors both have a capacitance of 0.1 microfarads and are selected as 104100NF100N capacitors.

[0056] The fifth and sixth power supplies are MS152D adjustable power supplies.

[0057] Preferably, the reset module includes a tenth resistor and an eleventh resistor;

[0058] One end of the tenth resistor is electrically connected to the reset pin of the logic discrimination module, and the other end is electrically connected to the +3.3V power supply.

[0059] One end of the eleventh resistor is electrically connected to the configuration completion pin of the logic discrimination module, and the other end is electrically connected to the +3.3V power supply.

[0060] The tenth resistor has a resistance of 330 ohms and is a MOF-3WS-330R-J-TB resistor.

[0061] The eleventh resistor has a resistance of 4.7 kΩ and is an ATD4701 resistor.

[0062] Preferably, the operating voltage of the first power supply is +15V;

[0063] The operating voltage of the second power supply is -15V;

[0064] The operating voltage of the third power supply is +2.5V;

[0065] The fourth power supply operates at +5V;

[0066] The fifth power supply operates at +3.3V;

[0067] The operating voltage of the sixth power supply is +1.2V.

[0068] In summary, compared with the prior art, the above-described technical solution conceived by this utility model can achieve the following beneficial effects:

[0069] 1. This utility model uses an FPGA to collect real-time current, voltage, and multi-channel temperature data from the power supply. Through programming, it implements complex algorithms to dynamically analyze the changing trends of parameters such as current, voltage, and temperature, and to predict potential overheating risks in advance. Therefore, it solves the technical problems of fixed-threshold thermal protection circuits, which rely excessively on fixed-temperature switches, thermistor circuits, and threshold comparators, lacking the ability to dynamically analyze temperature change trends, and are prone to malfunctions or protection delays.

[0070] 2. The FPGA chip used in this invention integrates digital control and algorithm processing functions into a single chip, reducing the need for discrete module design and thus significantly reducing system footprint. Simultaneously, the FPGA employs digital signal processing technology, providing strong anti-interference capabilities. Therefore, it solves the technical problem of analog circuit monitoring technology, which requires separate design of analog signal conditioning and digital control modules, resulting in large system footprint and weak anti-interference capabilities.

[0071] 3. This invention adopts an FPGA parallel architecture, which can realize the synchronous acquisition and processing of power supply current, voltage, and multiple temperature data. Therefore, it can solve the technical problem that microcontroller (MCU) monitoring technology is limited by the serial processing capability of the MCU when facing parallel acquisition of multiple parameters, resulting in high response delay and difficulty in meeting the real-time protection requirements of the power supply system.

[0072] 4. The FPGA chip used in this invention is programmable, allowing algorithm optimization and function iteration to be redefined through programming. This results in a shorter development cycle and easier adaptation to diverse application scenarios. Therefore, it addresses the limitations of application-specific integrated circuit (ASIC) monitoring technology, which suffers from fixed functions, difficulty in adapting to diverse application scenarios, long development cycles, high customization costs, lack of flexibility, and inability to support algorithm optimization or function iteration. Attached Figure Description

[0073] Figure 1 This is a circuit structure diagram of the FPGA-based power status monitoring and thermal protection circuit of this utility model;

[0074] Figure 2 This is a circuit diagram of the A / D signal conversion module in the FPGA-based power status monitoring and thermal protection circuit of this utility model;

[0075] Figure 3 This is a circuit diagram of the level conversion module in the FPGA-based power status monitoring and thermal protection circuit of this utility model. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model. Furthermore, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.

[0077] like Figure 1As shown, this utility model provides a power status monitoring and thermal protection circuit based on FPGA, including a clock signal analog signal acquisition module 1, an A / D signal conversion module 2, a level conversion module 3, a logic discrimination module 4, a power supply module 5, and a reset module 6.

[0078] The analog signal acquisition module 1 and the analog signal input terminals V1-V8 of the A / D signal conversion module 2 are electrically connected. The digital signal output terminals DB0-DB15 of the A / D signal conversion module 2 are electrically connected to the input terminals CADD0-CADD15 of the level conversion module 3, respectively. The output terminals XD0-XD15 of the level conversion module 3 are electrically connected to the parallel data input pins FADD0-FADD15 of the logic discrimination module 4, respectively. The power supply module 5 is electrically connected to the auxiliary power input pin VCCAAUX, the core power input pin VCCINT, and the I / O power input pin VCCO of the logic discrimination module 4. The reset module 6 is electrically connected to the reset pin PROGRAM_B_2 and the configuration completion pin DONE_2 of the logic discrimination module 4.

[0079] The analog signal acquisition module 1 includes a first resistor R248, a second resistor R249, a third resistor R250, a fourth resistor R251, a fifth resistor R252, a sixth resistor R253, a first capacitor C211, a second capacitor C212, a third capacitor C213, a first operational amplifier U66A, a second operational amplifier U66B, a third operational amplifier U66C, a first diode D1, a second diode D2, a third diode D3, a first power supply (+15V), a second power supply (-15V), and a third power supply (+2.5V).

[0080] One end of the first resistor R248, the second resistor R249, and the third resistor R250 are electrically connected to the non-inverting input terminals of the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C, respectively. The other end of the first resistor R248, the second resistor R249, and the third resistor R250 are electrically connected to the third power supply (whose operating voltage is +2.5V). One end of the first capacitor C211, the second capacitor C212, and the third capacitor C213 are electrically connected to the positive power supply input terminals of the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C, respectively. 211. The other ends of the second capacitor C212 and the third capacitor C213 are electrically connected to the ground wire AGND. One end of the fourth resistor R251, the fifth resistor R252, and the sixth resistor R253 are electrically connected to the output terminals of the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C, respectively. The other ends of the fourth resistor R251, the fifth resistor R252, and the sixth resistor R253 are electrically connected to the negative terminals of the first diode D1, the second diode D2, and the third diode D3, respectively. The positive terminals of the first diode D1, the second diode D2, and the third diode D3 are electrically connected to the ground wire AGND. The first power supply (its operating voltage is +15V) is electrically connected to the positive power supply input terminals of the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C. The second power supply (its operating voltage is -15V) is electrically connected to the negative power supply input terminals of the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C.

[0081] The first resistor R248, the second resistor R249, and the third resistor R250 are all 10 kΩ thermistors manufactured by Shenzhen Defang Electronics Co., Ltd., model SDNT1005X103F3950FTF. The first capacitor C211, the second capacitor C212, and the third capacitor C213 are all 0.1 μF capacitors manufactured by Shuyang Jiayile E-commerce Co., Ltd., model 104100NF100NF50V. The fourth resistor R251, the fifth resistor R252, and the sixth resistor R253 are all 51 Ω thermistors manufactured by Shenzhen Qixin Micro Technology Co., Ltd., model 18. The resistors are 1251R; the first operational amplifier U66A, the second operational amplifier U66B, and the third operational amplifier U66C are operational amplifiers manufactured by Shenzhen Chuangxin Lianying Electronics Co., Ltd., model TL064CNSR; the first diode D1, the second diode D2, and the third diode D3 are diodes manufactured by Beijing Minguang Technology Co., Ltd., model LSSPD-6-2P-0; the first and second power supplies are power supplies manufactured by Mean Well (Guangzhou) Electronics Co., Ltd., model RID-125-1515; the third power supply is an adjustable power supply manufactured by Maisheng Medical Equipment Co., Ltd., model MS152D.

[0082] like Figure 2 As shown, the A / D signal conversion module 2 includes a first analog-to-digital converter AD7606, a seventh resistor R215, an eighth resistor R216, a ninth resistor R219, a fourth capacitor C58, a fifth capacitor C59, a sixth capacitor C60, a seventh capacitor C61, an eighth capacitor C176, a first capacitor C169, a second capacitor C170, and a fourth power supply (its operating voltage is +5V).

[0083] The input terminals V1-V8 of the first analog-to-digital converter are electrically connected to the analog signal acquisition module 1, and the output terminals ADD0-ADD15 are electrically connected to the input terminals CADD0-CADD15 of the level conversion module; one end of the seventh resistor R215 is electrically connected to the STBY pin of the first analog-to-digital converter AD7606, and the other end is electrically connected to the +3.3V power supply; one end of the eighth resistor R216 is electrically connected to the RANGE pin of the first analog-to-digital converter AD7606, and the other end is electrically connected to the +3.3V power supply; the ninth resistor R219... One end of the first capacitor C58 is electrically connected to the ADC voltage source reference select pin REFSELECT, and the other end is electrically connected to the +3.3V power supply; one end of the fourth capacitor C58 is electrically connected to the +3.3V power supply, and the other end is connected to ground; one end of the fifth capacitor C59, the sixth capacitor C60, and the seventh capacitor C61 are electrically connected to the fourth power supply (its operating voltage is +5V), and the other end is electrically connected to ground; one end of the eighth capacitor C176 is electrically connected to the decoupling pin REGCAP of the first analog-to-digital converter AD7606, and the other end is electrically connected to the ground pin AGND of the first analog-to-digital converter AD7606; one end of the first capacitor C169 is electrically connected to the reference voltage capacitor pin REFCAPA of the first analog-to-digital converter AD7606, and the other end is electrically connected to ground; one end of the second capacitor C170 is electrically connected to the reset pin REFIN / REFOUT of the first analog-to-digital converter AD7606, and the other end is electrically connected to ground.

[0084] The seventh resistor R215, the eighth resistor R216, and the ninth resistor R219 have a resistance of 4.7 kΩ and are AR05DTD4701 resistors manufactured by Shenzhen Jiebixin Industrial Co., Ltd. The fourth capacitor C58, the fifth capacitor C59, the sixth capacitor C60, and the seventh capacitor C61 all have a capacitance of 0.1 μF and are 104100NF100NF50V capacitors manufactured by Shuyang Jiayile E-commerce Co., Ltd. The eighth capacitor C176 has a capacitance of 1 μF and is from Shenzhen Jiebixin Industrial Co., Ltd. The capacitors used are: CL21B105KBFZFN# manufactured by Shenzhen Tailai Electronics Trading Co., Ltd.; the first capacitor C169 and the second capacitor C170 are 16V10UF capacitors manufactured by Shuyang Daoerchi E-commerce Co., Ltd.; the fourth power supply (+5V) is an MS152D adjustable power supply manufactured by Maisheng Medical Equipment Co., Ltd.; and the first analog-to-digital converter AD7606 is an AD7606BST Z-6 analog-to-digital converter manufactured by Shenzhen Xinsihui Technology Co., Ltd.

[0085] like Figure 3As shown, the level conversion module 3 includes a ninth capacitor C67, a tenth capacitor C68, and a first bidirectional bus driver 74LCX16245.

[0086] One end of the ninth capacitor C67 and the tenth capacitor C68 are electrically connected to the +3.3V power supply, and the other end is electrically connected to the ground wire; the input terminal of the first bidirectional bus driver 74LCX16245 is electrically connected to the digital signal output terminals ADD0-ADD15 of the A / D signal conversion module, and the output terminals XD0-XD15 are electrically connected to the parallel data input pins FADD0-FADD15 of the logic discrimination module;

[0087] The ninth capacitor C67 and the tenth capacitor C68 both have a capacitance of 0.1 microfarads. They are capacitors manufactured by Shuyang Jiayile E-commerce Co., Ltd., with the model number 104100NF100NF50V. The first bidirectional bus driver is a bidirectional bus driver manufactured by Shenzhen Xinxiangyang Technology Co., Ltd., with the model number 74LC X16245MTDX.

[0088] The logic discrimination module 4 is specifically an FPGA chip, specifically the XC6SLX45T-2CSG324I FPGA chip manufactured by Shenzhen Xinxiangyang Technology Co., Ltd.

[0089] Power module 5 includes an eleventh capacitor C24, a twelfth capacitor C25, a fifth power supply (+3.3V), and a sixth power supply (+1.2V);

[0090] One end of the eleventh capacitor C24 is electrically connected to the fifth power supply (its operating voltage is +3.3V), and the other end is electrically connected to the ground; one end of the twelfth capacitor C25 is electrically connected to the sixth power supply (its operating voltage is +1.2V), and the other end is electrically connected to the ground; the fifth power supply (+3.3V) is electrically connected to the auxiliary power input pin VCCAAUX, the core power input pin VCCINT, and the I / O power input pin VCCO of the logic discrimination module 4;

[0091] The eleventh capacitor C24 and the twelfth capacitor C25 both have a capacitance of 0.1 microfarads. They are capacitors manufactured by Shuyang Jiayile E-commerce Co., Ltd., with the model number 104100NF100NF50V. The fifth power supply (+3.3V) and the sixth power supply (+1.2V) are adjustable power supplies manufactured by Maisheng Medical Equipment Co., Ltd., with the model number MS152D.

[0092] The reset module 6 includes a tenth resistor R28 and an eleventh resistor R32.

[0093] One end of the tenth resistor R28 is electrically connected to the reset pin (PROGRAM_B_2) of the logic discrimination module 4, and the other end is electrically connected to the +3.3V power supply; one end of the eleventh resistor R32 is electrically connected to the configuration completion pin DONE_2 of the logic discrimination module 4, and the other end is electrically connected to the +3.3V power supply.

[0094] The tenth resistor, R28, has a resistance of 330 ohms and is a MOF-3WS-330R-J-TB resistor manufactured by Shenzhen Yingfa Electronics Co., Ltd.; the eleventh resistor, R32, has a resistance of 4.7 kΩ and is an AR05DTD4701 resistor manufactured by Shenzhen Jiebixin Industrial Co., Ltd.

[0095] The working principle of this invention is as follows: First, the output terminal 1 of the analog signal acquisition module is electrically connected to the input terminal of the A / D signal conversion module 2, thereby acquiring analog signals of multiple parameters of the power supply, including voltage, current, and temperature. The analog signals of the voltage and current parameters are input through pins V4-V8 of the A / D signal conversion module 2, while the analog signal of the temperature parameter is input through pins V1-V3. Then, the A / D signal conversion module 2 converts the acquired analog signals of the power supply's voltage, current, and temperature into digital signals, thus obtaining the converted digital signals of these parameters. Subsequently, the digital signals of the power supply's voltage, current, and temperature obtained from the A / D signal conversion module 2 are transmitted to the input terminal CADD0 of the level conversion module 3 for level conversion and data buffering processing, thereby obtaining the level-converted and data-buffered digital signal. Subsequently, the digital signal, after level conversion and data buffering, is transmitted to the parallel data input pins FADD0-FADD15 of the logic discrimination module 4. The logic discrimination module 4 compares the input data with its internal algorithm to determine whether the power supply is in an abnormal state. Next, the reset module 6 is electrically connected to the reset pin PROGRAM_B_2 and the configuration completion pin DONE_2 of the logic discrimination module 4, thereby realizing the function of resetting when the voltage, current, temperature and other parameters of the power supply are abnormal. Finally, the eleventh capacitor C24 is electrically connected to the fifth power supply (its operating voltage is +3.3V), and the other end is electrically connected to the ground; one end of the twelfth capacitor C25 is electrically connected to the sixth power supply (its operating voltage is +1.2V), and the other end is electrically connected to the ground; the fifth power supply (+3.3V) is electrically connected to the auxiliary power input pin VCCAAUX, the core power input pin VCCINT, and the I / O power input pin VCCO of the logic discrimination module 4, thereby realizing continuous power supply to the logic discrimination module 4.

[0096] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A power status monitoring and thermal protection circuit based on FPGA, comprising an analog signal acquisition module, an A / D signal conversion module, a level conversion module, a logic discrimination module, a power supply module, and a reset module, characterized in that, The analog signal acquisition module is electrically connected to the analog signal input terminal of the A / D signal conversion module; The digital signal output terminals of the A / D signal conversion module are electrically connected to the input terminals of the level conversion module. The output of the level conversion module is electrically connected to the parallel data input pin of the logic discrimination module. The auxiliary power input pins, core power input pins, and I / O power input pins of the power module and the logic discrimination module are electrically connected; The reset pin and configuration completion pin of the reset module and logic discrimination module are electrically connected.

2. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The analog signal acquisition module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, a third capacitor, a first operational amplifier, a second operational amplifier, a third operational amplifier, a first diode, a second diode, a third diode, a first power supply, a second power supply, and a third power supply; One end of the first resistor, the second resistor, and the third resistor are electrically connected to the non-inverting input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier, respectively, and the other end of the first resistor, the second resistor, and the third resistor are electrically connected to the third power supply. One end of the first capacitor, the second capacitor, and the third capacitor are electrically connected to the positive power input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier, respectively, and the other end of the first capacitor, the second capacitor, and the third capacitor are electrically connected to the ground wire. One end of the fourth, fifth, and sixth resistors is electrically connected to the output terminals of the first, second, and third operational amplifiers, respectively, and the other end of the fourth, fifth, and sixth resistors is electrically connected to the negative terminals of the first, second, and third diodes, respectively. The positive terminals of the first diode, the second diode, and the third diode are respectively connected to the ground wire. The first power supply is electrically connected to the positive power input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier; The second power supply is electrically connected to the negative power supply input terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier.

3. The FPGA-based power status monitoring and thermal protection circuit according to claim 2, characterized in that, The resistance values ​​of the first, second, and third resistors are all 10 kΩ, and the selected model is SDNT1005X103F3950FTF thermistor. The capacitance values ​​of the first, second, and third capacitors are all 0.1 microfarads, and the selected capacitors are model 104100NF100N. The fourth, fifth, and sixth resistors all have a resistance of 51 ohms, and the selected resistors are model 181251R. The first operational amplifier, the second operational amplifier, and the third operational amplifier are operational amplifiers of model TL064CNSR. The first diode, the second diode, and the third diode are selected as LSSPD-6-2P-0 diodes; The first and second power supplies are both RID-125-1515 power supplies. The third power supply is an adjustable power supply of model MS152D.

4. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The A / D signal conversion module includes a first analog-to-digital converter, a seventh resistor, an eighth resistor, a ninth resistor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a first capacitor, a second capacitor, and a fourth power supply; The input terminal of the first analog-to-digital converter is electrically connected to the analog signal acquisition module, and the output terminal is electrically connected to the input terminal of the level conversion module. One end of the seventh resistor is electrically connected to the operating mode control pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply. One end of the eighth resistor is electrically connected to the RANGE pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply. One end of the ninth resistor is electrically connected to the ADC voltage source reference select pin of the first analog-to-digital converter, and the other end is electrically connected to the +3.3V power supply. One end of the fourth capacitor is connected to the +3.3V power supply, and the other end is connected to the ground wire; One end of the fifth, sixth, and seventh capacitors is electrically connected to the fourth power supply, and the other end is electrically connected to the ground wire. One end of the eighth capacitor is electrically connected to the decoupling pin of the first analog-to-digital converter, and the other end is electrically connected to the ground pin of the first analog-to-digital converter. One end of the first capacitor is electrically connected to the reference voltage capacitor pin of the first analog-to-digital converter, and the other end is electrically connected to the ground wire. One end of the second capacitor is electrically connected to the reset pin of the first analog-to-digital converter, and the other end is electrically connected to ground.

5. The FPGA-based power status monitoring and thermal protection circuit according to claim 4, characterized in that, The resistance values ​​of the seventh, eighth, and ninth resistors are 4.7 kΩ, and the resistors selected are ATD4701. The fourth, fifth, sixth, and seventh capacitors all have a capacitance of 0.1 microfarads and are selected as capacitors with the model number 104100NF100N. The eighth capacitor has a capacitance of 1 microfarad and is a 5KBFZFN# capacitor. The first and second capacitors are 16V 10UF capacitors. The fourth power supply used is an MS152D adjustable power supply; The first analog-to-digital converter used is the AD7606BSTZ-6.

6. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The level conversion module includes a ninth capacitor, a tenth capacitor, and a first bidirectional bus driver; One end of the ninth and tenth capacitors is electrically connected to the +3.3V power supply, and the other end is electrically connected to the ground wire; The input terminal of the first bidirectional bus driver is electrically connected to the digital signal output terminal of the A / D signal conversion module, and the output terminal is electrically connected to the parallel data input pin of the logic discrimination module. The capacitance values ​​of the ninth and tenth capacitors are both 0.1 microfarads, and the capacitors selected are model 104100NF100N. The first bidirectional bus driver selected is a bidirectional bus driver with model number 74LCX16245MTDX.

7. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The logic discrimination module uses an FPGA chip with the model number XC6SL-2CSG324I.

8. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The power module includes an eleventh capacitor, a twelfth capacitor, a fifth power supply, and a sixth power supply. One end of the eleventh capacitor is connected to the fifth power supply, and the other end is connected to the ground wire. One end of the twelfth capacitor is connected to the sixth power supply, and the other end is connected to the ground wire. The auxiliary power input pin, core power input pin, and I / O power input pin of the fifth power supply and logic discrimination module are electrically connected; The eleventh and twelfth capacitors both have a capacitance of 0.1 microfarads and are selected as 104100NF100N capacitors. The fifth and sixth power supplies are MS152D adjustable power supplies.

9. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The reset module includes the tenth resistor and the eleventh resistor; One end of the tenth resistor is electrically connected to the reset pin of the logic discrimination module, and the other end is electrically connected to the +3.3V power supply. One end of the eleventh resistor is electrically connected to the configuration completion pin of the logic discrimination module, and the other end is electrically connected to the +3.3V power supply. The tenth resistor has a resistance of 330 ohms and is a MOF-3WS-330R-J-TB resistor. The eleventh resistor has a resistance of 4.7 kΩ and is an ATD4701 resistor.

10. The FPGA-based power status monitoring and thermal protection circuit according to claim 1, characterized in that, The operating voltage of the first power supply is +15V; The operating voltage of the second power supply is -15V; The operating voltage of the third power supply is +2.5V; The fourth power supply operates at +5V; The fifth power supply operates at +3.3V; The operating voltage of the sixth power supply is +1.2V.

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