Method for collecting sensing signals, corresponding sensor device and imaging camera

Abstract

A method for collecting sensing signals, a corresponding sensor device, and an imaging camera are disclosed. A current signal indicating a sensed physical quantity is collected from a sensing transistor in a sensing transistor array. The sensing transistor has a corresponding control node and a current channel path passing between a corresponding first node and a second node shared by the sensing transistor. A bias voltage level is applied to a corresponding first node of the sensing transistor in the array, and one of the sensing transistors in the sensing transistor array is selected. The selected sensing transistor is decoupled from the bias voltage level, while the remaining sensing transistors in the sensing transistor array remain coupled to the bias voltage level. The corresponding first node of the selected sensing transistor in the sensing transistor array is coupled to an output node, and an output current signal is collected from the output node.

Description

[0001] Priority declaration

[0002] This application claims the benefit of priority from Italian Patent Application No. 102021000013181 filed on May 20, 2021, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to methods for collecting signals from sensors.

[0004] One or more embodiments may be used in conjunction with a passive infrared (IR) temperature sensor, such as a thermal MOS (TMOS) transistor device.

[0005] One or more embodiments may be applied in a healthcare or Internet of Things (IoT) context. Background Art

[0006] For example, non-imaging passive infrared (IR) security sensors are used in healthcare and industrial applications, such as motion detection in alarm systems.

[0007] These sensors are arranged in an array that is configured to create an image of an object based on the detected infrared radiation emitted from it. The image created represents the temperature of the object. It consists of a number of sub-pixels corresponding to a single sensor in the array arrangement that are electrically connected but thermally isolated.

[0008] TMOS devices can be used as IR sensors. The term "TMOS" (or "thermal MOS") currently refers to MOS transistors, such as those manufactured in standard CMOS-SOI technology. Due to appropriate microprocessing and dry etching processes, TMOS includes a silicon "block". The surface of the connection between the silicon "block" and the rest of the semiconductor die is reduced as much as possible (within mechanical tolerances) in order to maximize the thermal insulation of the TMOS.

[0009] For example, to measure IR radiation, the TMOS sensor is configured to send IR radiation to the "bulk" portion, which thereby becomes heated. The high thermal insulation of the rest of the die ensures that the heat received by the TMOS from the external quantity to be measured (e.g., IR radiation) causes a perceptible temperature change.

[0010] Due to the IV characteristics of the transistor itself, the temperature change of the TMOS is converted into an electrical signal. To this end, it may be relevant to provide a proper bias for the TMO. In addition, the amplification and post-processing of the small current signal generated in response to the temperature change can play an important role.

[0011] Existing front-end analog signal readout circuits for TMOS sensors envision a "bridge" differential circuit that measures the electrical signal difference between an array of TMOS sensors that are optically exposed ("active") and at least one TMOS sensor that is shielded from optical exposure ("blind").

[0012] This type of solution is proposed by Liang Dong, et al., "Fabrication and characterization of integrated uncooled infrared sensor arrays using a-Si thin-film transistors as active elements," Journal of Microelectromechanical Systems, vol. 14, no. 5, pp. 1167-1177, Oct. 2005, doi: 10.1109 / JMEMS.2005.851807 (incorporated by reference). The document discusses a monolithic uncooled 8 / spl times / 8 infrared sensor array based on amorphous silicon thin film transistors (a-Si TFTs). Since a-Si TFTs have a high leakage current temperature coefficient at room temperature, a-Si TFTs are used as active elements of the sensor. The porous silicon micromachining technology described in the document enables the sensor array based on a-Si TFTs to be integrated with a MOS readout circuit. A sacrificial material of porous silicon is prepared in a first step. Then, during the manufacture of the MOSFET and the sensor, it is always well protected before being released. Optical tests are performed to characterize the sensor. The effects of the gate voltage (V / sub g / ) of the a-Si TFT and the voltage source (V / sub dd / ) of the circuit system on the sensor performance were studied.

[0013] Existing solutions may suffer from one or more of the following disadvantages: difficulty in selecting each pixel of both "active" TMOS sensors and "blind" TMOS sensors; difficulty in correctly biasing unselected pixels; complex solutions for reducing TMOS sensor self-heating, introducing additional selection circuits; complex multiplexing operations for individually addressing each sensor of the array; and leakage at high temperatures can be almost non-negligible.

[0014] There is a need in the art to advance ways to overcome the above-mentioned shortcomings. Summary of the invention

[0015] One or more embodiments may be directed to a method. A method of collecting signals sensed from sense transistors in a sense transistor array may be an example of such a method.

[0016] One or more embodiments may relate to a respective sensor device.

[0017] One or more embodiments may be provided on an IR camera.

[0018] One or more embodiments facilitate reading signals generated by a TMOS array configured to generate an image representative of the distribution of temperature of an irradiating object in space in response to detecting IR radiation incident thereon.

[0019] One or more embodiments facilitate reading TMOS signals in an array (eg, of size n×j) of TMOS devices in a fast manner by reducing the thermal constant τ of the TMOS devices.

[0020] One or more embodiments facilitate maintaining proper biasing of all devices of an array.

[0021] One or more embodiments facilitate reducing dead time due to thermal transients of a sensor.

[0022] One or more embodiments facilitate reducing temperature leakage effects, especially at high temperatures. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0024] Figure 1 is an exemplary circuit diagram of a sensing transistor array;

[0025] Figure 2 and Figure 3 is an exemplary diagram of characteristics of a sensing transistor; and

[0026] Figure 4 and Figure 5 is an exemplary diagram according to an embodiment of the present disclosure. Specific embodiments

[0027] In the following description, one or more specific details are shown to provide a deeper understanding of the examples of the embodiments of the present specification. The embodiments can be obtained without one or more specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not described or described in detail so as not to obscure certain aspects of the embodiments.

[0028] References to "an embodiment" or "an embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may be present in one or more points of this specification do not necessarily refer to the same embodiment.

[0029] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0030] The drawings are in simplified form and are not to exact scale.

[0031] Throughout the figures attached hereto, like parts or elements are denoted by like references / numerals, and the corresponding description will not be repeated for the sake of brevity.

[0032] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0033] Figure 1 is a circuit diagram of a thermal detector array including a sensing circuit part 10 and a signal processing circuit part 100 .

[0034] For simplicity, one or more embodiments discuss a detector array including a TMOS device configured to detect infrared (IR) radiation to provide a signal indicating the temperature of an object, and it is also understood that such a sensor device is purely exemplary and not limiting. For example, one or more embodiments may use any type of sensor, not only for detecting temperature, but also for detecting other physical quantities, such as pressure.

[0035] like Figure 1 As shown, the sensing circuit portion 10 includes a plurality of IR sensors (eg, TMOS devices) T 11 , T 1m ,…,T ij ,…,T n1 , T nm A two-dimensional matrix arrangement 10 having n number of rows and m number of columns, the ijth IR sensor T being identified via a tuple of indices including a first (eg, row) index i and a second (eg, column) index j ij Position in the matrix arrangement 10 .

[0036] For example, the IR sensors T on the same i-th row 11 , T 1m ,…,T ij, . . . having a common source terminal configured to be coupled to a first common voltage node (eg, ground) and a common gate terminal configured to be coupled to a bias voltage level Vg.

[0037] like Figure 1 The illustrated arrangement of thermal sensors can be used in the IR camera 1000 to place the ijth IR sensor T ij Consider the pixels of the IR camera 1000 to generate an image of an object emitting IR radiation. Specifically, the thermal IR detector T can be arranged two-dimensionally based on the pixels of the image to be detected. 11 , T 1m ,…,T ij ,…,T n1 , T n to generate a series of two-dimensional images.

[0038] like Figure 1 As shown, the sensing circuit system 10 further includes a bias branch Vg configured to 11 , T 1m ,…,T ij ,…,T n1 , T nm providing an appropriate bias voltage level Vg at a control node (e.g., a gate) of the IR sensor; and a plurality of switches, including a first plurality of (e.g., horizontal) switches and a second plurality of (e.g., vertical) switches, wherein the jth switch M in the first plurality of switches yj and the i-th switch M of the second plurality of switches xi Coupled to the ijth IR sensor T in the sensor array 10 ij .

[0039] like Figure 1 As illustrated, the signal processing circuit portion 100 of the detector comprises a multiplexing arrangement 102, 104, the multiplexing arrangement comprising a pair of shift registers 102, 104. For example: a first (eg, vertical) shift register 102 of the pair of shift registers 102, 104 is coupled to a first plurality of switches M yj , the first shift register 102 is configured to activate the jth switch M yj to select the jth entry (eg, row) of the matrix 10; and a second (eg, horizontal) shift register 104 coupled to a second plurality of switches, the second shift register 104 being configured ... by activating the i-th horizontal switch xi To select the i-th entry (eg, column) of the matrix arrangement 10 .

[0040] like Figure 1As illustrated, processing circuitry 100 also includes a reference (eg, MOSFET) transistor M coupled to at least one shift register (eg, 104) and a preamplifier stage 106. REF , and a pair of identical resistive loads Z coupled to the preamplifier stage 106 and the array 10.

[0041] In such Figure 1 In the illustrated conventional IR detector, the ij The output signals of are read (eg, sequentially) to the common sense amplifier 106 and are output to the common sense amplifier 106 .

[0042] For example, the processing circuit system 100 is configured (via the switch M xi 、M yj ) Select the ijth IR sensor T ij , and will refer to MOS M REF and load Z coupled to the ijth IR sensor T ij , thus forming a Wheatstone-like bridge configured to convert the ijth sensor T in a manner known per se ij The drain current in.

[0043] like Figure 1 As shown in the example, when the ijth sensor T ij is selected and coupled to the bias branch Vg, all remaining unselected sensors T 11 , T 1m ,…,T n1 , T nm Keep it off.

[0044] For example, the signal at the selected sensor T may be received and amplified via a preamplifier stage 106 (eg, an operational amplifier). ij The (drain) current flowing in.

[0045] like Figure 1 As illustrated, serial readout with a single preamplifier 106 provides a relatively simple implementation.

[0046] TMOS sensor T ij The sensing performance of varies based on different parameters, among which an important role may be played by the following: The thermal parameter τ, which is inversely proportional to the (residual) pressure inside the TMOS device (e.g., a pressure of about 0.01 to 1 Pascal corresponds to a thermal parameter of about 80 to 100 milliseconds), such as Figure 2 As illustrated; and the gate-source voltage V GS Evolution over time, in particular over a transient interval of time Δt, which is the signal V GS From the initial value V0 to the steady-state value V∞ time interval Δt.

[0047] like Figure 3 As shown, the TMOS T is biased using the current I0 provided at the initial time t0. ij In the exemplary case of GS Evolving from an initial value V0, it reaches a steady-state value V after a time interval Δt ∞ , this time interval can be expressed as a multiple of the thermal parameter τ, for example, Δt≈4τ.

[0048] The thermal τ and time Δt parameters may be related, as it is expected that the TMOS T ij No thermal sensing is performed during the transient time Δt (which is based on τ). This reduces the gain due to the change from the initial value V0 to the steady-state value V ∞ The transient voltage change in TMOS T ij The thermal contribution of the dissipated power affects the possibility of temperature measurement.

[0049] In such Figure 4 and Figure 5 In one or more of the illustrated embodiments, the dependence of the sensing performance on the thermal parameter τ can be reduced.

[0050] like Figure 4 As illustrated, the IR detector array 40 , 400 according to the present disclosure includes a sensing circuit portion 40 and a signal processing circuit portion 400 .

[0051] like Figure 4 As illustrated, the sensing circuit portion 40 of the IR detector array comprises a first “active” plurality of TMOS sensors T arranged in a matrix of n rows and m columns. 11 , T ij , T 1n , T n1 , T n2 , T nm , where the ijth TMOS sensor T ij As mentioned above Figure 1 The tuple identifier of the index in question of array 10; the TMOS sensor T of the i-th row 11 ,…,T 1n All sensors T with a common gate terminal (e.g., the first row) 11 ,…,T 1n G1) and a common source terminal S. The sensing circuit portion 40 also includes a bias node D B , the bias node D B is configured to "blind" the sensor M B is coupled to a bias branch VDD which is configured, for example, via a current mirror Mmir MB provides bias voltage, current mirror M mir MB is coupled to a first operational amplifier 406, which is configured to arrange the current mirror M mir 、M B The drain-source voltage value of a transistor (e.g., MOSFET) is set to a reference voltage V REF The sensing circuit portion 40 further includes a selective element array M 11 、M ij 、M 1n 、M n1 、M n2 、M nm , the selective element arrays comprising selective elements arranged in the same matrix arrangement of the sensor array 40, the ijth selective element array being identified by a tuple of indices, each selective element array being coupled to a sensor T in the sensor array 40 having a matching tuple of index values ij , for example, coupled to the sensor T 11 Selective arrangement of M 11 .

[0052] As illustrated herein, the sensor device includes an array of sense transistors (eg, T ) configured to provide a corresponding current signal indicative of a sensed physical quantity. 11 , T ij , T 1n , T n1 , T n2 , T nm ), wherein the sensing transistors in the sensing transistor array have corresponding control nodes (eg, G1, . . . , G n ) and a current channel path passing between corresponding first nodes and second nodes (S) common to the sensing transistors in the array. The sensor device also includes a signal processing circuit system that is coupled to the sensing transistor array and is configured to receive signals from the sensing transistor array (e.g., T) according to the method according to the present disclosure. 11 , T ij , T 1n , T n1 , T n2 , T nm ) collects the signal.

[0053] For example, the sensing transistors in the sensing transistor array include TMOS transistors configured to detect infrared rays.

[0054] As illustrated herein, an imaging camera (eg, 1000 ) is equipped with a sensor device according to the present disclosure.

[0055] like Figure 4As shown, the ijth selective arrangement M of the selective arrangements of the sensor array 40 ij Includes a pair of switches M ijA 、M ijB , the switch M ijA 、M ijB are configured to operate as a differential pair and have respective control terminals configured to receive a drive signal from the signal processing circuit portion 400 of the detector.

[0056] like Figure 4 As illustrated, the signal processing circuit portion 400 comprises a first multiplexing arrangement 402, the first multiplexing arrangement comprising an m-bit binary counter 401 and a first decoder 402, the m-bit binary counter 401 being configured to receive a first clock signal f CKm The m-bit signal is provided to the first shift register 402, and the m-bit decoder 402 is configured to generate a set of 2 m A control signal φ 11 、φ' 11 ,φ ij 、φ' ij ,φ 1m 、φ' 1m , the group 2 m The control signals include the first group 2 m-1 Signal φ 11 ,φ ij ,φ 1m and the second group 2 m-1 Signal φ' 11 、φ' ij 、φ' 1n , the first group 2 m-1 The signal is configured to drive the 11 M 11A ) of the first transistor of the pair of transistors (e.g., in Figure 4 The control terminal of the transistor marked with the suffix A in the second group 2 m-1 The signal is configured to drive the 11 M 11B ) of the pair of transistors (e.g., in Figure 4 The control terminal of the second group of signals φ' 11 、φ' ij 、φ' 1n is generated as the negation (eg, as an inverse copy) of a signal in the first set of signals, for example, φ' 11 = non(φ 11); These signals are used to selectively activate / deactivate the ijth sensor T in the sensor array 40 ij , as discussed below. The signal processing circuit portion 400 also includes a second multiplexing arrangement 403, 404, the second multiplexing arrangement including an n-bit binary counter 403 and a second decoder 404, the n-bit binary counter 403 being configured to receive the second clock signal f CKn The n-bit decoder 402 is configured to generate a set of 2 n A control signal φ 11 、φ' 11 ,φ ij 、φ' ij ,φ n1 、φ' n1 , the group 2 n The control signals include the first group 2 n-1 Signal φ 11 ,φ ij ,φ 1n and the second group 2 n-1 Signal φ' 11 、φ' ij 、φ' 1n , the first group 2 n-1 A signal driver is in each selective arrangement (eg, in selective arrangement M 11 M 11A ) of the pair of transistors (e.g., in Figure 4 The control terminals of the second group 2 n-1 The signal is configured to drive the 11 M 11B ) of the second transistor of the pair of transistors (e.g., in Figure 4 The second set of signals is generated as the negation (eg, as an opposite copy) of the signals in the first set of signals, for example, φ' 11 = non(φ 11 ); These signals are used to selectively activate / deactivate the ijth sensor T in the sensor array 40 ij , as discussed below.

[0057] like Figure 4 As illustrated, a single active IR sensor T may be selected using first decoder stages 401, 402 and second decoder stages 403, 404. ij , as discussed below.

[0058] like Figure 4As illustrated, the IR detector 40, 400 also includes an "active" pin D A and the "blind" pin D B , which are configured to provide respectively from the selected "active" sensor T ij and from the blind element M B The IR detector 40, 400 also includes a first amplifier stage 406, for example, having a non-inverting input node 406a, coupled to a reference voltage level V REF and a second amplifier stage 408, for example having a first non-inverting input node 408a, a second non-inverting input node 408b, coupled to a reference voltage level V REF The second bias node VDD is configured to be coupled to the first amplifier stage 406 and the second amplifier stage 408. The transistor M mir 、M B In a current mirror arrangement, transistor M mir 、M B The bias current generator I has a common gate terminal coupled to the output node 406d of the first operational amplifier 406 and has a drain-source current path and is coupled to the second non-inverting input node 408b of the second amplifier stage 408. BIAS Coupled to the current mirror device M mir 、M B and is configured to provide the ijth thermal sensor T ij A bias is provided, optionally with which a current mirror is formed, as discussed below.

[0059] For example: the first amplifier stage 406 is configured to set the drain-source voltage V of the transistor in the current mirror arrangement DS ; Blind pin D B Coupled to the current mirror arrangement M mir 、M B The transistor M in B and the second non-inverting node 408B of the second amplifier stage 408; the active pin D A is configured to selectively couple to the array T ij The target ijth sensor; and the second amplifier stage 408 is configured to place the transistor M in the current mirror arrangement mir 、M B The drain-source voltage V DS The value is set to the reference voltage V REF .

[0060] like Figure 4 As shown, the row-wise common gate nodes G1, ..., G n coupled to a common node, for example, a current mirror arrangement M mir 、M B Therefore, all sensors T in the sensing circuit section 40 are 11 ,…,T ij ,…,T nm It can be achieved by arranging M mir 、M B The "reflected" bias current I BIAS To bias.

[0061] like Figure 4 As shown, a plurality of IR sensors T in a reading sensing circuit portion 40 11 ,…,T ij ,…,T nm The target ijth sensor in (e.g., T 11 ) values ​​include:

[0062] The target ijth sensor (e.g., T 11 ) of the first control signal (e.g., φ 11 ) is set to a first value, for example, "0";

[0063] Get the value for the target ijth sensor (e.g., T 11 ) having a second value (eg, "1") opposite to the first value; a second control signal (eg, φ' 11 );

[0064] In response to a second control signal (eg, φ′) for the target ijth sensor 11 ) (e.g., φ' 11 =1), the target ijth sensor (e.g., T 11 ) is coupled to a first (e.g., drain) terminal of the second OTA 408, and in particular to a first non-inverting input 408a of the second OTA 408;

[0065] Therefore, for example, using the high gain of OTA 408, the current mirror arrangement M mir 、M B The blind transistor M in B and the selected target ijth sensor (e.g., T 11 ) is set at a reference voltage V REF ;as well as

[0066] For any ijth sensor T in the sensor array ijRepeat the above steps in sequence.

[0067] Note that when the ijth control signal (e.g., φ 11 ) is set to a first value (e.g., φ 11 = 0) in order to select the target ijth IR sensor (e.g., T 11 ), all other control signals are at a second value (eg, “1” or VDD).

[0068] like Figure 4 As shown, from the selected arrangement M 11 , …, M 1n The leakage current is reduced to, for example, equal to the (selected) selective arrangement (eg, M in the example above). 11A ) bias current I BIAS and on-resistance R on The value of the product of .

[0069] like Figure 4 As shown, the circuit block 410 includes a second amplifier stage 408, a blind transistor M B , the corresponding blind D B and active pin D A and the jth row sensor T of the sensor array 40 n1 ,…,T nm (and the corresponding optional arrangement M n1 , …, M nm ).

[0070] like Figure 5 As illustrated, the circuit block 410 may be replicated, and in an alternative embodiment 50, the replicas 410a, ..., 410n of each item (eg, row) are configured to execute multiple sensor T in parallel. 11 ,…,T ij ,…,T nm This facilitates increasing the speed of signal processing in the signal processing section 400, for example.

[0071] The method as exemplified herein includes: 11 , T ij , T 1n , T n1 , T n2 , T nm ) collects current signals, and the sensing transistors in the sensing transistor array are configured to provide corresponding current signals indicating the sensed physical quantity, wherein the sensing transistors in the sensing transistor array have corresponding control nodes (e.g., G1, . . . , G n) and a current channel path passing between corresponding first and second nodes (e.g., S) shared by sense transistors in the array.

[0072] For example, the method includes:

[0073] Set the bias voltage level (for example, V REF ) is applied to said respective first nodes of sense transistors in the array;

[0074] Select the sensing transistor array (eg, M ij ) in the sensing transistor (e.g., T ij );

[0075] The selected sensing transistor (eg, φ ij ) is decoupled from the bias voltage level while maintaining the sense transistor array except for the selected sense transistor (e.g., T ij ) outside the sensing transistor (e.g., φ 11 ,φ ij ,φ 1m ,φ n1 ,φ n1 ) is coupled to the bias voltage level (V REF );as well as

[0076] A respective first node of a selected sense transistor in the sense transistor array is coupled to an output node (eg, D A ), and collect an output current signal from the output terminal.

[0077] As illustrated herein, the method further includes sequentially selecting different sense transistors (eg, T ij ), sequentially collecting current signals provided from the selected different sensing transistors.

[0078] As illustrated herein, the method further includes providing an arrangement of a plurality of matching transistors in a sensing transistor array (eg, M 11 、M ij 、M 1n 、M n1 、M n2 、M nm ), the arrangement of matched transistors in the sensing transistor array is configured to selectively couple the respective first nodes of the sensing transistors to a bias voltage source (e.g., V REF ) or (for example, φ 11 ,φ 1m ,φ n1 ,φ n1 ) is coupled to the output node.

[0079] The selected sensing transistor (eg, T ij ) and the bias voltage level (e.g., V REF ) decoupling (e.g., φ ij ), while maintaining the sensing transistors in the sensing transistor array other than the selected sensing transistor (eg, φ 11 ,φ ij ,φ 1m ,φ n1 ,φ n1 ) to a bias voltage level includes: coupling a selected sensing transistor (e.g., T ij ) corresponding selectivity (transistor) arrangement (e.g., M ij ) of the selected control signal (e.g., φ ij ) is set to a first value, and multiple control signals (eg, φ 11 ,φ 1m ,φ n1 ,φ n1 ) in addition to the selected control signal (φ ij ) is set to a second value opposite to the first value.

[0080] For example, the method includes:

[0081] Provide at least one clock signal (e.g., f CKn 、f CKm );

[0082] generating a binary signal (eg, 401, 403) indicating a number of cycles of at least one clock signal; and

[0083] A control signal (eg, 402, 404) is generated based on a binary signal indicating a number of cycles of at least one clock signal.

[0084] As exemplified herein, the method comprises:

[0085] At least one reference sense transistor (eg, M ) configured to provide a blind reference current is provided. B );as well as

[0086] The selected sensing transistor (eg, T ij ) is coupled to at least one reference sense transistor, subtracts the blind reference current from the corresponding current signal, thereby generating a corresponding normalized current signal, and directs a selected sense transistor (e.g., T ij ) is coupled to an output node (e.g., D A ), from which the corresponding normalized current signals are collected.

[0087] like Figure 5 One or more of the illustrated embodiments employs a group of sensors T that simultaneously select items or entries (eg, rows) belonging to the sensing circuit portion of array 50. 11 ,…,T 1m possibility, reducing the time to convert the drain-source current value into a pixel value.

[0088] like Figure 5 As illustrated, the array 50 includes a plurality of sensors (eg, T 11 ,…,T 1n ) is repeated as Figure 4 Copies 410a, ..., 410n of circuit block 410 are illustrated.

[0089] like Figure 5 As illustrated, each row of the sensor array 50 includes a corresponding blind sensor M B1 , …, M Bj and operational amplifiers 408a, ..., 408n.

[0090] For example, the array 50 includes: a plurality of blind pixels M in each j-th row of the array 50 Bj A plurality of second amplifier stages 408a, ..., 408n, a second amplifier stage for each j-th row of the array 50; a plurality of active pins D A1 ,…,D An and multiple blind pins D B1 ,…,D Bn ; and multiple selective arrangements M j1 、M jn , coupled to the corresponding IR sensor T of the array 50 j1 ,…,T jn , amplifier stages 408a, ..., 408n and corresponding active pins D Aj and blind pin D Aj .

[0091] For example, selecting the jth row of sensors in the array 5 comprises setting all control signals to a first value, such as “0”, for example, Φ 11 =Φ 21 =... =Φ j1 =0; therefore, all sensors T in row j are n1 ,…,T nm coupled to the corresponding j-th second amplifier stage (eg, 408n) and the corresponding active pin D Aj , thereby generating multiple read signals to the user circuit 60.

[0092] For example, the active pixels T in each i-th row can be selected ij and connect it to row D AjThe output drain of the remaining unselected pixels T 11 ,…,T 1n With the same current and V DS Bias on.

[0093] Note that when the jth row is selected, the remaining IR sensors in the array 50 are connected to the reference voltage V REF Keep biased so that the corresponding blind pin D B1 ,…,D Bj ,…,D Bm provides a "blind" (i.e., during inactivity) current value at the active pin D A1 ,…,D Aj ,…D An Provides active current.

[0094] As illustrated herein, a method includes providing a transistor configured to sense a reference transistor (eg, M B ) collects at least one additional output terminal (e.g., D B ).

[0095] As illustrated herein, a sensing transistor array (eg, T 11 , T ij , T 1n , T n1 , T n2 , T nm ) is a planar array, in which the sensing transistors in the sensing transistor array and the matching selective arrangement (eg, M ij ) is identified by an index tuple.

[0096] For example, the method includes:

[0097] Provide a bias voltage level (e.g., V REF ) and connecting the corresponding first node of the sensing transistor in the sensing transistor array and at least one reference transistor (eg, M B ) is coupled to the bias voltage level;

[0098] Select the sensor array (for example, M ij ) in each row of the sensing transistor (e.g., T ij );

[0099] The selected sensing transistors (eg, φ ij ) is decoupled from the bias voltage level while maintaining the sensing transistors (eg, φ 11 ,φ ij ,φ 1m ,φ n1,φ n1 ) is coupled to a bias voltage level; and

[0100] Each of the selected sense transistors in each row of the sense transistor array is coupled to a plurality of output nodes (eg, D A1 ,…,D Am ) and collect corresponding current signals therefrom in parallel.

[0101] It should also be understood that the various individual implementation options illustrated in the drawings throughout this specification are not necessarily intended to be employed in the same combination illustrated in the drawings. Thus, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the attached drawings.

[0102] Without prejudice to the underlying principle, the details and embodiments may vary, by way of example only, with respect to what is described, even significantly, without departing from the scope of protection.

[0103] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0104] The scope of protection is determined by the appended claims.

Claims

1. A method for collecting a current signal from a sense transistor in a sense transistor array, the current signal being indicative of a sensed physical quantity, wherein the sense transistors in the sense transistor array have respective control nodes and current channel paths passing between respective first and second nodes common to the sense transistors in the array, the method comprising: applying a bias voltage level to the first nodes of all of the sense transistors in the array; selecting a sensing transistor in the sensing transistor array; decoupling the first node of the selected sense transistor from the bias voltage level while maintaining coupling of the first nodes of the sense transistors in the sense transistor array other than the selected sense transistor to the bias voltage level; coupling the first node of the selected sense transistor to an output node; as well as An output current signal is collected from the output node.

2. The method of claim 1 , wherein selecting comprises sequentially selecting different sense transistors in the sense transistor array, the first nodes of the different sense transistors being decoupled from the bias voltage level, and wherein collecting comprises sequentially collecting the current signal provided from each of the sequentially selected sense transistors.

3. The method of claim 1 , wherein the arrangement of the plurality of matched transistors in the sensing transistor array is configured to selectively couple the respective first nodes of the sensing transistors to an output node and a bias voltage source providing the bias voltage level in an alternative manner based on a plurality of control signals, wherein decoupling the selected sensing transistor from the bias voltage level while maintaining coupling of the first nodes of the sensing transistors in the sensing transistor array other than the selected sensing transistor to the bias voltage level comprises: The selected control signal of the corresponding selective arrangement matched with the selected sensing transistor is set to a first value, and the control signals other than the selected control signal among the plurality of control signals are set to a second value opposite to the first value.

4. The method according to claim 3, comprising: providing at least one clock signal; generating a binary signal indicative of a number of clock cycles of the at least one clock signal; as well as The control signal is generated based on the binary signal indicating the number of clock cycles of the at least one clock signal.

5. The method of claim 1 , wherein at least one reference sensing transistor is configured to provide a blind reference current, the method further comprising: coupling a selected sense transistor in the array to the at least one reference sense transistor; subtracting the blind reference current from the current signal of the selected sense transistor; as well as generating a normalized current signal resulting from said subtraction; The coupling includes coupling the normalized current signal to the output node to be collected as the output current signal. 6 . The method of claim 5 , further comprising outputting the blind reference current from the reference sense transistor to at least one additional output terminal for collection.

7. The method of claim 5, wherein the sensing transistor array is a planar array, the positions of the sensing transistors in the sensing transistor array and the positions of the matching selective arrangements are identified by index tuples, and wherein the method further comprises: providing a bias voltage level and coupling the respective first nodes of the sense transistors in the sense transistor array and the at least one reference sense transistor to the bias voltage level; selecting a sense transistor in each row of the sense transistor array; decoupling selected sense transistors in each row from the bias voltage level while maintaining coupling of the sense transistors in the sense transistor array other than the selected sense transistors to the bias voltage level; as well as Each of the selected ones of the sense transistors in each row of the sense transistor array is coupled to a respective one of a plurality of output nodes, and a respective current signal is collected in parallel from the respective output node.

8. A sensor device comprising: a sense transistor array configured to provide respective current signals indicative of a sensed physical quantity, wherein sense transistors in the sense transistor array have respective control nodes and current channel paths passing between respective first and second nodes common to the sense transistors in the array; as well as A circuit system is coupled to the sense transistor array and is configured to collect signals from sense transistors in the sense transistor array by: applying a bias voltage level to the first nodes of all of the sense transistors in the array; selecting a sensing transistor in the sensing transistor array; decoupling the first node of the selected sense transistor from the bias voltage level while maintaining coupling of the first nodes of sense transistors in the sense transistor array other than the selected sense transistor to the bias voltage level; as well as coupling the first node of the selected sense transistor to an output node; as well as An output current signal is collected from the output node. 9 . The sensor device of claim 8 , wherein the sensing transistors in the sensing transistor array include thermal MOS (TMOS) transistors configured to detect infrared rays. 10 . The sensor device according to claim 8 , wherein the circuit system is further configured to sequentially select different sensing transistors in the sensing transistor array, and sequentially collect current signals provided from the selected different sensing transistors.

11. The sensor device of claim 8, wherein the arrangement of the plurality of matched transistors in the sensing transistor array is configured to selectively couple the respective first nodes of the sensing transistors to a bias voltage source and the output node in an alternative manner based on a plurality of control signals, and wherein, The circuitry to decouple a selected sense transistor from the bias voltage level while maintaining coupling of sense transistors in the sense transistor array other than the selected sense transistor to the bias voltage level is configured to: The selected control signal of the corresponding selective arrangement matched with the selected sensing transistor is set to a first value, and the control signals other than the selected control signal among the plurality of control signals are set to a second value opposite to the first value.

12. The sensor device of claim 11, wherein the circuit system is further configured to: providing at least one clock signal; generating a binary signal indicative of a number of clock cycles of the at least one clock signal; and The control signal is generated based on the binary signal indicating the number of clock cycles of the at least one clock signal.

13. The sensor device according to claim 8, further comprising: at least one reference sense transistor configured to provide a blind reference current, and wherein the circuit system is further configured to: coupling a selected sense transistor in the array to the at least one reference sense transistor; subtracting the blind reference current from the current signal of the selected sense transistor; as well as generating a normalized current signal as a result of said subtracting; The coupling includes coupling the normalized current signal to the output node to be collected as the output current signal.

14. The sensor device according to claim 13, further comprising: At least one further output terminal is configured to collect the blind reference current from the reference sense transistor.

15. The sensor device of claim 13, wherein the sensing transistor array is a planar array, positions of sensing transistors in the sensing transistor array and positions of matching selective arrangements are identified by index tuples, and wherein the circuit system is further configured to: providing a bias voltage level and coupling the respective first nodes of the sense transistors in the sense transistor array and the at least one reference sense transistor to the bias voltage level; selecting a sense transistor in each row of the sense transistor array; decoupling selected sense transistors in each row from the bias voltage level while maintaining coupling of sense transistors in the sense transistor array other than the selected sense transistors to the bias voltage level; as well as Each of the selected sense transistors in each row of the sense transistor array is coupled to a respective output node of a plurality of output nodes, and a respective current signal is collected in parallel from the respective output node.

16. An imaging camera equipped with a sensor device according to claim 9.

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