Bulk memory initialization

Abstract

The present disclosure relates to techniques for bulk initializing memory in a computer system. The computer system includes a processor core including an access unit and a last level cache in communication with the processor core. The last level cache is configured to receive bulk store operations from the access unit. Each bulk store operation includes a physical address in the memory to be initialized. The last level cache is configured to send a plurality of write transactions to the memory for each bulk store operation to perform bulk initialization of the memory for each bulk store operation. The last level cache is configured to track a status of the bulk store operations.

Description

Technical Field

[0001] This disclosure generally relates to memory initialization in a computing system. Background Technology

[0002] Data movement is becoming a major performance bottleneck in modern processors. To perform any operation on data residing in main memory, the central processing unit (CPU) first issues a series of commands to main memory (such as DRAM modules) via an off-chip bus, typically called a memory channel. Main memory responds by sending data to the CPU, which is then placed into a cache. This process of moving data from main memory to the CPU introduces long latency and consumes a significant amount of energy.

[0003] Memory initialization is the process of establishing known values ​​in memory. Initialization of a memory region can occur in response to the allocation of that region to, for example, a computer program or operating system. In some cases, memory is initialized to all zeros. Main memory initialization is generally broken down into a series of store instructions. Each store instruction initializes a small region of main memory. For example, each store instruction can initialize a main memory region of size equal to a cache line. This series of store instructions can be executed in the CPU execution unit. Each store instruction can fetch a cache line into the cache, modify the cache line, and write the cache line back to main memory. In these operations, if a line fetched into the cache is not subsequently reused by the CPU, the cache is not being used properly. Summary of the Invention

[0004] According to one aspect of this disclosure, a computer system for initializing memory is provided. The computer system includes a processor core, which includes a central processing unit (CPU), an access unit, and an internal cache. The computer system includes a last-level cache in communication with the processor core. The last-level cache is configured to receive bulk memory operations from the access unit. Each bulk memory operation includes a physical address in memory to be initialized. The last-level cache is configured to send multiple write transactions to the memory for each bulk memory operation to perform bulk initialization of the memory for each bulk memory operation. The last-level cache is configured to track the state of the bulk memory operations.

[0005] Optionally, in the foregoing aspects, the last-level cache is also configured to maintain cache coherence in the cache hierarchy of the computer system when performing a bulk initialization of memory for each bulk store operation.

[0006] Optionally, in any of the foregoing aspects, the access unit includes a bulk storage combination buffer, and the access unit is configured to store the state of the bulk storage operation in the bulk storage combination buffer.

[0007] Alternatively, in any of the foregoing aspects, the access unit is also configured to bypass the internal cache and send a batch storage operation directly to the last-level cache.

[0008] Optionally, in any of the foregoing aspects, the access unit is also configured to track pending bulk store operations. Each bulk store operation is associated with a region of memory to be initialized. The access unit is also configured to prevent newer loads of memory associated with any region of memory associated with any pending bulk store operation.

[0009] Alternatively, in any of the foregoing aspects, the access unit is configured to, in response to a final cache indication that a batch storage operation is complete, set the pending status of the batch storage operation to complete, or remove the batch storage operation from the batch storage combination buffer.

[0010] Optionally, in any of the foregoing aspects, the last-level cache is also configured to store information about the complete state associated with each bulk store operation. The complete state indicates whether the memory region initialized by the bulk store operation is complete and has its initialization value. The last-level cache is also configured to set the complete state to incomplete in response to another processor core writing to the memory region associated with the bulk store operation.

[0011] Optionally, in any of the foregoing aspects, the access unit is further configured to invalidate the entry for the first batch store operation in the batch store combination buffer in response to an integrity status indicating that the status is incomplete. The access unit is also configured to keep the corresponding entry for the second batch store operation in the batch store combination buffer as a valid entry in response to an integrity status indicating that the status is complete.

[0012] Alternatively, in any of the foregoing aspects, the access unit is further configured to respond to a newer load instruction that loads from that region by providing a known initialization value if the region of memory initialized by the completed bulk storage operation is still intact.

[0013] Alternatively, in either of the foregoing aspects, each batch store operation initializes a region of the memory to all zeros.

[0014] Alternatively, in either of the foregoing aspects, each write transaction initializes a region of memory with a cache line size.

[0015] Alternatively, in either of the foregoing aspects, each batch storage operation initializes a region of memory with a page size.

[0016] Alternatively, in any of the foregoing aspects, the computer system further includes logic configured to create a single batch storage operation from multiple storage instructions, each storage instruction being configured to initialize a region of cache line size of the memory.

[0017] According to another aspect of this disclosure, a method for initializing memory in a computer system is provided. The method includes receiving a bulk store operation from an access unit in a processor core of the computer system at the last-level cache in a cache hierarchy. The method includes performing bulk initialization of the memory for each bulk store operation, including sending multiple write transactions from the last-level cache to the memory for each bulk store operation. The method includes tracking the state of the bulk store operations.

[0018] According to another aspect of this disclosure, a computer system for initializing memory is provided. The computer system includes main memory, a central processing unit, an access unit, and a cache hierarchy including a last-level cache. The access unit includes access unit means for tracking the state of page memory operations. Each page memory operation includes a physical address in the main memory. The last-level cache includes means for sending multiple write transactions to the main memory for each page memory operation to initialize a page in the main memory. The last-level cache includes last-level cache means for tracking the state of page memory operations and reporting the state to the access unit.

[0019] The Summary Section is provided to introduce, in a simplified form, some concepts that will be further described in the following Detailed Description. The Summary Section is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter. The claimed subject matter is not limited to embodiments that address any or all of the drawbacks mentioned in the Background Section. Attached Figure Description

[0020] Various aspects of this disclosure are illustrated by way of example and are not limited to the accompanying drawings, in which like reference numerals indicate like elements.

[0021] Figure 1A This is a block diagram of one embodiment of a computing system capable of performing bulk memory initialization.

[0022] Figure 1B This is a block diagram of an embodiment of a final-level cache that forms multiple write transactions from a single batch storage operation.

[0023] Figure 2 Depicting Figure 1B An example of a batch storage engine in [the context of the application].

[0024] Figure 3 An embodiment of a bulk storage operation buffer that may exist in a bulk storage engine is described.

[0025] Figure 4 An embodiment of the access unit is described.

[0026] Figure 5 A flowchart illustrating one embodiment of the process for performing bulk initialization of memory is provided.

[0027] Figure 6 A flowchart depicts an embodiment of the process for performing a bulk storage operation at an access unit.

[0028] Figure 7 A flowchart depicts an embodiment of the action process at the access unit when a bulk storage operation is initiated.

[0029] Figure 8 An example of the process of tracking the state of a batch storage operation at the final cache level is described.

[0030] Figure 9 A flowchart depicts one embodiment of the process of initializing memory for a bulk storage operation at the final cache level.

[0031] Figure 10 A flowchart depicts an embodiment of the process of maintaining cache coherence at the last-level cache when processing bulk storage operations.

[0032] Figure 11 A flowchart depicts one embodiment of the actions performed at the access unit when a bulk storage operation is completed.

[0033] Figure 12 A flowchart depicts an embodiment of the process by which an access unit handles loading while or after a bulk storage operation is pending. Detailed Implementation

[0034] This disclosure will now be described with reference to the accompanying drawings, which generally relate to bulk initialization of memory in a computing system. As used herein, "bulk initialization of memory" refers to the initialization of a memory region larger than a cache line. A cache line is the basic unit of cache storage and may also be referred to as a cache block. As an example, bulk initialization may be used to initialize a region of four kilobytes in size (here, a kilobyte is defined as 1024 bytes). In one embodiment, an access unit in the processor core sends a bulk store operation to the last-level cache. The last-level cache is configured to send multiple write transactions to memory for each bulk store operation to perform bulk initialization of memory. The last-level cache is configured to track the state of the bulk store operations. The last-level cache is configured to maintain cache coherence across the cache hierarchy while performing bulk initialization of memory for each bulk store operation. Bulk store operations can eliminate the need for a large number of store transactions at the access unit, thus saving significant time. Bulk store operations can eliminate the need to transfer a series of store transactions through the cache hierarchy, thus saving significant time. When performing a bulk initialization of memory, bulk storage operations can reduce or eliminate the need to cache data in the cache hierarchy, thereby saving significant time and reducing complexity.

[0035] In one embodiment, the access unit has a bulk store combination buffer configured to store the state of bulk store operations. The last-level cache can report the state of the bulk store operations to the access unit. In one embodiment, the access unit prevents newer loads associated with any region of memory related to any pending bulk store operation.

[0036] It should be understood that embodiments of this disclosure may be implemented in many different forms, and the scope of the claims should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the inventive concept to those skilled in the art. In fact, this disclosure is intended to cover alternatives, modifications, and equivalents to these embodiments, all of which are included within the scope and spirit of this disclosure as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of embodiments of this disclosure in order to provide a thorough understanding. However, it will be apparent to those skilled in the art that embodiments of this disclosure may be practiced without these specific details.

[0037] Figure 1AThis is a block diagram of one embodiment of a computing system 100. The computing system 100 is configured to perform bulk memory initialization. The computing system 100 includes a processor core 102, a last-level cache (LLC) 104, and main memory 108. Main memory 108 is optional. In one embodiment, main memory 108 is volatile memory, such as DRAM or SRAM. However, main memory 108 is not required to be volatile memory.

[0038] Processor core 102 includes at least one central processing unit (CPU) 110, a load storeunit (LSU) 112, and an internal cache 114. The term internal cache 114 refers to a cache located on the same semiconductor die (chip) as the CPU 110. In one embodiment, internal cache 114 includes L1 cache and L2 cache. Therefore, internal cache 114 may include more than one level of cache. Computing systems can use caches to improve computing performance. For example, a computing system can store data that it needs to access more frequently in a smaller, faster cache memory instead of storing data in a slower, larger memory (e.g., main memory 108).

[0039] The computing system 100 has a cache hierarchy, with these caches ordered by cache levels as referred to herein. Typically, cache levels are numbered from the highest to the lowest level. There may be two, three, four, or even more levels in the cache hierarchy. In this document, by convention, the lowest number refers to the highest level cache, with lower levels receiving higher numbers. For example, the highest level cache in the hierarchy may be called the L1 cache. Lower cache levels may be called L2, L3, L4, etc. In one embodiment, internal cache 114 has an L1 cache, which is a small, fast cache located close to the central processing unit 110. The lowest level cache is referred to as the Last Level Cache (LLC) 104.

[0040] In one embodiment, computing system 100 performs a bulk initialization of main memory 108. In some conventional techniques, processor core 102 initializes main memory 108 by sending commands to initialize a region of cache line size. In one embodiment, processor core 102 sends a single bulk store operation to last-level cache 104 to initialize a large region in main memory 108. As an example, the size of this region could be four kilobytes. In one embodiment, the bulk store operation is used to initialize a region of page size. Here, a page is defined as the smallest unit of data used for memory management in the virtual address space. A page is typically described by a single entry in a page table. For example, one page may be equivalent to 64 cache lines. Therefore, as an example, processor core 102 sends one bulk store operation instead of 64 store transactions. Furthermore, access unit 112 can bypass the internal cache 114 (e.g., L1 cache, L2 cache) in processor core 102 and send bulk store operations directly to last-level cache 104. Bypassing the internal cache 114 improves efficiency. When the size of the memory region being initialized is one page, a bulk store operation can be called a page store operation. Typically, bulk store operations are used to initialize memory regions that are multiple cache lines in size.

[0041] The last-level cache 104 forms multiple write transactions from a single batch store operation. The last-level cache 104 is configured to send multiple write transactions to main memory 108 for each batch store operation to perform batch initialization of main memory 108 for each batch store operation. The last-level cache 104 is configured to track the status of batch store operations received from access unit 112. Figure 1B Further details of one embodiment of the final-level cache are described in the text.

[0042] Note that main memory 108 can... Figure 1A The processor core 102 and other processors shown are shown. Figure 1A (Not shown in the text) is shared between [these memory regions]. Such other processors might attempt to access a region of main memory 108 during bulk initialization. In other words, such an access might leave the region in a state where it is uncertain whether the region still contains its initialized value. Here, "region intact" means that the region still contains its initialized value. The final-level cache 104 is configured to track such potential accesses and change the state from intact to incomplete if necessary. This state can be reported to the access unit 112.

[0043] Figure 1BAn embodiment of a last-level cache 104 that forms multiple write transactions from a single batch store operation is depicted. The last-level cache 104 has a batch store engine 118 and a cache pipeline 120. The batch store engine 118 and the cache pipeline 120 can be implemented in hardware. In one embodiment, the batch store engine 118 includes combinational and sequential logic. In one embodiment, the cache pipeline 120 includes combinational and sequential logic. In one embodiment, to initiate a batch initialization of main memory 108, an access unit 112 in processor core 102 sends a batch store operation to the last-level cache 104. In one embodiment, the batch store engine 118 generates multiple write transactions for the batch store operation and sends the multiple write transactions to the cache pipeline 120. The cache pipeline 120 processes each write transaction. In one embodiment, while the batch store operation is being processed, the cache pipeline maintains cache coherence in the cache of computer system 100. A write transaction can be a cache line-sized transaction.

[0044] Figure 2 Depicting Figure 1B This is one embodiment of the batch storage engine 118 depicted. The batch storage engine 118 is configured to perform batch initialization of a region in main memory 108 for each batch storage operation. The batch storage engine 118 has a write transaction former 202 configured to form multiple write transactions for each batch storage operation. In one embodiment, each write transaction is for a region of cache line size in main memory 108. In one embodiment, the write transaction former 202 sends write transactions to cache pipeline 120, which sends a corresponding number of write transactions to main memory 108.

[0045] Batch storage engine 118 has a batch storage state tracker 204 configured to track the state of each batch storage operation. Batch storage state tracker 204 maintains the state tracking in batch storage operation buffer 206. Write transaction former 202 and batch storage state tracker 204 may be part of a cache controller in last-level cache 104. In one embodiment, write transaction former 202 is implemented in hardware. For example, write transaction former 202 may be implemented using sequential logic and / or combinational logic. In one embodiment, batch storage state tracker 204 is implemented in hardware. For example, batch storage state tracker 204 may be implemented using sequential logic and / or combinational logic. For discussion purposes, batch storage operation buffer 206 is depicted in batch storage engine 118. Batch storage operation buffer 206 may be implemented in a portion of memory in last-level cache 104 for cache entries. Further details of one embodiment of batch storage operation buffer 206 are provided in... Figure 3 As shown in the image.

[0046] Figure 3 An embodiment of a bulk store operation buffer 206 is depicted. When a bulk store engine 118 receives a bulk store operation, the bulk store engine 118 creates a new entry in the bulk store operation buffer 206. Each bulk store operation includes a physical address (PA) 304, which is the starting physical address to be initialized in memory (e.g., main memory 108). Figure 3 There are two entries in the bulk store operation. One entry has a physical address of 0x8000 (hexadecimal or HEX). The other entry has a physical address of 0x9000. The size of the region to be initialized in memory can be a default value. Therefore, it is not necessary to specify the size in the bulk store operation. Optionally, the size of the region can be specified in the bulk store operation. For ease of illustration, an example of a size of 4 kilobytes (or 1000 HEX) will be discussed. Therefore, one bulk store operation can be used to initialize the physical address between 0x8000 and 0x8FFF (inclusive). The other bulk store operation can be used to initialize the physical address between 0x9000 and 0x9FFF (inclusive).

[0047] While processing each batch storage operation, the batch storage engine 118 tracks the status of the batch storage operation. The column labeled "Progress" 306 is used to track how far the batch storage operation has progressed. As described above, the batch storage engine 118 forms multiple write transactions for each batch storage operation. The progress column 306 is used to track how many write transactions have been completed. Figure 3 In this context, one batch storage operation has completed, while another has completed 53 write transactions. For example, for a batch storage operation, there might be 64 write transactions for main memory 108.

[0048] While processing each batch store operation, the batch store engine 118 also monitors whether the region in main memory 108 associated with the batch store transaction is affected by any other storage in main memory 108. For example, during the batch initialization of a region in main memory 108, a portion of that region may be written to. This write may originate from a processor core other than the processor core that initiated the batch store operation. A column marked "Complete" (each entry referred to as the complete flag 308) is used to track whether a region is complete.

[0049] A column marked "valid" (each entry referred to as LLC valid flag 302) is used to track whether the entry is still valid. In one embodiment, if the complete flag 308 is set to zero, the entry for the bulk store operation is invalidated. Otherwise, the entry can be retained in the bulk store operation buffer 206 after the bulk store operation has completed.

[0050] Figure 4 An embodiment of access unit 112 is depicted. Access unit 112 has a storage queue 402, a storage combination buffer 404, and a bulk storage combination buffer 406. The storage queue 402, storage combination buffer 404, and bulk storage combination buffer 406 can be implemented in the memory of processor core 102. A bulk storage manager 408 is configured to maintain the bulk storage combination buffer 406. The bulk storage manager 408 can be implemented in hardware.

[0051] Multiple entries 402-1 to 402-8 are depicted on memory queue 402. These entries can be executed in the order of entries 402-1 to 402-8. These entries correspond to the instructions in Table I. However, since instruction I4 is a load instruction, it is not represented on memory queue 402. In the store instructions in Table I, the physical address in main memory for storing a value can be derived from register R1. In some cases, register R1 contains a virtual address, which is translated into a physical address in main memory 108.

[0052]

[0053] Entry 402-1 stores the operation (St0) corresponding to instruction I0 in Table I. Therefore, entry 402-1 is the operation of storing the contents of register R8 into physical address 0x1000 in main memory 108. Entry 402-2 stores the operation (St1) corresponding to instruction I1 in Table I. Therefore, entry 402-2 is the operation of storing the contents of register R9 into physical address 0x1040 in main memory 108. Entry 402-3 stores the operation (St2) corresponding to instruction I2 in Table I. Therefore, entry 402-3 is the operation of storing the contents of register R9 into physical address 0x1080 in main memory 108. These three storage operations (St0, St1, St2) can be conventional storage operations, each storing into a memory region equal to 64 bytes. This region can be larger or smaller (e.g., 32 bytes or 128 bytes). In one embodiment, 64 bytes is the size of a cache line. A cache line can be larger or smaller (e.g., 32 bytes or 128 bytes).

[0054] Entries 402-4 correspond to instruction I3 in Table I and store a bulk store operation (BlkSt0). The bulk store operation has a physical address of 0x8000. In one embodiment, the bulk store operation is used to initialize a region of 0x1000 in main memory 108. In another embodiment, the bulk store operation is used to initialize a region of page size in main memory 108. For example, the page size could be 4 kilobytes (or 1000 HEX). Note that in Table I, instruction I3 specifies register R3, indicating that the physical address can be obtained based on the contents of register R3. In some embodiments, register R3 contains a virtual address that is translated to a physical address in main memory 108. Instruction I3 does not contain an operand of data to be stored at the physical address, as this data may be implied by the DC ZVA PG instruction. In one embodiment, the DC ZVA PG instruction implies that the contents of the memory will be zeroed out. However, the DC ZVA PG instruction can be used to imply some other mode, such as initializing the memory to all 1s. Optionally, an operand can be provided in the DC ZVA PG instruction to, for example, provide a mode to be written to memory. For example, a second register can be specified in the DC ZVA PG instruction, where the contents of the second register contain the pattern to be written to memory. Note that this pattern may be repeated multiple times because the size of the region to be initialized in memory is typically much larger than the register.

[0055] There is no entry for instruction I4 in storage queue 402 because instruction I4 is a load instruction, not a store instruction. However, access unit 112 may have a load queue where a load operation for instruction I4 can be placed. Figure 4 (Not shown in the diagram). In one embodiment, the bulk storage manager 408 prevents a newer load of a memory region that is being initialized by a bulk storage operation. Therefore, the bulk storage manager 408 may prevent the execution of instruction I4 because there are pending bulk storage operations on the memory region to be loaded by instruction I4.

[0056] Entry 402-5 stores the operation (St3) corresponding to I5 in Table I. Therefore, entry 402-5 is the operation that stores the contents of register R9 at physical address 0x10c0 in main memory 108. Entry 402-6 stores the bulk store operation (BlkSt1) corresponding to instruction I6 in Table I. The bulk store operation BlkSt1 has a physical address of 0x9000, which is determined based on the contents of register R1 plus 0x1000 (see Table I). As mentioned above, the contents of register R1 can be a virtual address, which is translated into a physical address. Entry 402-7 stores the bulk store operation (BlkSt2) corresponding to instruction I7 in Table I. The bulk store operation BlkSt2 has a physical address of 0xa000, which is determined based on the contents of register R1 plus 0x2000 (see Table I). Entry 402-8 stores the bulk store operation (BlkSt3) corresponding to instruction I8 in Table I. The bulk storage operation BlkSt3 has a physical address of 0x8000, which is determined based on the contents of register R1 (see Table I).

[0057] Storage combination buffer 404 is used to track memory operations. The entries for the first three regular memory operations (St0, St1, St2) are represented in storage combination buffer 404, as indicated by the physical addresses. Storage combination buffer 404 has columns indicating whether the corresponding memory operation resulted in a cache hit. Storage combination buffer 404 also has columns indicating whether the entry is currently valid.

[0058] Batch store combination buffer 406 is used to track batch store operations. As indicated by the physical addresses in physical address column 424, the entries for the first three batch store operations (BlkSt0, BlkSt1, BlkSt2) are represented in batch store combination buffer 406. Batch store combination buffer 406 has a column indicating whether the corresponding batch store operation is pending (called the pending flag 426). Batch store combination buffer 406 also has a column indicating whether the entry is currently valid (called the LSU valid flag 422).

[0059] The bulk storage manager 408 is configured to maintain the bulk storage combination buffer 406. When a bulk storage operation is initiated, the bulk storage manager 408 can add entries to the bulk storage combination buffer 406. The bulk storage manager 408 can update the status (e.g., pending, valid) in response to status reports from the bulk storage engine 118 in LLC 104. This will be discussed in conjunction with the following... Figure 12 Further details of one embodiment of maintaining the bulk store combination buffer 406 are described. In one embodiment, the bulk store manager 408 prevents newer loads of any area of ​​main memory 108 where bulk store operations are pending. This will be discussed in conjunction with the following... Figure 12 Further details of one embodiment of preventing newer loads are described. The bulk storage manager 408 may be implemented in hardware. In one embodiment, the bulk storage manager 408 includes combinational logic and sequential logic.

[0060] Figure 5 A flowchart illustrating one embodiment of a batch initialization process 500 for performing memory is provided. Process 500 can be used in computer system 100 to initialize main memory 108. In one embodiment, process 500 is performed by a batch storage engine 118 in LLC 104. Reference will be made to process 500 in the discussion. Figure 1A The components in; however, process 500 is not limited to Figure 1A For ease of explanation, steps 504-506 in process 500 are described in a specific order, but they do not necessarily occur in the order depicted. Therefore, steps 504-506 may occur in different orders. Furthermore, steps 504-506 may be executed simultaneously.

[0061] Step 502 includes receiving a bulk store operation at the final level cache (LLC) 104 in the computer system 100. In one embodiment, processor core 102 sends the bulk store operation to LLC 104. In another embodiment, access unit 112 sends the bulk store operation to LLC 104. The bulk store operation may bypass other caches, such as internal cache 114 (e.g., L1 cache and L2 cache). Therefore, other caches can be unloaded during the bulk store operation.

[0062] Step 504 includes performing a bulk initialization of the memory for the bulk storage operation. In one embodiment, bulk initialization of main memory 108 is performed. In one embodiment, the result of bulk initialization is to zero out a memory region. In other words, after bulk initialization, the contents of the memory region may be all zeros. However, the result of bulk initialization may be a different pattern. For example, after bulk initialization, the contents of the memory region may be all 1s. The result may be a different pattern, such as alternating 1s and 0s. (Refer to...) Figure 9 Further details of one embodiment of performing bulk initialization of memory are shown and depicted.

[0063] Step 506 includes tracking the status of the bulk store operation. In one embodiment, the bulk store engine 118 updates the bulk store operation buffer 206. For example, the bulk store engine 118 may update the progress column, the complete column, and the valid column. See reference. Figure 8 Further details of an embodiment for tracking the state of a batch initialization operation are shown and depicted.

[0064] Figure 6A flowchart illustrating one embodiment of a batch store operation process 600 executed at access unit 112 is provided. Process 600 can be initiated when an instruction executed in processor core 102 instructs that a batch store operation be performed.

[0065] Procedure 600 describes two ways in which a bulk store operation can be initiated. Step 602a describes option A, where the bulk store operation is derived from a bulk store instruction from a set of instructions executed in processor core 102. Table I shows a set of instructions containing four bulk store instructions (instructions I3, I6, I7, and I8).

[0066] Step 602b describes option B, where a bulk store operation is formed based on multiple store instructions. Each of these store instructions stores the same value into memory. For example, each store instruction can zero out the memory. However, each of these store instructions can be a different region to be stored in memory. In general, store instructions can be configured to store into contiguous regions of memory. Table II describes example store instructions that can form a bulk store operation. Forming a single bulk store operation from multiple store instructions can be called code morphing. In one embodiment, the bulk store manager 408 is capable of performing code morphing. For ease of illustration, the instructions in Table II are numbered from I0 to I63, but these instructions are different from those in Table I.

[0067]

[0068] In Table II, each store instruction is associated with a memory region of size 40 HEX (or 64 bytes). In Table II, each store instruction specifies an address based on the contents of register R1. In one embodiment, register R1 contains a virtual address, which is translated into a physical address in main memory 108. Therefore, 64 store instructions will be written to a contiguous memory region totaling four thousand bytes. Note that the region size written to by each instruction, the total region size written to by all instructions, and the number of instructions are for illustrative purposes only. However, the store instructions forming a bulk store operation should be written to a contiguous region of memory.

[0069] In Table II, each store instruction specifies data based on the contents of register R8. This is for illustrative purposes. In one embodiment, the data for all store instructions should be the same. In another embodiment, the data is not explicitly provided but implicit. For example, in one embodiment, a second register (R8 in Table II) is not required, and the data is implicit. Implicit data may result in memory being zeroed out.

[0070] Step 604 includes calculating the physical address to be initialized in memory. Step 604 may include a virtual address to physical address translation. In one embodiment, the address contained in a register referenced in the instruction forming the bulk store operation is a virtual address. For example, the address in register R1 in the instruction in Table I could be a virtual address. Similarly, the address in register R1 in the instruction in Table II could also be a virtual address.

[0071] Step 606 includes allocating an entry for the bulk storage operation in the bulk storage combination buffer 406.

[0072] Step 608 includes access unit 112 sending a bulk store operation to the last-level cache 104. The bulk store operation includes a physical address to be initialized in main memory 108. The bulk store operation also includes operands or other identifiers indicating that it is a bulk store operation. In one embodiment, access unit 112 bypasses all other caches in the cache hierarchy (e.g., internal cache 114) and sends the bulk store operation directly to the last-level cache 104. This allows other caches to be offloaded from processing bulk store operations.

[0073] Step 610 includes access unit 112 waiting for the bulk storage operation to complete. By waiting for the bulk storage operation, access unit 112 means that it does not take any action to initialize main memory 108, as it is left in the last-level cache 104.

[0074] Step 612 is executed while waiting for the bulk store operation to complete. Step 612 includes preventing newer loads from the region of main memory 108 that is being initialized by the bulk store operation. A newer load is defined as a load that occurs strictly in the order of instructions after the bulk store operation. Note that sometimes instructions loaded from or stored in memory may be executed out of order. In the case of Table I, instruction I4 is a newer load relative to instruction I3. Therefore, if the bulk store operation originates from instruction I3, the load associated with instruction I4 (assuming that the load comes from the region of main memory 108 that is being initialized by the bulk store operation) will be prevented until the bulk store operation completes. However, instruction I4 is not a newer load relative to instructions I6, I7, or I8. Therefore, if the bulk store operation originates from any of instructions I6, I7, or I8, the load associated with instruction I4 will not be prevented. The following is in conjunction with... Figure 12 Further details of one embodiment of preventing newer loads are described below.

[0075] After the bulk storage operation is completed, step 614 is executed. In one embodiment, when the bulk storage operation is complete, the last-level cache 104 notifies the access unit 112. Step 614 includes releasing / updating the entries for the bulk storage operation in the bulk storage combination buffer 406. Releasing an entry means removing or otherwise marking the entry so that it is no longer in use. In one embodiment, the entry is marked as invalid to release it. In one embodiment, the entry is physically deleted to release it. Updating an entry means that the entry is changed in some way, and the information in the entry can still be used. In one embodiment, the pending status changes from pending to non-pending, and the LSU validity flag 422 remains valid when the entry is updated. The non-pending status can also be referred to as completed. The following is in conjunction with Figure 11 Further details of one embodiment of releasing / updating entries used for bulk storage operations are described below.

[0076] Figure 7 A flowchart illustrating one embodiment of the action process 700 at access unit 112 when a bulk storage operation is initiated is provided. Process 700 can be executed after the bulk storage operation has been added to storage queue 402. Process 700 describes... Figure 6 Further details of one embodiment of step 606.

[0077] Step 702 includes accessing a bulk storage operation from storage queue 402 by access unit 112. For illustration, the bulk storage operation at entry 402-6 will be discussed in process 700.

[0078] Step 704 includes creating an entry for the bulk store operation to the bulk store merge buffer 406. Step 704 also includes adding the physical address for the bulk store operation to the entry. Step 706 includes setting the pending flag 426 in the entry to "1". Step 708 includes setting the LSU valid flag 422 in the entry to "1". (Reference) Figure 4 Add an entry with physical address 0x9000. The pending flag 426 of this entry is set to "1". The LSU valid flag 422 of this entry is set to "1".

[0079] Figure 8 An embodiment of a process 800 for tracking the state of a bulk store operation at the final cache level 104 is described. Process 800 provides... Figure 5 Further details of one embodiment of step 506. In one embodiment, process 800 is performed by a bulk storage state tracker 204.

[0080] Step 802 includes the last-level cache 104 receiving a bulk store operation from the access unit 112. In one embodiment, step 802 serves as... Figure 6This occurs as a result of step 608 in the main memory. A bulk store operation contains operands (or other types of identifiers) indicating that it is a bulk store operation. In one embodiment, the last-level cache 104 identifies this as a bulk store operation based on the operands. In one embodiment, the bulk store operation also contains the physical address to be initialized in main memory 108.

[0081] Step 804 includes the bulk store engine 118 in the last-level cache 104 creating an entry for the bulk store operation in the bulk store operation buffer 206. Step 804 also includes adding the physical address of the bulk store operation to the buffer entry.

[0082] Step 806 includes setting the complete flag 308 in the entry to "1". Step 808 includes setting the LLC valid flag 302 in the entry to "1". (See reference) Figure 4 As an example, an entry with physical address 0x9000 was added. The entry's pending flag was set to "1". The entry's LLC valid flag 302 was set to "1". The progress field was initially set to 0 to indicate that the process of sending a write transaction to main memory 108 had not yet begun.

[0083] Step 810 includes tracking the status of the bulk storage operation. Step 810 includes modifying the progress field as more portions of the memory are initialized for the bulk storage operation. Further details on updating the progress field will be provided in conjunction with... Figure 9 The following steps are described. Step 810 may include modifying the complete flag 308 of the entry. Step 810 may include modifying the LLC validity flag 302 of the entry.

[0084] Step 812 includes the last-level cache 104 reporting the completion of the bulk storage operation to the access unit 112. Step 812 also includes the last-level cache 104 reporting the status of the bulk storage operation to the access unit 112. In one embodiment, the status includes a complete status.

[0085] Figure 9 A flowchart depicts an embodiment of a process 900 for initializing memory at the final cache level 104 in response to a bulk store operation. Process 900 provides... Figure 5 Further details of one embodiment of step 504.

[0086] Step 902 includes setting the initial physical address to the address in the bulk storage operation. In one embodiment, this is a physical address in main memory 108.

[0087] Step 904 includes forming a write transaction to write to the current physical address. In one embodiment, the write transaction is a write transaction that writes a cache line. In one embodiment, the write transaction is a WriteUnique transaction. In one embodiment, the WriteUnique transaction conforms to the AMBA® 5 CHI architecture specification published by ARM Ltd. As is known to those skilled in the art, there are various types of WriteUnique transactions (e.g., WriteUniquePtl, WriteUniqueFull, WriteUniquePtlStash, WriteUniqueFullStash).

[0088] Step 906 includes sending a write transaction to main memory 108. Step 906 may also include receiving a response from main memory reporting the status of the write transaction. For the purposes of discussion, it is assumed that all write transactions in process 900 complete successfully. However, if one or more write transactions encounter errors, process 900 may terminate with an error status.

[0089] In one embodiment, step 906 includes sending the WriteUnique transaction formed in step 904 to cache pipeline 120. The WriteUnique transaction can be used to remove all copies of cache lines before issuing a write transaction to main memory 108. The WriteUnique transaction can trigger a back snoop on processor core 102. The WriteUnique transaction may also trigger snoops on other processor cores. After the snoop is complete, data is written to main memory 108.

[0090] Step 908 includes updating the progress of the bulk storage operation in buffer 206 of the bulk storage engine 118. In one embodiment, the progress field is used as a counter for the number of write transactions that have successfully completed. Therefore, the progress field can be incremented by one each time a write transaction successfully completes.

[0091] Step 910 determines whether the bulk storage operation has completed. In other words, the bulk storage engine 118 determines whether all write transactions have completed successfully. If not, control proceeds to step 912, where the physical address is incremented. In one embodiment, the increment size is equal to the size of each write transaction. In another embodiment, the increment size is equal to the size of a cache line.

[0092] After step 912, control proceeds to step 904. In step 904, another write transaction is formed using the current value of the physical address. When all write transactions have successfully completed (yes in step 910), control proceeds to step 914. Step 914 includes the last-level cache 104 sending a completion status of the bulk store operation to the access unit 112. In one embodiment, the completion status includes an indication of whether the bulk store operation was successful during memory initialization. In another embodiment, the completion status includes the complete status of the bulk store operation entry in buffer 206.

[0093] Figure 10 A flowchart depicts one embodiment of a process 1000 for maintaining cache coherence at the last-level cache 104 during batch storage operations. In one embodiment, process 1000 is performed for each write transaction in step 906 of process 900. Therefore, process 1000 provides further details for one embodiment of step 906. In one embodiment, process 1000 is performed by cache pipeline 120 in the last-level cache 104. Process 1000 can be performed for each write transaction sent to cache pipeline 120 (e.g., each WriteUnique transaction).

[0094] Step 1002 includes the bulk storage engine 118 sending a write transaction to the cache pipeline 120. As described above, this can be a WriteUnique transaction. In one embodiment, the write transaction is a write to a memory region having a cache line size.

[0095] Step 1004 includes checking the tag and snoop filter of the last-level cache 104. The tag can be used to determine whether the last-level cache 104 has a cache line associated with an address in main memory to be initialized by a write transaction. The snoop filter can be checked to determine whether another cache has a cache line associated with an address in main memory to be initialized by a write transaction. Therefore, the snoop filter maintains the consistent state of tracking cache lines.

[0096] Step 1006 includes snooping at the final cache 104. Step 1006 may trigger a reverse snooping at the processor core 102 that initiated the bulk store operation. Step 1006 may trigger snooping at other processor cores sharing the main memory 108.

[0097] Step 1008 includes updating the tags and snooping filters in the last-level cache 104. Therefore, the last-level cache is able to maintain cache consistency when processing bulk storage operations.

[0098] Step 1010 includes updating the state of the bulk store operation if necessary. Note that during process 1000, other processor cores may attempt to read from or write to the portion of main memory 108 that is being initialized by the bulk store operation. In one embodiment, if any read request touches the area of ​​main memory 108 that is being initialized, the integrity flag 308 in the bulk store operation buffer 206 is set to 0. In one embodiment, if any snooping request touches the area of ​​main memory 108 that is being initialized, the integrity flag 308 is set to 0.

[0099] Step 1012 includes sending a write transaction from the last-level cache to the main memory 108.

[0100] Figure 11 A flowchart depicts an embodiment of the action process 1100 performed at access unit 112 when a bulk storage operation is completed.

[0101] Step 1102 includes the access unit 112 receiving an indication from the last-level cache 104 that a bulk storage operation has been completed.

[0102] Step 1104 includes access unit 112 checking whether the integrity flag 308 in the response is set to 1 or 0. The last-level cache 104 sets the integrity flag 308 to 1 to indicate that the region of memory being initialized is still complete. The last-level cache sets the integrity flag 308 to 0 to indicate that the region of memory being initialized is no longer complete.

[0103] In response to the integrity flag 308 being 1, steps 1106 and 1108 are executed. In step 1106, the pending flag 426 in the entry for the bulk store operation in the bulk store combination buffer 406 is set to 0, indicating that the bulk store operation is no longer pending (or otherwise referred to as completed). Step 1108 includes keeping the LSU valid flag 422 in the entry in the bulk store combination buffer 406 1. The LSU valid flag 422 being 1 and the pending flag 426 being 0 can be interpreted as the initialized regions in memory remaining intact after the bulk store operation is completed.

[0104] In response to the integrity flag 308 being 0, step 1110 is executed. In step 1110, the entry in the bulk store combination buffer 406 for the bulk store operation is invalidated. In one embodiment, this includes setting the LSU validity flag 422 in the entry in the bulk store combination buffer 406 to 0, which indicates that the entry is no longer valid. Other techniques can be used to invalidate the entry.

[0105] After performing steps 1106 and 1108, or alternatively after performing step 1110, control is transferred to step 1112. Step 1112 includes access unit 112 sending a completion acknowledgment (ACK) to bulk storage engine 118.

[0106] Figure 12 A flowchart depicts one embodiment of the loading process 1200 in which the access unit 112 processes the loading process 1200 while or after a bulk storage operation is pending.

[0107] Step 1202 includes accessing a load operation through access unit 112. The load operation can be accessed from the load queue in access unit 112. The load operation can be associated with a load instruction, such as instruction I4 in Table I.

[0108] Step 1204 includes checking the bulk store combination buffer 406 for the bulk store operation against the physical address in the overwrite load command. The following examples will be used for illustration. The first example load instruction loads data at address 0x6040 in main memory 108 into register R3. The second example load instruction loads data at address 0x8040 in main memory 108 into register R3. The third example load instruction loads data at address 0x9040 in main memory 108 into register R3.

[0109] refer to Figure 4 The value depicted in the bulk store combination buffer 406 does not have a bulk store operation that overwrites 0x6040 in main memory 108. Therefore, step 1206 is NOT for the first load instruction. Therefore, control proceeds to step 1208 to load data for the first example instruction. Thus, the data at 0x6040 in main memory 108 can be loaded into, for example, register R3.

[0110] For the second example load instruction, there exists a bulk store operation that overwrites 0x8040 in main memory 108. Specifically, a bulk store operation with physical address 0x8000 in main memory 108 overwrites 0x8040 in main memory 108 (due to the 1000 HEX length of the bulk store operation). For the third example load instruction, there exists a bulk store operation that overwrites 0x9040 in main memory 108. Specifically, a bulk store operation with physical address 0x9000 in main memory 108 overwrites 0x9040 in main memory 108 (due to the 1000 HEX length of the bulk store operation). Therefore, for example instructions two and three, control will transfer to step 1210.

[0111] Step 1210 includes determining whether a pending flag 426 for a bulk storage operation is set. If so, control proceeds to step 1212. Figure 4In step 1212, a pending flag 426 is set for a bulk store operation with physical address 0x9000 in main memory 108. Therefore, in step 1212, loading from 0x9040 in main memory 108 is prevented. In other words, access unit 112 does not allow the third example load instruction to load data at address 0x9040 in main memory 108 into register R3. This blocking is enforced until the bulk store operation with physical address 0x9000 in main memory 108 completes.

[0112] exist Figure 4 In this example, the pending flag 426 is not set for the bulk store operation with physical address 0x8000 in main memory 108. The unset pending flag 426 indicates that the bulk store operation has been completed. Therefore, loading from 0x8040 in main memory 108 is not prevented. Therefore, for the second example load instruction, control proceeds to step 1214. Step 1214 includes determining whether the LSU valid flag 422 has been sent for the relevant entry in the bulk store combination buffer 406. If the LSU valid flag 422 is not set (No in step 1214), then in step 1216, data is loaded from the relevant address in main memory 108. If the LSU valid flag 422 is set (Yes in step 1214), then there is no need to load data from the relevant address in main memory 108. Instead, since the initialization value is known, a known initialization value can be provided in step 1218. For example, if it is known that the memory is initialized to all zeros, all zeros are provided in response to the load operation without requiring access to main memory 108. Therefore, time can be saved by avoiding memory access. Furthermore, it is not necessary to store the initialization value in, for example, 64 cache lines. In one embodiment, an entry in the bulk store combination buffer 406 contains information in response to a load request in step 1218. In step 1218, the information in the entry in the bulk store combination buffer 406 can be used in response to a load instruction that requests data for any portion of a large (e.g., page-size) region in memory initialized by a completed bulk store operation. Therefore, cache space can be saved by not storing the initialization value in, for example, 64 cache lines.

[0113] In one embodiment, the access unit device for tracking the state of page storage operations includes a bulk storage manager. In one embodiment, the access unit device for tracking the state of page storage operations is configured to execute process 700. In one embodiment, the access unit device for tracking the state of page storage operations is configured to execute process 1100.

[0114] In one embodiment, the means for sending multiple write transactions to main memory for each page storage operation to initialize a page in main memory includes one or more of a bulk storage engine and a cache pipeline. In one embodiment, the means for sending multiple write transactions to main memory for each page storage operation to initialize a page in main memory is configured to perform process 900.

[0115] In one embodiment, the means for tracking the status of page storage operations and reporting the status to the access unit includes one or more of a bulk storage engine and a cache pipeline. In one embodiment, the means for tracking the status of page storage operations and reporting the status to the access unit is configured to execute process 1000.

[0116] In one embodiment, means for maintaining cache coherence in the cache hierarchy when initializing pages of main memory for each page store operation includes one or more of a bulk storage engine and a cache pipeline. In one embodiment, means for maintaining cache coherence in the cache hierarchy when initializing pages of main memory for each page store operation is configured to perform process 1000.

[0117] In one embodiment, the means for tracking pending page storage operations (each page storage operation being associated with a memory region to be initialized) includes a bulk storage manager. In one embodiment, the means for tracking pending page storage operations is configured to perform process 700, where each page storage operation is associated with a memory region to be initialized. In one embodiment, the means for tracking pending page storage operations (each page storage operation being associated with a memory region to be initialized) is configured to perform process 1100.

[0118] In one embodiment, means for preventing a newer load associated with any region of memory associated with any pending page storage operation includes a bulk storage manager. In one embodiment, means for preventing a newer load associated with any region of memory associated with any pending page storage operation is configured to perform process 1200.

[0119] The techniques described herein can be implemented using hardware, software, or a combination of hardware and software. The software used is stored on one or more of the aforementioned processor-readable storage devices to program the one or more processors to perform the functions described herein. Processor-readable storage devices can include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable media can include computer-readable storage media and communication media. Computer-readable storage media can be implemented using any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disk (DVD) or other optical disc storage, cassette tape, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by a computer. One or more computer-readable media do not include propagating, modulated, or transient signals.

[0120] Communication media typically take the form of computer-readable instructions, data structures, program modules, or other data in a propagated, modulated, or transient data signal, such as a carrier wave or other transmission mechanism, and include any information transmission medium. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in a manner that encodes information in the signal. By way of example and not limitation, communication media include wired media such as wired networks or direct wired connections, and wireless media such as RF and other wireless media. Any combination of the foregoing is also included within the scope of computer-readable media.

[0121] In alternative embodiments, some or all of the software may be replaced by dedicated hardware logic components. Examples, but not limited to, exemplary hardware logic component types that may be used include Field-programmable Gate Arrays (FPGAs), Application-specific Integrated Circuits (ASICs), Application-specific Standard Products (ASSPs), System-on-a-chip Systems (SoCs), Complex Programmable Logic Devices (CPLDs), dedicated computers, etc. In one embodiment, software implementing one or more embodiments (stored on a storage device) is used to program one or more processors. The one or more processors may communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0122] It should be understood that this subject matter can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the subject matter comprehensive and complete, and to fully communicate this disclosure to those skilled in the art. In fact, this subject matter is intended to cover alternatives, modifications, and equivalents to these embodiments, all of which are included within the scope and spirit of this subject matter as defined by the appended claims. Furthermore, numerous specific details have been set forth in the foregoing detailed description of this subject matter in order to provide a thorough understanding of it. However, it will be apparent to those skilled in the art that this subject matter can be practiced without these specific details.

[0123] This document describes aspects of the present disclosure with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which are executable by the processor of the computer or other programmable instruction execution apparatus, create a mechanism for implementing the functions / actions specified in one or more flowchart illustration and / or block diagram blocks.

[0124] The description in this disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to its disclosed forms. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of this disclosure. Various aspects of this disclosure have been selected and described herein in order to best explain the principles and practical applications of this disclosure and to enable others skilled in the art to understand that this disclosure has various modifications suitable for the particular intended use.

[0125] For the purposes of this document, each process associated with the disclosed technology may be executed sequentially by one or more computing devices. Each step in the process may be executed by the same or different computing devices used in other steps, and each step need not be executed by a single computing device.

[0126] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing the claims.

Claims

1. A computer system for initializing memory, comprising: The processor core includes the central processing unit (CPU), memory access unit, and internal cache. as well as A final-level cache communicating with the processor core, the final-level cache including a cache pipeline, the final-level cache being configured as follows: Receive batch storage operations from the access unit, each batch storage operation including a physical address in the memory to be initialized; For each batch storage operation, multiple first write transactions are sent to the cache pipeline; For each batch storage operation, a plurality of corresponding second write transactions are sent from the cache pipeline to the memory to perform batch initialization of the memory for each batch storage operation; as well as The status of the bulk storage operation is tracked, wherein the cache pipeline in the last-level cache is configured to maintain cache consistency in the cache hierarchy of the computer system in response to receiving each first write transaction and before sending a corresponding second write transaction to the memory.

2. The computer system according to claim 1, wherein: The access unit includes a bulk storage combination buffer; and The access unit is configured to store the state of the bulk storage operation in the bulk storage combination buffer.

3. The computer system according to claim 1 or 2, wherein the access unit is further configured to: Bypassing the internal cache, the batch storage operation is sent directly to the last-level cache.

4. The computer system according to claim 1 or 2, wherein the access unit is further configured to: Track pending batch storage operations, where each batch storage operation is associated with a region of the memory to be initialized; and Prevent newer loads associated with any area of ​​the memory that is associated with any pending bulk storage operation.

5. The computer system according to claim 1, wherein: The access unit includes a bulk storage combination buffer; and The access unit is configured to, in response to the last-level cache indicating that a batch storage operation is complete, either set the pending status of the batch storage operation to complete or remove the batch storage operation from the batch storage combination buffer.

6. The computer system according to claim 1, wherein: The final-level cache is also configured to store information about the complete state associated with each batch store operation, the complete state indicating whether the memory regions initialized by the batch store operation have complete initialization values; and The final-level cache is also configured to set the complete state to incomplete in response to another processor core writing to a region of the memory associated with a bulk storage operation.

7. The computer system according to claim 6, wherein: The access unit includes a bulk storage combination buffer; and The access unit is also configured to: In response to the complete state indicating that the state is incomplete, invalidate the entry for the first batch store operation in the batch store combination buffer; and In response to the complete state indicating that the state is complete, the corresponding entry for the second batch storage operation is kept as a valid entry in the batch storage combination buffer.

8. The computer system according to claim 1 or 2, wherein the access unit is further configured to: If the memory region initialized by the completed bulk storage operation is still intact, a newer load instruction to load from the region is responded to by providing a known initialization value.

9. The computer system of claim 1 or 2, wherein each bulk storage operation initializes a region of the memory to all zeros.

10. The computer system of claim 1 or 2, wherein each second write transaction initializes a region of the memory having a cache line size.

11. The computer system of claim 1 or 2, wherein each bulk storage operation initializes a region of the memory having a page size.

12. The computer system according to claim 1 or 2, further comprising logic configured to: A single batch storage operation is created from multiple storage instructions, each of which is configured to initialize a region of cache line size of the memory.

13. A method for initializing memory in a computer system, comprising: At the last-level cache in the cache hierarchy of the computer system, a bulk storage operation is received from the access unit in the processor core of the computer system. Perform batch initialization of the memory for each batch storage operation, including: For each batch storage operation, multiple first write transactions are sent to the cache pipeline in the last-level cache. For each batch storage operation, a corresponding number of second write transactions are sent from the cache pipeline to the memory; and Track the status of the batch storage operation; Maintaining cache consistency in the cache hierarchy of the computer system when performing a batch initialization of the memory for each batch storage operation includes: the cache pipeline maintaining cache consistency in response to receiving each first write transaction and before sending a corresponding second write transaction to the memory.

14. The method of claim 13, wherein sending a corresponding plurality of second write transactions from the cache pipeline to the memory for each batch storage operation comprises: Send a second write transaction, each of which initializes a region of cache line size in the memory.

15. The method of any one of claims 13 or 14, wherein sending a plurality of first write transactions from the last-level cache to the memory for each batch storage operation comprises: Send multiple WriteUnique transactions to the cache pipeline in the last-level cache.

16. The method of claim 13 or 14, wherein performing the batch initialization of the memory for each batch storage operation comprises: The memory region with a page size is initialized.

17. The method according to claim 13 or 14, further comprising: Replace multiple store instructions with a single batch store operation, where each store instruction initializes a region of cache line size in the memory.

18. The method according to claim 13 or 14, further comprising: Track pending batch storage operations, where each batch storage operation is associated with a region of the memory to be initialized; as well as Prevent newer loads associated with any area of ​​the memory that is associated with any pending bulk storage operation.

19. The method according to claim 13 or 14, further comprising: In response to the completion of the first batch storage operation and the integrity of the memory region initialized by the first batch storage operation, the pending state of the first batch storage operation is set to complete; as well as In response to the completion of the second batch storage operation and the memory region initialized by the second batch storage operation being no longer complete, the tracking information for the second batch storage operation is removed.

20. The method according to claim 13 or 14, further comprising: In response to another processor core writing to the region of memory associated with the bulk storage operation, the complete state of the bulk storage operation is set to incomplete.

21. The method according to claim 13 or 14, further comprising: If the memory region initialized by the completed bulk storage operation is still intact, a newer load instruction to load from the region is responded to by providing a known initialization value.

22. The method of claim 21, wherein each batch storage operation initializes a region of the memory to all zeros.

23. A computer system for initializing memory, comprising: Main memory; Central processing unit; Access unit, the access unit including access unit means for tracking the state of page storage operations, each page storage operation including a physical address in the main memory; and The cache hierarchy includes the last-level cache. The last-level cache also includes a first means for maintaining cache consistency in the cache hierarchy when initializing the pages of the main memory for each page storage operation. The final-level cache includes a second means for sending a plurality of first write transactions to the main memory for each page storage operation to initialize a page of the main memory; The first device is further configured to send a plurality of corresponding second write transactions to the main memory to initialize the page of the main memory; as well as The last-level cache includes a third means for tracking the state of the page storage operation and reporting the state to the access unit, wherein the first means is further configured to maintain cache consistency in the cache hierarchy in response to receiving each first write transaction and before sending a corresponding second write transaction to the main memory.

24. The computer system of claim 23, wherein each page storage operation initializes a page of the main memory to all zeros.

25. The computer system of claim 23 or 24, wherein each second write transaction initializes a region of cache line size of the main memory.

26. The computer system of claim 23 or 24, wherein the access unit further comprises: A means for tracking pending page storage operations, wherein each page storage operation is associated with a region of the memory to be initialized; as well as A means for preventing newer loads associated with any region of the memory that is associated with any pending page storage operation.

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