Electronic devices, methods, and computer programs

Abstract

An electronic device is disclosed that includes a clock-gated latch between two routing lines that transmit a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of electronic devices, in particular, imaging devices and methods for imaging devices. BACKGROUND

[0002] A time-of-flight camera is a range imaging camera system that determines the distance of an object by measuring the time-of-flight (ToF) of a light signal between the camera and the object for each point of the image. A time-of-flight camera thus receives a depth map of a scene. Typically, a time-of-flight camera has an illumination unit to modulate light to illuminate a target area and a pixel array to collect light reflected from the same target area. When a single pixel collects light from certain parts of the scene, the time-of-flight camera can include a lens for imaging while maintaining a reasonable light collection area.

[0003] A typical ToF camera pixel produces a charge representative of the correlation between the illumination light and the backscattered light. To achieve the correlation between the illumination light and the backscattered light, each pixel is controlled by a common modulation input from one or more hybrid drivers. The modulation input to the pixel is synchronized with the illumination block modulation.

[0004] The number of pixels of a ToF camera or an indirect time-of-flight (iToF) camera can be very large. For example, a camera with 1 megapixel has 1 million pixels. Typically, these pixels are arranged in rows and columns of pixels. When transmitting signals, the large number of pixel column rows and columns can cause synchronization problems.

[0005] It is therefore generally desirable to improve the performance of ToF and iToF sensors in terms of the synchronization of signal transmission. SUMMARY

[0006] According to a first aspect, the disclosure provides an electronic device comprising a clock-gated latch located between two routing lines that transmit a demodulation signal from a demodulation driver to a pixel in a pixel column of a pixel array.

[0007] According to another aspect, the disclosure provides a method comprising controlling a clock-gated latch located between two routing lines that transmit a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

[0008] According to another aspect, the disclosure provides a computer program comprising instructions which, when executed on a processor, control a clock-gated latch located between two routing lines that transmit a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

[0009] Other aspects are set out in the dependent claims, the following description and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments are explained by way of example with reference to the accompanying drawings, in which:

[0011] Figure 1 The basic working principle of an indirect time-of-flight (iToF) camera is schematically illustrated;

[0012] Figure 2 An example of an iToF sensor 6 is schematically illustrated, as this iToF sensor 6 can be used in an iToF camera of the type Figure 1

[0013] Figure 3 A circuit diagram of one pixel column of an iToF sensor of the type Figure 2

[0014] Figure 4 A circuit diagram of one pixel column of an iToF sensor of the type Figure 2 Figure 3

[0015] Figure 5 A circuit diagram of one pixel column of an iToF sensor of the type Figure 2 Figure 3

[0016] Figure 6 A circuit diagram of one pixel column of an iToF sensor of the type Figure 2 Figure 3

[0017] Figure 7 An example of an iToF sensor 6 is schematically illustrated, as this iToF sensor 6 can be used in an iToF camera of the type Figure 1 Figure 2

[0018] Figure 8 A timing diagram of the signals transmitted within an iToF sensor of the type Figure 2

[0019] Figure 9 A circuit diagram of a circuit configuration of a pixel structure of a pixel is shown;

[0020] Figure 10 ​​​​​​​​​​​a timing diagram of signals transmitted within an iToF sensor from Figure 2 a clock signal for a clock-gated latch is generated by reusing a gate signal of an overflow transistor (OFG) of the iToF sensor;

[0021] Figure 11 a column of an iToF sensor from Figure 2 is shown, having clock-gated latches on the top side of the pixel array and clock-gated latches on the bottom side of the pixel array, wherein a latch signal is generated by reusing the OFG signal;

[0022] Figure 12 an arrangement of contact pads and connections for clock-gated latches in a binary tree structure is shown; and

[0023] Figure 13 an arrangement of contact pads and connections for clock-gated latches in a binary tree structure is shown. DETAILED DESCRIPTION

[0024] Before embodiments are described in detail, a general explanation is provided.

[0025] As mentioned in the outset, time-of-flight (ToF) cameras are known to comprise a variety of methods that can measure the time it takes for light to travel a distance in a medium, and thus can determine the distance. In indirect time-of-flight (iToF) cameras, the phase shift between the illuminating light and the backscattered light is calculated using signals obtained based on the backscattered light by sampling the correlation wave (e.g. between the modulated signals used to drive the light source, the pixel array, etc.) to obtain a depth measurement.

[0026] Embodiments described in more detail below disclose an electronic device comprising a clock-gated latch between two routing lines, the clock-gated latch transmitting a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

[0027] The electronic device can be, for example, an image sensor, for example an image sensor of an indirect time-of-flight camera (ToF). The indirect time-of-flight camera can resolve distances by measuring the phase shift of the emitted light and the backscattered light. The electronic device can also be a device comprising a ToF or iToF sensor, for example a time-of-flight camera or a smartphone. The time-of-flight camera can be a range imaging camera system that determines the distance of an object whose flight time (ToF) of a measured light signal is between the object and the camera for each point of an image.

[0028] A pixel array can comprise columns and rows of pixels. Pixels of a ToF camera typically comprise one or more photosensitive elements (e.g. photodiodes). The photosensitive elements convert incident light into electrical current. A switch (e.g. a transfer gate) connected to the photodiode can direct the electrical current to one or more storage elements (e.g. a floating diffusion) that act as accumulation elements that accumulate and / or store electrical charge. The pixels can be locked-in pixels for time-of-flight cameras, e.g. FDGS-type pixels or photon-mixer devices (PMDs). All pixels in a ToF / iToF sensor can be controlled by modulation / demodulation signals based on a multi-level synchronous clock signal. A multi-level hybrid clock scheme can be used to generate one or more (effective) modulation / demodulation signals that drive the pixels. These modulation / demodulation signals can be a step function comprising multiple voltage levels.

[0029] For each pixel column, a demodulation driver can be used. The demodulation driver can generate a demodulation signal based on a multi-level synchronous clock signal.

[0030] Each demodulation driver can be connected to the pixels in the corresponding column by two routing lines. The demodulation can be transmitted via the two routing lines. The demodulation signals transmitted by the two routing lines can have a phase shift. The phase shift can be 90 degrees or 180 degrees or 270 degrees. A clock-gated latch can be installed between the two routing lines such that the two routing lines are connected to the clock-gated latch in a symmetrical manner.

[0031] According to embodiments, the clock-gated latch improves the fall time of the demodulation signals transmitted by the routing lines. The fall time can be the time it takes for the amplitude of a signal to drop from a first specified value to a second specified value. For example, the first specified value can be 70%, 80% or 90% of the peak value of the signal. For example, the second specified value can be 30%, 20% or 10% of the peak value of the signal.

[0032] According to embodiments, the clock-gated latch is installed on the top side of the pixel column.

[0033] According to embodiments, the clock-gated latch is directly installed above the first pixel of the pixel column.

[0034] According to embodiments, the clock-gated latch is installed on the bottom side of the pixel column.

[0035] According to embodiments, the clock-gated latch is directly installed below the last pixel of the pixel column.

[0036] According to embodiments, a first clock-gated latch is installed on the top side of the pixel column and a second clock-gated latch is installed on the bottom side of the pixel column.

[0037] According to embodiments, the first clock-gated latch is directly installed above the first pixel of the pixel column and the second clock-gated latch is directly installed below the last pixel of the pixel column.

[0038] According to an embodiment, the clock-gated latch comprises two inverter gates.

[0039] According to an embodiment, the clock-gated latch comprises a latch enabling input. The latch enabling input can be any interface that allows an electrical signal to be input to the latch by changing the state of the latch to enabled or disabled. The input signal can be a current signal or a voltage signal.

[0040] According to an embodiment, the clock signal enables / disables the clock-gated latch. The clock signal can be a current signal or a voltage signal. The signal can change the state of the clock-gated latch to enabled or disabled. The clock signal can be a signal that oscillates between a high and a low state.

[0041] The clock signal can be a rectangular signal. The generation of the rectangular signal can be done by a quartz oscillator or an oscillating crystal. There can be a need for several different clock signals. In this case, there can be one master oscillator responsible for providing these different clock signals, which can be generated with the help of a phase-locked loop (PLL) or a frequency divider.

[0042] According to an embodiment, the clock signal is generated by a latch clock. The latch clock can be the same as the clock of the electronics that can generate the clock signal of the latch as described above, or the latch clock signal can be generated based on the clock signal of the electronics by a phase-locked loop (PLL) or a frequency divider as described above. Or the latch clock can be a separate clock device. In this case, the latch clock can be generated by a quartz oscillator comprising a control circuit or by an oscillating crystal. The latch clock can also be implemented as a software program.

[0043] According to an embodiment, the clock signal is generated based on the overflow transistor gate signal. The OFG signal can be generated by the same synchronous clock that generates other signals (e.g. demodulation signals) within the iToF sensor, so the delay gradient is the same. In another embodiment, the OFG signal can be generated by a separate clock, such as a vertical scanner in an image sensor.

[0044] According to an embodiment, the clock signal is generated by inverting the overflow transistor gate signal. The inversion can be done with the help of an inverter gate.

[0045] According to an embodiment, the contact pads for the power supply of the clock-gated latch are installed in the middle part of the pixel array.

[0046] According to an embodiment, a first contact pad for a power supply of the clock-gated latch is mounted at a left side of the pixel array and a second contact pad for a power supply of the clock-gated latch is mounted at a right side of the pixel array.

[0047] According to an embodiment, the electronic device is a time-of-flight camera.

[0048] The embodiments described below disclose in further detail a method comprising controlling a clock-gated latch, the clock-gated latch being located between two routing lines, the routing lines transmitting a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

[0049] The embodiments described below in further detail disclose a computer program comprising instructions which, when executed on a processor, control a clock-gated latch, the clock-gated latch being located between two routing lines, the routing lines transmitting a demodulation signal from a demodulation driver to a pixel of a pixel column of a pixel array.

[0050] Embodiments will now be described, by way of example, with reference to the accompanying drawings.

[0051] Figure 1 The basic working principle of an indirect time-of-flight (iToF) camera is schematically shown. The iToF camera comprises an illumination unit (laser) 2, a lens 3 and an iToF sensor 6. The iToF sensor 6 comprises an array of time-resolved pixels 7. The time-resolved pixel 7 comprises two floating diffusions FA, FB, two hybrid clock guides GA, GB, an overflow transistor, a photodiode 8 and other elements. The hybrid clock guides GA, GB are controlled by a clock that is synchronized with a modulation clock in the illumination unit (laser) 2. The same synchronized clock guides the demodulation signals GDA and GDB (see Figure 3 ) and the overflow transistor gate signal (OFG signal). The synchronized clock is part of the driver array (demodulation driver) as shown in Figure 2 The photodiode 8 generates electrons based on incident photons. The generated electrons are guided to either the floating diffusion FA or the floating diffusion FB because complementary clocks are applied to the two hybrid clock guides GA and GB. In another embodiment, the synchronized clock can be implemented by a software program. In another embodiment, the demodulation signals GDA and GDB, the LSR signal (see Figure 8 and Figure 9 ) and the gate signal can be guided by different clocks. Since there can be an offset between the different clocks, an electrical delay can be added to compensate for this offset.

[0052] A dedicated illumination unit 2 is used, for example using a timing generator ( Figure 1At least one set of light pulses of a predetermined frequency (not shown) are generated to actively illuminate object 1 using modulated light 4 of a predetermined wavelength. The modulated light 4 returns from object 1. Lens 3 collects the returned light 5 and forms an image of the object on the iToF sensor 4 of the camera. Depending on the distance Z between the object and the camera, there is a delay between the emission of the modulated light 4 (e.g., the so-called light pulses) and the reception of these returned light pulses 5 at the camera.

[0053] The indirect time-of-flight (iToF) camera calculates the delay between the modulated light 4 and the returned light 5 to obtain depth measurements by sampling the correlated wave (e.g., the correlated wave between the demodulated signal generated by the timing generator and the reflected light 5 stored in the time-resolved pixel 7).

[0054] Figure 2 A schematic example of the iToF sensor 6 is shown because it can be used... Figure 1 The iToF camera. The iToF sensor 6 includes a demodulation driver array 20, which includes one demodulation driver 20A for each pixel column. Additionally, a synchronization clock ( Figure 2 (Not shown in the image) is part of the driver array. Furthermore, the iToF sensor 6 includes a pixel array 21, which may consist of a plurality of pixels 7 per row and per column. Additionally, the iToF sensor 6 includes routing lines 22 (dashed lines) connecting the demodulation driver array 20 to the pixels within the pixel array. In this embodiment, the iToF sensor 6 includes a demodulation driver 20A for each pixel column, the demodulation driver 20A generating modulation signals GDA and GDB (see image). Figure 3 The modulated signal is transmitted via two corresponding routing lines 22A and 22B. Each demodulation driver 20A drives one column of pixels on the iToF sensor. It should be noted that... Figure 2 The complete iToF sensor is not shown; instead, a simplified schematic diagram of the iToF sensor is presented to illustrate the relationship between the hybrid clock driver (top-side triangle) and the routing lines and pixel array.

[0055] Figure 3 schematically shown Figure 2 The circuit diagram shows a pixel column of an iToF sensor. Each pixel column (sometimes referred to as a column) includes a demodulation driver 20A, which includes two amplifiers 30A and 30B. Amplifiers 30A and 30B receive demodulated signals GDA and GDB, respectively, as a synchronization clock. Figure 3The amplifiers 30A and 30B are supplied with a positive supply voltage VDD. Furthermore, each column of the iToF sensor 6 comprises two routing lines 36A and 36B connecting all pixels 7 within the considered column with the demodulation driver 20A, so that the demodulation signals GDA and GDB are transferred to each pixel 7 in the considered column. Furthermore, for each pixel 7 in the considered column, there is a resistance-capacitance section 32 comprising two storage capacitors 34A and 34B along the routing line 36A, and a resistance 32A between the storage capacitors 34A and 34B. Furthermore, the resistance-capacitance section 32 comprises two storage capacitors 34C and 34D along the routing line 36B, and a resistance 32B between the storage capacitors 34b and 34D.

[0056] When the pixel array 21 becomes large, e.g. 1 megapixel, several problems can arise, because the demodulation driver 20A of the driver array 20 (or by the sync clock) can have difficulties to deliver proper waveforms GDA and GDB in terms of rise and fall times of the signals GDA and GDB and achievable voltages to demodulate the locked pixels 7 in the iToF sensor 6. The problem can be caused by a time delay (time constant) of the signals GDA and GDB at the delayed pixels 7. This time delay can occur due to different possible aspects, e.g. due to PCB routing line inductance (L) / resistance (R) / capacitance (C) or due to bond wire inductance (L) / resistance (R) / parasitic capacitance (C), or due to resistance (R) / parasitic capacitance (C) of the demodulation driver 20A, or due to routing line metal line (across the pixel array) resistance (R) / (C) and load capacitance contributed by the pixel elements.

[0057] In the following, the problem of time delay due to routing line metal line resistance (R) / capacitance (C) and load capacitance contributed by the pixel elements shall be addressed.

[0058] As mentioned above, if the pixel array is large and many pixels are placed in one column, the increased resistance and capacitance become large, so the demodulation signals have a time delay (RC filter effect) and the demodulation driver can no longer properly drive the routing lines and the pixels 7. This problem can be solved by making the demodulation driver larger in terms of power to increase the driving capability. However, this will increase the power consumption due to the parasitic capacitance of the demodulation driver itself. Furthermore, the time delay of the demodulation signals GDA and GDB is almost only determined by the pixel bottom side routing line resistance / capacitance and the pixel capacitance (see Figure 2 ), so in this case, increasing the driving capability of the driver does not help to improve the signals.

[0059] Clock gated latches

[0060] In embodiments described in more detail below, the problem of time delay due to routing line metal resistance (R) / capacitance (C) and pixel element contributed load capacitance is addressed by adding clock gated latches on the top side of the pixel array (after the drivers) or adding clock gated latches on the bottom side of the pixel array, or adding clock gated latches on both the top and bottom side of the pixel array, and on the bottom side of the pixel array, as shown in Figure 4 , Figure 5 and Figure 6 In embodiments of Figure 4 , Figure 5 and Figure 6 , the clock signal Latch Enable to enable or disable the latches is generated by a latch clock located in the driver array 20. In another implementation, the latch clock can not be located in the driver array but in other parts of the iToF sensor. In another embodiment, the clock signal Latch Enable can not be generated by a latch clock but by another clock, for example a synchronization clock also used to steer other parts of the iToF sensor, for example Figure 1 . In another embodiment the latch clock can be implemented by a software program.

[0061] Figure 4 A circuit diagram of one pixel column of the iToF sensor of Figure 2 is schematically shown, wherein clock gated latches are added on the top side of the pixel array compared to the example of Figure 3 . The clock gated latches are added on the top side of the pixel array, for example directly after the drivers and above the first pixel. Each column comprises a demodulation driver comprising two amplifiers 30A and 30B. The amplifiers 30A and 30B receive a demodulation signal GDA and GDB, respectively, as from a synchronization clock Figure 4The amplifiers 30A and 30B are equipped with a positive supply voltage VDD. Furthermore, each column of the iToF sensor 6 comprises two routing lines 36A and 36B connecting all pixels 7 within the considered column with a demodulation driver, thereby transmitting the demodulation signals GDA and GDB to each pixel 7 in the considered column. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 34A and 34B along the routing line 36A and a resistor 32A between the storage capacitances 34A and 34B. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 34C and 34D along the routing line 36B and a resistor 32B between the storage capacitances 34C and 34D. Furthermore, at the top side of the pixel array, in the considered column of pixels, a clock-gated latch 40 is placed between the routing lines 36A and 36B. The top side of the pixel array in the considered column is to be understood with respect to the considered column, which means that the top side refers to the beginning side of the considered column of pixels. For example, the latch-gated latch 40 is located directly above the first pixel element. The clock-gated latch 40 comprises two inverter gates (also referred to as NOT gates) 42A and 42B. The clock-gated latch 40 is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 40 has an enable input EN, which is connected to a clock signal Latch Enable. The clock signal Latch Enable is amplified by an amplifier 44 equipped with a positive supply voltage YDD. Furthermore, the clock-gated latch is equipped with a positive supply voltage VDD.

[0062] In another embodiment, the clock-gated latch can be placed in the upper half of the considered column of the pixel array. In yet another embodiment, the clock-gated latch can be placed outside of the considered column of the pixel array, but the clock-gated latch can be connected to the pixels in the considered column in a way that it is connected to the topmost pixel in the considered column first.

[0063] The inverter gates 42A and 42B are logic gates. An inverter gate outputs to its input a voltage representing the opposite logic level. This means that its main function is to invert the applied input signal, i.e. if the applied signal is low, the output becomes high and vice versa. A logic inverter gate can be implemented as a circuit in different ways. For example, a logic inverter gate can be built using a single NMOS transistor or a single PMOS transistor coupled with a resistor. Alternatively, an inverter can be implemented using two complementary transistors in a CMOS configuration. Another alternative is to implement a bipolar junction transistor inverter logic in a resistor-transistor logic or transistor-transistor logic configuration.

[0064] The clock signal Latch Enable (if off) implements that the clock enabled latches do not accept any input signal that could change the output or in other words the latches are switched off. Due to the complementarity of the latches the contained clock signal Latch Enable is applied. If the demodulation signals GDA and GDB are set to 1 at the same time or set to 0 at the same time for a longer time period a high current will be observed. To avoid this problem the clock signal Latch Enable is set to 0 besides the integration time period (mixing time period) and the additional pre- and post mixing time periods (see Figure 8 ) to enable the correct switching of the contained control circuit signals Latch Enable.

[0065] Figure 5 A circuit diagram of one pixel column of an iToF sensor is schematically shown Figure 2 , wherein clock gated latches are added at the bottom side of the pixel array compared to the example of Figure 3 . Each column comprises a demodulation driver comprising two amplifiers 30A and 30B. The amplifiers 30A and 30B receive the demodulation signals GDA and GDB, respectively, as input from a synchronized clock Figure 5The amplifiers 30A and 30B are provided with a positive supply voltage VDD. Furthermore, each column of the iToF sensor 6 comprises two routing lines 36A and 36B connecting all pixels 7 within the considered column with the demodulation driver, so that the demodulation signals GDA and GDB are transmitted to each pixel 7 in the considered column. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 34A and 34B along the routing line 36A and comprises a resistance 32A between the storage capacitances 34A and 34B. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 34C and 34D along the routing line 36B and comprises a resistance 32B between the storage capacitances 34C and 34D. Furthermore, on the bottom side of the pixel array, in the considered column of pixels, a clock-gated latch 50 is placed between the routing lines 36A and 36B. The bottom side of the pixel array in the considered column is to be understood with respect to the considered column, which means that the bottom side refers to the end side of the considered column of pixels. For example, the latch-gated latch 50 is located directly below the last pixel element. The clock-gated latch 50 comprises two inverter gates (also referred to as NOT gates) 52A and 52B. The clock-gated latch 50 is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 50 has an enable input EN, which is connected to a latch enable clock signal. The latch enable clock signal is amplified by an amplifier 44, which is provided with a positive supply voltage VDD. Furthermore, the clock-gated latch is provided with a positive supply voltage VDD2. A contact pad connecting the latch to the supply VDD2 is mounted on the bottom side of the pixel array. This is possible because the latch is self-triggering (in fact, another pair of clock and mix driver parts are arranged on the bottom side of the pixel array without hybrid clock delay mismatch problems).

[0066] In another embodiment, the clock-gated latch can be placed in the lower half of the considered column of the pixel array. In yet another embodiment, the clock-gated latch can be placed outside of the considered column of the pixel array, but the clock-gated latch can be connected to the pixels in the considered column in a way that it is connected to the bottom-most pixel in the considered column first.

[0067] As a clock-gated latch is added on the other side of the pixel array, the clock-gated latch can draw current from the newly added power pad instead of only from the power pad of the demodulation driver. Thus, if we consider the RC time constant, not only the routing line resistance R from the top side, there are two parallel effective routing line resistances on both sides, which have an effective resistance smaller than the resistance of the routing line from only one side. Thus, as mentioned above, the inclusion of a clock-gated latch in the column of the iToF sensor can help to break the RC time constant. Furthermore, due to the presence of a positive feedback loop in the latch circuit, the latch circuit can increase the switching speed of the complementary clock, i.e. GDA / GDB. Thus, the demodulator signal of the iToF sensor has a faster rise / fall time. In other words, in this case, due to the added power supply (voltage VDD2), which is provided by a power pad (i.e. IO pins located around the core of the chip to provide an interface to the outside of the chip by e.g. a bond wire), the clock-gated latch is placed on the bottom side of the pixel array, the RC time constant of the bottom pixels is not limited by the path from the top driver (and the large resistance and capacitance due to the long distance), but is reduced by the clock-gated latch placed on the bottom and the added bottom side power supply. Thus, the total RC time constant is reduced. Furthermore, the current flowing from the bottom power supply is much smaller than the current flowing from the top side. Thus, only a small number of power pads is needed on the bottom side (see also Figure 12 and Figure 13 ). Thus, the clock-gated latch helps to break the RC time constant of all pixels in the pixel column where the clock-gated latch is placed, especially the pixels on the bottom side of the pixel array. Thus, the demodulator signal of the iToF sensor has a faster rise / fall time.

[0068] Figure 6 a circuit diagram of one pixel column of the iToF sensor of Figure 2 is shown schematically, wherein, in contrast to the example of Figure 3 , a clock-gated latch is added on the top side of the pixel array and a clock-gated latch is added on the bottom side of the pixel array. Each column comprises a demodulation driver, which comprises two amplifiers 30A and 30B. The amplifiers 30A and 30B receive the demodulation signals GDA and GDB, respectively, as a clocked signal from a synchronization clock Figure 6The amplifiers 30A and 30B are supplied with a positive supply voltage VDD. Furthermore, each column of the iToF sensor 6 comprises two routing lines 36A and 36B connecting all pixels 7 within the considered column with a demodulation driver, so that the demodulation signals GDA and GDB are transferred to each pixel 7 in the considered column. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 34A and 34B along the routing line 36A and a resistance 32A between the storage capacitances 34A and 34B. Furthermore, each pixel 7 in the column comprises two storage capacitances 34C and 34D along the routing line 36B and a resistance 32B between the storage capacitances 34A and 34D. Furthermore, at the top side of the pixel array, in the considered column of pixels, a clock-gated latch 60A is placed between the routing lines 36A and 36B. The top side of the pixel array in the considered column is to be understood with respect to the considered column, which means that the top side refers to the beginning side of the considered column of pixels. For example, the latch-gated latch 60A is directly located above the first pixel element. The clock-gated latch 60A comprises two inverter gates (also referred to as NOT gates) 62A and 62B. The clock-gated latch 60A is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 60A has an enable input EN, which is connected to a Latch Enable clock signal. The clock signal Latch Enable is amplified by an amplifier 44, which is supplied with a positive supply voltage VDD. Furthermore, the clock-gated latch 60A is supplied with a positive supply voltage VDD. Furthermore, at the bottom side of the pixel array in the considered column of pixels, a clock-gated latch 60B is placed between the routing lines 36A and 36B. The bottom side of the pixel array in the considered column is to be understood with respect to the considered column, which means that the bottom side refers to the end side of the considered column of pixels. For example, the latch-gated latch 60B is directly located below the last pixel element. The clock-gated latch 60B comprises two inverter gates (also referred to as NOT gates) 62C and 62D. The clock-gated latch 60B is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 60B has an enable input EN, which is connected to a Latch Enable clock signal Latch Enable. The clock signal Latch Enable is amplified by an amplifier 44, which is supplied with a positive supply voltage VDD. Furthermore, the clock-gated latch is supplied with a positive supply voltage VDD2.

[0069] In another embodiment, the clock-gated latch 60A can be placed in the upper half of the considered column of the pixel array. In yet another embodiment, the clock-gated latch 60A can be placed outside of the considered column of the pixel array, but the clock-gated latch 60A can be connected to the pixels in the considered column in a way that it is connected to the topmost pixel in the considered column first.

[0070] In another embodiment, a clock-gated latch 60B can be placed in the lower half of the considered column of the pixel array. In yet another embodiment, a clock-gated latch 60B can be placed outside the considered column of the pixel array, but the clock-gated latch 60B can be connected to the pixels in the considered column in a way that it is connected first to the bottom-most pixel in the considered column.

[0071] In this case, when one clock-gated latch is placed at the bottom side of the pixel array and one clock-gated latch is placed at the top side of the pixel array, the RC time constant of all pixels is reduced. Therefore, the demodulator signal of the iToF sensor has a faster rise / fall time. Furthermore, the current flowing from the bottom power supply is much smaller than the current flowing from the top side of the pixel array. Therefore, only a small amount of power pads is needed at the bottom side of the pixel array (see also Figure 12 and Figure 13 ).

[0072] In the above embodiments, two latches are used per pixel column. In alternative embodiments, more than two latches per column can also be implemented. For example, a third latch can be installed in the middle of each row. The clock-gated latches in this setup are used in the analog domain to directly adjust the driving capability, and the clock-gated latches are not used as registers.

[0073] Figure 7 An example of an iToF sensor 6 is schematically shown, as this iToF sensor 6 can be used in an iToF camera of the type Figure 1 ; with Figure 2 An additional clock-gated latch is added at the top side of the pixel array, and an additional clock-gated latch is added at the bottom side of the pixel array. One row of latches 71 is added at the top side of the pixel array. One row of latches 72 is added at the bottom side of the pixel array. In this embodiment, for each column of the pixel array, there is one latch at the top and one latch at the bottom. In this embodiment, the row of latches 71 is installed above the first row of pixels, and the row of latches 72 is installed below the last row of pixels. In another embodiment, the row of latches 71 can be installed in the upper half of the pixel array 21, and the row of latches 72 can be installed in the lower half of the pixel array 21. Adding a row of latches at the top side of the pixel array will be understood with respect to the pixel array, which means that top means the start side of the pixel array, i.e. above the first row. Adding a row of latches at the bottom side of the pixel array will be understood with respect to the pixel array, which means that bottom means the end side of the pixel array, i.e. below the last row.

[0074] Figure 8 An example of an iToF sensor 6 is schematically shown, as this iToF sensor 6 can be used in an iToF camera of the type Figure 2of the iToF sensor. From this timing diagram, the synchronization clock and the latch clock can control the timing of the individual signals. The integration time period or mixing time period is the time period in which the photons emitted from the laser 2 of the iToF camera are received and accumulated (also integrated or mixed together) by each pixel 7 of the iToF sensor 6 to calculate a correlation signal in order to measure the distance of an object. A pre-mixing time period is defined before the integration time period and a post-mixing time period is defined after the integration time period. The signal Integration Enable is the signal defining the integration time of the iToF camera, i.e. the time period in which the arriving photons emitted by the laser 2 of the iToF camera are integrated. Therefore, Integration Enable is set to 1 during the integration time period and 0 otherwise. The LSR signal is the laser signal emitted by the laser 2 of the iToF camera, e.g. a modulated light 4 with a predetermined wavelength 1 (see Figure 1 ). The LSR signal can be a square wave signal with a predetermined wavelength 1 or another periodic or non-periodic signal with different wavelengths. Outside the integration time period, the LSR signal is set to 0. The demodulation signal GDA is generated by the synchronization clock and has the same phase and wavelength 1 as the laser signal LSR. The demodulation signal GDA does not vanish during the pre-mixing and post-mixing time period. The demodulation signal GDB generated by the mixing clock GB has a phase difference of 180° to the LSR signal and the same wavelength 1 as the laser signal LSR. The demodulation signal GDB does not vanish during the pre-mixing and post-mixing time period. The clock signal Latch Enable, which switches on / off the above mentioned clock gated latches 40, 50 and 60 (see Figure 4 、 Figure 5 and Figure 6 ) is set to 1 (on) during the integration time period and 0 otherwise for a certain time before, e.g. for a half wavelength 1 before, i.e. during the pre-mixing, and after, e.g. for a wavelength 1 after, i.e. during the post-mixing. This means that GDA and GDB start before and end after the LSR signal, respectively. When the clock signal Latch Enable is set to 0, the clock enabled latches 40, 50 and 60 do not accept any input signal that could change the output or, in other words, the latches are switched off. Due to the complementarity of the latches 40, 50 and 60, the clock signal Latch Enable is applied. This means that if both demodulation signals GDA and GDB are set to 1 or to 0 at the same time for a longer time period, a large current will be observed. To avoid this problem, the clock signal Latch Enable is set to 0 outside the integration time period and parts of the pre-mixing and post-mixing time period to switch the clock signal Latch Enable correctly.

[0075] Reuse of OFG signal

[0076] In an iToF sensor, different signals are generated and used to operate the sensor. In the present embodiment, the overflow transistor gate signal ("OFG signal") is reused in order to generate a clock signal for enabling clock-gated latches.

[0077] Figure 9 A circuit diagram showing a circuit configuration of a pixel structure of a pixel is shown. The pixel includes, for example, in addition to a photodiode 76 as a photoelectric conversion unit, a transfer transistor 71, a reset transistor 72, an amplification transistor 73, a selection transistor 74, and an overflow transistor (also referred to as a charge / discharge transistor) 75. The anode of the photodiode 76 is connected to a negative power supply (e.g., ground), photoelectrically converts received visible light into photoelectric charges in an amount proportional to the light quantity thereof, and accumulates the photoelectric charges. The photodiode 76 has a cathode electrode electrically connected to the gate of the amplification transistor 73 via the transfer transistor 71. A node 77 electrically connected to the gate electrode of the amplification transistor 73 will be referred to as an FD (floating diffusion) portion.

[0078] The overflow transistor 75 is connected between the photodiode 76 and a charge discharge node (e.g., a power supply line of a power supply voltage Vdd). When the overflow transistor gate signal OFG is supplied to its gate electrode, the overflow transistor 75 is turned on, whereby the photoelectric charges in the photodiode 76 are selectively discarded to the overflow node.

[0079] The overflow transistor 75 is turned on during a period in which photoelectric charge accumulation is not performed, which is sometimes referred to as an anti-blooming mode. Therefore, overexposure in an image due to charge overflow within a pixel element should be prevented, which means preventing excess light from being incident into the photodiode 76 and saturated by photoelectric charges, and then the charges exceeding the saturated charge amount overflow the FD portion 77 or its periphery. By reusing the overflow transistor gate signal, i.e., the OFG signal, as a clock signal for enabling clock-gated latches, instead of installing a new clock and signal line, an additional signal pin can be saved. The OFG signal can be generated by the same synchronization clock that generates a demodulation signal, so the delay gradient is the same. In another embodiment, the OFG signal can be generated by a separate clock, such as a vertical scanner in an image sensor.

[0080] Figure 10 A circuit diagram showing a circuit configuration of a pixel structure of a pixel is shown. The pixel includes, for example, in addition to a photodiode 76 as a photoelectric conversion unit, a transfer transistor 71, a reset transistor 72, an amplification transistor 73, a selection transistor 74, and an overflow transistor (also referred to as a charge / discharge transistor) 75. The anode of the photodiode 76 is connected to a negative power supply (e.g., ground), photoelectrically converts received visible light into photoelectric charges in an amount proportional to the light quantity thereof, and accumulates the photoelectric charges. The photodiode 76 has a cathode electrode electrically connected to the gate of the amplification transistor 73 via the transfer transistor 71. A node 77 electrically connected to the gate electrode of the amplification transistor 73 will be referred to as an FD (floating diffusion) portion. Figure 2a timing diagram of signals transmitted within an iToF sensor, wherein a clock signal of a clock-gated latch is generated by reusing an overflow transistor gate signal (OFG) of the iToF sensor. From the timing diagram, a timing generator can control the timing of the individual signals. The integration time period or mixing time period is the time period in which the photons emitted by the laser 2 of the iToF camera are received and accumulated (also integrated or mixed together) by the iToF sensor 6 to calculate a correlation signal in order to measure the distance of an object. The LSR signal is the laser signal emitted by the laser 2 of the iToF camera, e.g. a modulated light 4 having a predetermined wavelength (see Figure 1 ). The LSR signal can be a square wave signal having a predetermined wavelength 1 or another periodic or non-periodic signal having different wavelengths. Outside the integration time period, the LSR signal is set to 0. The demodulation signal GDA (see Figure 3 ) generated by the sync clock has the same phase and wavelength 1 as the laser signal LSR. The demodulation signal GDB generated by the mixing clock GB (see Figure 3 ) has a phase difference of 180° to the LSR signal and the same wavelength 1 as the laser signal LSR. The OFG signal is a signal controlling the gate of an overflow transistor. The clock signal Latch Enable_2 is a clock signal turning on / off the clock-gated latch 40, 50, 60 or 91 (see Figure 11 ). The clock signal Latch Enable_2 is set to 1 (on) when either the demodulation signal GDA or GDB is non-0 and to 0 when both demodulation signals GDA and GDB are 0. This means that the clock signal Latch Enable_2 is just the inverted OFG signal. Thus, the clock signal Latch Enable_2 can be generated by inverting the OFG signal and thereby reusing the OFG signal. To invert the OFG signal, e.g. an inverter gate or a non-overlapping clock generator or other circuitry can be used, which will be explained in the following Figure 9 .

[0081] Figure 11 shows Figure 2 a column of an iToF sensor having clock-gated latches at the top side of the pixel array and clock-gated latches at the bottom side of the pixel array, wherein the latch signals are generated by reusing the OFG signal. Each column comprises a demodulation driver comprising two amplifiers 30A and 30B. The amplifiers 30A and 30B receive the demodulation signals GDA and GDB, respectively, as from the sync clock Figure 11The amplifiers 30A and 30B are supplied with a positive supply voltage VDD. Furthermore, each column of the iToF sensor 6 comprises two routing lines 36A and 36B connecting all pixels 7 within the considered column with the demodulation driver, so that the demodulation signals GDA and GDB are transferred to each pixel 7 in the considered column. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 94A and 94B along the routing line 36A and a resistance 92A between the storage capacitances 94B and 94A. Furthermore, each pixel 7 in the considered column comprises two storage capacitances 94C and 94D along the routing line 36B and a resistance 92B between the storage capacitances 94B and 94D. Furthermore, directly on top of the pixel array below the amplifiers 90A / 90B, in the considered pixel column, a clock-gated latch 91A is placed between the routing lines 36A and 36B. The clock-gated latch 91A comprises two inverter gates (also called NOT gates) 92A and 92B. The clock-gated latch 91A is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 91A has an enable input. Furthermore, if the pixel column is directly below the last pixel element, in the considered pixel array, at the bottom side, a clock-gated latch 91B is placed between the routing lines 36A and 36B. The clock-gated latch 91B comprises two inverter gates (also called NOT gates) 92C and 92D. The clock-gated latch 91B is connected to the routing lines 36A and 36B. Furthermore, the clock-gated latch 91B has an enable input. Furthermore, the OFG signal is amplified by an amplifier 90C and the amplified OFG signal is inverted by an inverter gate 94A. The output of the inverter gate 94A is the clock signal Latch Enable_2, which is input to the latch enable input of the latch 91A (not shown in the middle) to enable the latch 91A. Furthermore, the amplified OFG signal is also connected to the inverter gate 94B through the resistance 92C and the two capacitances 34E and 34F. The output of the inverter gate 94B is the latch enable signal Latch Enable_2, which is input (not shown in the middle) to the latch enable input of the latch 91B to enable the latch 91B. Figure 11 Figure 11

[0082] Contact pad arrangement

[0083] A contact pad is a designated surface area on an iToF chip where components are electrically connected to a power supply, for example. Possible electrical connection pads include soldering and wire bonding.

[0084] If a clock-gated latch is included in a pixel as described above, in particular if the clock-gated latch is mounted at the bottom side of the pixel array, an additional power supply for the latch is needed, so an additional contact pad is needed. As Figure 2 ​​As shown, there can be a large number of columns in the iToF sensor 6, for example, if the iToF has 10 million pixels (1 megapixel), there can be 1000 columns and 1000 rows, and thus a large number of clock gated latches can be used in the pixel array. As a result, new pads need to be installed, and the contact pads at the iToF sensor 6 can have different arrangements. Alternatively, the contact pads are already installed, and there are different possible arrangements of which ones of the already installed contact pads to use. Because the pad size is much smaller than the size of the pixel array, a way of fanning out must be found.

[0085] Figure 12 An arrangement of contact pads and connections for clock gated latches in a binary tree structure is shown. The iToF sensor 6 includes a driver and clock section 102 that includes clocks and drivers for all pixels of the iToF sensor 6. The contact pads 104 are arranged in a middle portion of the pixel array in the bottom of the pixel array. The middle portion of the pixel array can mean that the contact pads can be located in the middle third of the pixel array along the horizontal axis, meaning for example in the middle third of the length of the pixel array along the horizontal axis. For example, if the pixel array has 1000 columns and 1000 rows, the contact pads can be arranged below row 1000 and between columns 500 and 501. The contact pads 104 are connected to a power supply. Because of this arrangement and the binary tree layout of the power supply metal routing lines, the gradient caused by a single pad is reduced. Furthermore, the contact pads connect the power supply to the latches in each row of the pixel array via a binary tree structure 106. The binary tree structure can be implemented by a conductive material, for example copper. If one contact pad in the middle of the pixel array connected to the power supply is not enough to counteract the horizontal gradient, one or more additional contact pads can be added, such that the space between the contact pads is equally large. For example, when two contact pads are installed, one contact pad can be installed after one third of the length of the pixel array in the horizontal direction, and the second contact pad can be after two thirds of the length of the pixel array in the horizontal direction. Alternatively, in another embodiment, the contact pads are already installed, and it must be decided which of the already installed contact pads should be used. In this case, the installed pads can form a line along the pixel array or along a portion of the pixel array. As described above, in this case, a contact pad that is located in the middle portion of the line of contact pads along the pixel array can be used to power the clock gated latches in a binary tree structure. For example, the middle portion of the line of contact pads along the pixel array can be located at one third of the way along the line of contact pads along the pixel array. As described above, if one contact pad in the middle of the line of contact pads along the pixel array is not strong enough to counteract the horizontal gradient, more of the contact pads in a row of contact pads along the pixel array can be used, and connected to the clock gated latches in a binary tree structure.

[0086] Figure 13An arrangement of contact pads and connections for clock-gated latches in a bilateral structure is shown. The iToF sensor 6 comprises a driver and clock section 112 which comprises the clock and driver for all pixels of the iToF sensor 6. A contact pad 114A is arranged at the bottom of the pixel array and at the left side of the pixel array. Both contact pads 114A and 114B are connected to a power supply. Furthermore, the contact pads 114A and 114B connect the power supply to the latches in each row of the pixel array via conductive lines 116. The power supply should be strong enough to counteract the horizontal gradient. Another possibility is to place only one pad at the left side of the pixel array or only one pad at the right side. If there is one contact pad on each side, or only one pad on one side, the routing lines have to be strong enough, or the resistance small enough, to avoid a fan-out gradient. Alternatively, in another embodiment, the contact pads have already been installed and it has to be decided which of the already installed contact pads should be used. In this case, the installed pads can form a line along the pixel array. In this case, the contact pad located left of the line of contact pads or the contact pad located right of the line of contact pads, or one contact pad located left of the line of contact pads and one contact pad located right of the line of contact pads can be used to power the clock-gated latches as described above.

[0087] Simulation results

[0088] Tables 1 to 4d show the different fall time tf simulation results of the demodulation signal GDA or GDB of an iToF sensor with clock-gated latches (Tables 3 and 4) and without clock-gated latches (Tables 1 and 2). The fall time (pulse decay time) tf is the time it takes for the signal amplitude to fall from one specified value (80% of the peak value in our simulation) to another specified value (20% of the maximum value in the simulation). The simulation was performed at a clock signal frequency of 200 MHz. Furthermore, different corners of the CMOS process were simulated, namely: TT for typical corners of nmos and pmos; SS for slow corners of nmos and pmos; FF for fast corners of nmos and pmos; FS (or fnsp) for fast corner of nmos and slow corner of pmos; SF (or snfp) for slow corner of nmos and fast corner of pmos.

[0089] Table 1 shows the fall time tf simulation results of the demodulation signal GDA or GDB measured at the top of the pixel array without latches.

[0090] Table 1 - Simulation results of the fall time tf of the demodulation signal GDA or GDB measured at the top of the pixel array without latches.

[0091] Proximal TF TT SS FF FS SF VDD = 1.45V 1.348ns 1.418ns 1.284ns 1.408ns 1.298ns VDD = 1.55V 1.293ns 1.351ns 1.235ns 1.348ns 1.241ns VDD = 1.65V 1.244ns 1.301ns 1.201ns 1.297ns 1.201ns

[0092] Table 2 shows the fall time tf simulation results for the demodulation signal GDA or GDB measured at the bottom of the pixel array without latches.

[0093] Table 2 - Fall time tf simulation results for the demodulation signal GDA or GDB measured at the top of the pixel array with latches.

[0094] Remote TF TT SS FF FS SF VDD = 1.45V 1.544ns 1.619ns 1.484ns 1.616ns 1.483ns VDD = 1.55V 1.489ns 1.545ns 1.437ns 1.550ns 1.431ns VDD = 1.65V 1.444ns 1.495ns 1.405ns 1.497ns 1.394ns

[0095] Table 3 shows the fall time tf simulation results for the demodulation signal GDA or GDB measured at the top of the pixel array with latches.

[0096] Table 3 - Fall time tf simulation results for the demodulation signal GDA or GDB measured at the top of the pixel array with latches.

[0097]

[0098]

[0099] Table 4 shows the fall time tf simulation results for the demodulation signal GDA or GDB measured at the bottom of the pixel array with latches.

[0100] Table 4 - Fall time tf simulation results for the demodulation signal GDA or GDB measured at the top of the pixel array with latches.

[0101] Remote TF TT SS FF FS SF VDD = 1.45V 1.220ns 1.232ns 1.205ns 1.234ns 1.216ns VDD = 1.55V 1.209ns 1.224ns 1.196ns 1.219ns 1.198ns VDD = 1.65V 1.200ns 1.211ns 1.187ns 1.212ns 1.188ns

[0102] It should be appreciated that the embodiments describe exemplary timing diagrams with the timing diagrams having an example ordering. However, the specific order of the method steps is for illustrative purposes only and should not be construed as having a binding force. For example, the steps signal Integration Enable, LSR, GDA, GDB, or Latch Enable in Figure 8 may be exchanged. Figure 10 The same is true.

[0103] Note that the present technology can also be configured as follows:

[0104] (1) An electronic device comprising a clock-gated latch (40; 50; 60A; 60B; 91A; 91B) between two routing lines (36A, 36B) that transmit a demodulation signal (GDA, GDB) from a demodulation driver (20A) to a pixel (7) of a pixel column of a pixel array (21).

[0105] (2) The electronic device according to (1), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) improves the fall time (tf) of the demodulated signal (GDA; GDB) transmitted by the routing line (36A; 36B).

[0106] (3) The electronic device according to (1) or (2), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is mounted on the top side of the pixel column.

[0107] (4) The electronic device according to any one of (4), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is directly mounted above the first pixel (7) of the pixel column.

[0108] (5) The electronic device according to any one of claims (1) to (2), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is mounted on the bottom side of the pixel column.

[0109] (6) The electronic device according to (5), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is directly mounted below the last pixel (7) of the pixel column.

[0110] (7) The electronic device according to (1) or (2), wherein a first clock-gated latch (60A; 91A) is mounted on the top side of the pixel column and a second clock-gated latch (60B; 91B) is mounted on the bottom side of the pixel column.

[0111] (8) The electronic device according to (7), wherein the first clock-gated latch (60A; 91A) is directly mounted above the first pixel (7) of the pixel column and the second clock-gated latch (60B; 91B) is directly mounted below the last pixel (7) of the pixel column.

[0112] (9) The electronic device according to any one of (1) to (8), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) comprises two inverter gates.

[0113] (10) The electronic device according to any one of (1) to (9), wherein the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) comprises a latch enable input (EN).

[0114] (11) The electronic device according to any one of claims (1) to (10), wherein a clock signal (LatchEnable; Latch Enable_2) enables / disables the clock-gated latch (40; 50; 60A; 60B; 91A; 91B).

[0115] (12) The electronic device according to (11), wherein the clock signal (Latch Enable) is generated by a latch clock.

[0116] (13) The electronic device according to claim (11), wherein the clock signal (Latch Enable_2) is generated based on an overflow transistor gate signal (OFG).

[0117] (14) The electronic device according to (13) or (14), wherein the clock signal (Latch Enable_2) is generated by inverting the overflow transistor gate signal (OFG).

[0118] (15) The electronic device according to any one of claims (1) to (14), wherein the contact pad for the power supply of the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is mounted in the middle of the array of pixels (21).

[0119] (16) The electronic device according to any one of (1) to (15), wherein a first contact pad for the power supply of the clock-gated latch (40; 50; 60A; 60B; 91A; 91B) is mounted on the left side of the array of pixels (21) and a second contact pad for the power supply of the clock-gated latch (40, 50; 60B, 60A; 91A, 91B) is mounted on the right side of the array of pixels (21).

[0120] (17) The electronic device according to any one of (1) to (16), wherein the electronic device is a time-of-flight camera.

[0121] (18) A method comprising controlling a clock-gated latch (40; 50; 60A; 60B; 91A; 91B) located between two routing lines (36A, 36B) that transmit demodulation signals (GDA, GDB) from a demodulation driver (20A) to pixels (7) of a column of pixels of an array of pixels (21).

[0122] (19) A computer program comprising instructions which, when executed on a processor, control a clock-gated latch (40; 50; 60A; 60B; 91A; 91B) located between two routing lines (36A, 36B) that transmit demodulation signals (GDA, GDB) from a demodulation driver (20A) to pixels (7) of a column of pixels of an array of pixels (21).

Claims

1. An electronic device comprising a clock-gated latch between two routing lines that transmit demodulated signals from a demodulation driver to pixels in a pixel column of a pixel array, wherein, The routing line connects the array of demodulation drivers to the pixels within the pixel array, and the demodulated signal is used to drive the pixels. The clock-gated latch includes two inverter gates and includes a latch enable input that improves the fall time of the demodulated signal transmitted by the routing line by changing the latch state to enable or disable.

2. The electronic device according to claim 1, wherein, The clock-gated latch is mounted on the top side of the pixel column.

3. The electronic device according to claim 2, wherein, The clock-gated latch is mounted directly above the first pixel of the pixel column.

4. The electronic device according to claim 1, wherein, The clock-gated latch is installed on the bottom side of the pixel column.

5. The electronic device according to claim 4, wherein, The clock-gated latch is installed directly below the last pixel of the pixel column.

6. The electronic device according to claim 1, wherein, A first clock-gated latch is installed on the top side of the pixel column, and a second clock-gated latch is installed on the bottom side of the pixel column.

7. The electronic device according to claim 6, wherein, The first clock-gated latch is installed directly above the first pixel of the pixel column, and the second clock-gated latch is installed directly below the last pixel of the pixel column.

8. The electronic device according to claim 1, wherein, The clock signal enables / disables the clock-gated latch.

9. The electronic device according to claim 8, wherein, The clock signal is generated by the latch clock.

10. The electronic device according to claim 8, wherein, The clock signal is generated based on the gate signal of an overflow transistor, which is included in the pixel.

11. The electronic device according to claim 10, wherein, The clock signal is generated by inverting the gate signal of the overflow transistor.

12. The electronic device according to claim 1, wherein, The contact pads for the power supply of the clock-gated latch are mounted in the middle of the pixel array.

13. The electronic device according to claim 1, wherein, The first contact pad for the power supply of the clock-gated latch is mounted on the left side of the pixel array, and the second contact pad for the power supply of the clock-gated latch is mounted on the right side of the pixel array.

14. The electronic device according to claim 1, wherein, The electronic device is a time-of-flight camera.

15. A method comprising: A clock-gated latch is configured to be located between two routing lines that transmit demodulated signals from demodulation drivers to pixels in a pixel column of a pixel array. The routing lines connect the array of demodulation drivers to the pixels within the pixel array, and the demodulated signals are used to drive the pixels. The clock-gated latch includes two inverter gates and includes a latch enable input that improves the fall time of the demodulated signal transmitted by the routing lines by changing the latch state to enable or disable.

16. A computer program product comprising instructions that, when executed on a processor, control a clock-gated latch located between two routing lines that transmit demodulated signals from a demodulation driver to pixels in a pixel column of a pixel array, wherein... The routing line connects the array of demodulation drivers to the pixels within the pixel array, and the demodulated signal is used to drive the pixels. The clock-gated latch includes two inverter gates and includes a latch enable input that improves the fall time of the demodulated signal transmitted by the routing line by changing the latch state to enable or disable.

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