Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises an insulating substrate, an alignment mark and a first insulating layer arranged on the insulating substrate. The first insulating layer is arranged on the side of the alignment mark away from the insulating substrate. The first insulating layer is formed with a through hole exposing the alignment mark. In the embodiment of the application, a raised layer is arranged between the alignment mark and the insulating substrate. The raised layer is arranged corresponding to the through hole. The alignment mark covers the raised layer. The height difference between the alignment mark and the first insulating layer on the two sides adjacent to the alignment mark is reduced. In the rubbing orientation process of the array substrate, the rubbing cloth is prevented from being deformed or even damaged when passing through the position of the mark pattern, so that the formation of the orientation layer groove of the array substrate and the subsequent liquid crystal drop are improved. The risk of display spot phenomenon of the display panel is reduced, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a display panel. BACKGROUND

[0002] In the manufacturing process of liquid crystal panel, mark has a very important role, for example, when the precise measuring instrument coordinates positioning and the exposure machine exposure alignment are carried out, the position of mark needs to be read; or when the thin film transistor array substrate and the color filter substrate are assembled, the mark also needs to be confirmed.

[0003] In the current design of thin film transistor array substrate, the mark is designed on the periphery of the thin film transistor array substrate, and most of the marks are made of gate metal, and then an insulating film is deposited on the non-pixel area where the mark is located. In order to better display the position of the mark, the insulating layer is usually arranged on the area in the non-pixel area except the mark, so that a step is formed between the mark and the adjacent two sides of the insulating layer on the array substrate. When the rubbing roller is used to rub the array substrate, the rubbing cloth on the rubbing roller is easy to deform or even break when passing through the step position. The deformed or broken rubbing cloth passes through the display area of the array substrate, which affects the formation of the orientation layer groove of the array substrate and the subsequent drop of liquid crystal. Therefore, when the array substrate is applied to the display device, display mura will be formed, which affects the display effect of the display device. SUMMARY

[0004] The embodiments of the present application provide an array substrate and a display panel to improve the display Mura phenomenon and improve the display effect.

[0005] To achieve the above functions, the technical solutions provided by the embodiments of the present application are as follows:

[0006] The embodiments of the present application provide an array substrate, comprising:

[0007] An insulating substrate;

[0008] A mark is arranged on the insulating substrate;

[0009] A first insulating layer is arranged on the side of the mark away from the insulating substrate, and the first insulating layer forms a through hole exposing the mark;

[0010] The array substrate further comprises a pad layer between the mark and the insulating substrate, the pad layer is arranged corresponding to the through hole, and the mark covers the pad layer.

[0011] In the array substrate provided in this application embodiment, the shape of the through hole is the same as the shape of the cross-section of the alignment mark in the first direction, and the alignment mark is located in the through hole; wherein, the first direction is parallel to the side of the insulating substrate near the alignment mark.

[0012] In the array substrate provided in the embodiments of this application, the orthographic projection of the first insulating layer on the insulating substrate does not overlap with the orthographic projection of the alignment mark on the insulating substrate.

[0013] In the array substrate provided in the embodiments of this application, the array substrate further includes a first electrode located on the side of the first insulating layer away from the insulating substrate. One side of the first electrode passes through the sidewall of the through hole and is connected to the alignment mark, and the other side of the first electrode is located on the side of the first insulating layer away from the insulating substrate.

[0014] In the array substrate provided in the embodiments of this application, the first electrode includes a first sub-electrode located on the side of the insulating layer away from the insulating substrate and a second sub-electrode located at the bottom of the via, the second sub-electrode being connected to the alignment mark; wherein, in the direction perpendicular to the insulating substrate, the vertical distance between the side of the first sub-electrode away from the insulating substrate and the side of the second sub-electrode away from the first insulating layer is greater than or equal to 150 angstroms and less than or equal to 6000 angstroms.

[0015] In the array substrate provided in the embodiments of this application, the array substrate includes a second insulating layer located between the pad layer and the insulating substrate. The second insulating layer includes a boss corresponding to the through hole, and the alignment mark is located on the upper surface of the boss.

[0016] In the array substrate provided in the embodiments of this application, the array substrate includes a second electrode located between the second insulating layer and the insulating substrate, and the second electrode is disposed corresponding to the through hole.

[0017] In the array substrate provided in the embodiments of this application, the array substrate includes a display area and a non-display area adjacent to the display area, and the non-display area includes an alignment mark area;

[0018] The array substrate includes a first metal layer on the insulating substrate. The first metal layer includes a gate in the display area and a first metal sublayer in the non-display area. In a first direction, the shape of the cross-section of the gate is the same as the shape of the cross-section of the first metal sublayer. The first metal sublayer includes an alignment mark in the alignment mark area. The first direction is parallel to the side of the insulating substrate near the first metal sublayer.

[0019] In the array substrate provided in the embodiments of this application, the via is located on the side of the first metal sublayer away from the insulating substrate, and the via exposes at least a portion of the first metal sublayer.

[0020] A display panel comprising any of the array substrates described above.

[0021] The beneficial effects of this application embodiment are as follows: This application embodiment provides an array substrate and a display panel. The array substrate includes an insulating substrate, alignment marks disposed on the insulating substrate, and a first insulating layer. The first insulating layer is disposed on the side of the alignment marks away from the insulating substrate, and the first insulating layer has through holes that expose the alignment marks. In this application embodiment, by providing a padding layer between the alignment marks and the insulating substrate, the padding layer is disposed corresponding to the through holes, and the alignment marks cover the padding layer, thereby reducing the step height between the alignment marks and the first insulating layers on their adjacent sides. This improves the problem of deformation or even damage of the friction cloth when passing through the mark pattern position during the friction alignment of the array substrate, which affects the formation of alignment layer trenches and subsequent liquid crystal dispensing, thereby reducing the risk of display spots on the display panel. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of an existing array substrate;

[0024] Figure 2 This is a first cross-sectional schematic diagram of the array substrate provided in the embodiments of this application;

[0025] Figure 3 A top view of the alignment mark provided in an embodiment of this application;

[0026] Figure 4 This is a second cross-sectional schematic diagram of the array substrate provided in the embodiments of this application;

[0027] Figure 5 Top cross-sectional view of the array substrate provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0029] This application provides an array substrate and a display device. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0030] Please see Figures 2 to 5 This application provides an array substrate 100 and a display panel, wherein the array substrate 100 includes:

[0031] Insulating substrate 10;

[0032] Alignment mark 40A is disposed on the insulating substrate 10;

[0033] A first insulating layer 30 is disposed on the side of the alignment mark 40A away from the insulating substrate 10, and the first insulating layer 30 has a through hole 31 exposing the alignment mark 40A;

[0034] The array substrate 100 further includes a padding layer 50 located between the alignment mark 40A and the insulating substrate 10. The padding layer 50 is disposed corresponding to the through hole 31, and the alignment mark 40A covers the padding layer 50.

[0035] Understandably, please combine Figure 1This is a schematic diagram of the structure of an existing array substrate. In the design of the existing array substrate 100, a pair of alignment mark areas MD are set in the non-display area ND of the array substrate 100. A second insulating layer 20 is set on the insulating substrate 10. The second insulating layer 20 includes a groove 21 located in the alignment mark area MD. The array substrate 100 includes an alignment mark 40A located in the groove 21. The alignment mark 40A is located in the alignment mark area MD. Then, a first insulating layer 30 is deposited on the non-display area ND where the alignment mark 40A is located. In this case, the alignment mark 40A is conventionally made of metal. In order to better show the position of the alignment mark 40A, the first insulating layer 30 usually has a through hole 31. The through hole 31 passes through the first insulating layer 30 and exposes the alignment mark 40A. Therefore, a step P is formed between the alignment mark 40A and the first insulating layers 30 on both sides of the array substrate 100. Figure 1 As shown, the distance d1 of the step difference P is greater than 6000 angstroms. When the array substrate is rubbed with a friction roller, the rubbing cloth on the friction roller is easily deformed or even damaged when it passes through the step difference position. The deformed or damaged rubbing cloth will affect the formation of the alignment layer trench of the array substrate and the subsequent liquid crystal dispensing when it passes through the display area of ​​the array substrate. As a result, when the array substrate is used for display in a display device, display spots will be formed, affecting the display effect of the display device.

[0036] It is understood that, in this embodiment of the application, a padding layer 50 is provided between the alignment mark 40A and the insulating substrate 10. The padding layer 50 is provided corresponding to the through hole 31. The alignment mark 40A covers the padding layer 50, thereby reducing the step height P between the alignment mark 40A and the first insulating layer 30 on its adjacent sides. This is to improve the situation where, during the friction alignment of the array substrate 100, the friction cloth is deformed or even damaged when passing through the position of the alignment mark 40A, which affects the formation of the alignment layer trench of the array substrate and the subsequent liquid crystal dispensing, thereby reducing the risk of display spots on the display panel.

[0037] The technical solution of this application will now be described in conjunction with specific embodiments.

[0038] In one embodiment, please refer to Figure 2 and Figure 3 ;in, Figure 2 This is a first cross-sectional schematic diagram of the array substrate provided in the embodiments of this application; Figure 3 This is a top view of the alignment mark provided in an embodiment of this application.

[0039] This embodiment provides an array substrate 100, which includes an insulating substrate 10, an alignment mark 40A disposed on the insulating substrate 10, and a first insulating layer 30. The first insulating layer 30 is disposed on the side of the alignment mark 40A away from the insulating substrate 10. It should be noted that a step difference P is formed between the alignment mark 40A and the first insulating layer 30 on the adjacent two sides on the array substrate 100.

[0040] The insulating substrate 10 includes, but is not limited to, a rigid substrate or a flexible substrate. When the insulating substrate 10 is a rigid substrate, the material can be metal or glass. When the insulating substrate 10 is a flexible substrate, the material can include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane-based resin, cellulose resin, siloxane resin, polyimide-based resin, and polyamide-based resin. The material of the first insulating layer 30 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x ), or a double-layer structure of the above films, wherein the first insulating layer 30 includes, but is not limited to, a passivation layer.

[0041] Specifically, the array substrate 100 includes a display area (not shown in the figure) and a non-display area ND adjacent to the display area. The non-display area ND includes a alignment mark area MD. The alignment mark 40A is located within the alignment mark area MD. In this embodiment, in order to better display the position of the alignment mark 40A, the first insulating layer 30 is formed with a through hole 31 that exposes the alignment mark 40A. The through hole 31 passes through the first insulating layer 30 and is located in the alignment mark area MD.

[0042] The array substrate 100 further includes a padding layer 50 located between the alignment mark 40A and the insulating substrate 10. The padding layer 50 is disposed corresponding to the through hole 31, and the alignment mark 40A covers the padding layer 50. Specifically, the padding layer 50 can be made of an insulating material, and the material of the padding layer 50 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). x ), or a double-layer structure of the above membrane layers.

[0043] It is understood that this application reduces the step height P between the alignment mark 40A and the insulating substrate 10 by providing a padding layer 50 between the alignment mark 40A and the insulating substrate 10, with the padding layer 50 corresponding to the through hole 31 and the alignment mark 40A covering the padding layer 50. This reduces the risk of display spots on the display panel by providing a padding layer 50 between the alignment mark 40A and the first insulating layer 30 on its adjacent sides.

[0044] In this embodiment, the shape of the cross-section of the alignment mark 40A includes, but is not limited to, a cross shape, a triangle shape, a circle, or an "L" shape. Preferably, in this embodiment, the cross-section of the alignment mark 40A is "L" shaped. The shape of the through hole 31 is the same as the shape of the cross-section of the alignment mark 40A in the first direction X, and the alignment mark 40A is located inside the through hole 31. The first direction X is parallel to the side of the insulating substrate 10 near the alignment mark 40A. Specifically, this embodiment uses the first direction X to describe the technical solution of this application.

[0045] Furthermore, the thickness of the padding layer 50 is greater than or equal to 800 angstroms and less than or equal to 1150 angstroms, and the thickness of the padding layer 50 is preferably 800 angstroms, 1000 angstroms, or 1150 angstroms. It can be understood that in this embodiment, by setting the shape of the through hole 31 to be the same as the cross-sectional shape of the alignment mark 40A, and by having both the alignment mark 40A and the spacer layer located within the through hole 31, this avoids the situation where the distance between the alignment mark 40A and the sidewall of the through hole 31 is too large, which would otherwise lead to… The width of the step difference P between the alignment mark 40A and the first insulating layer 30 on its adjacent sides is relatively large. By setting the thickness of the pad layer 50 to be greater than or equal to 800 angstroms and less than or equal to 1150 angstroms, the distance between the alignment mark 40A and the first insulating layer 30 on the side away from the insulating substrate 10 is avoided to be greater than 6000 angstroms. This improves the phenomenon that the friction cloth is deformed or even damaged when passing the position of the alignment mark 40A during the friction alignment of the array substrate 100.

[0046] Meanwhile, since the shape of the through hole 31 is the same as the cross-sectional shape of the alignment mark 40A, the orthographic projection of the first insulating layer 30 on the insulating substrate 10 does not overlap with the orthographic projection of the alignment mark 40A on the insulating substrate 10. This avoids the first insulating layer 30 forming a protrusion in the alignment mark area MD when it covers the alignment mark 40A, which would cause the step height P between the alignment mark 40A and the first insulating layers 30 on its adjacent sides to increase.

[0047] Furthermore, in this embodiment, the array substrate 100 further includes a first electrode 61 located on the side of the first insulating layer 30 away from the insulating substrate 10. One side of the first electrode 61 passes through the sidewall of the through hole 31 and is connected to the alignment mark 40A. The other side of the first electrode 61 is located on the side of the first insulating layer 30 away from the insulating substrate 10. The second electrode 62 is a transparent electrode, and the material of the second electrode 62 includes, but is not limited to, indium tin oxide (ITO), thereby preventing the first electrode 61 from obstructing the alignment mark 40A.

[0048] Specifically, the first electrode 61 includes a first sub-electrode 61A located on the side of the insulating layer away from the insulating substrate 10, and a second sub-electrode 61B located at the bottom of the through hole 31. The second sub-electrode 61B is connected to the alignment mark 40A. In the direction perpendicular to the insulating substrate 10, the vertical distance d2 between the side of the first sub-electrode 61A away from the insulating substrate 10 and the side of the second sub-electrode 61B away from the first insulating layer 30 is greater than or equal to 150 angstroms and less than or equal to 6000 angstroms, thereby further reducing the step height P between the alignment mark 40A and the first insulating layer 30 on its adjacent sides. This improves the situation where, during the rubbing alignment of the array substrate 100, the rubbing cloth is deformed or even damaged when passing the alignment mark 40A, which affects the formation of the alignment layer trench of the array substrate 100 and the subsequent liquid crystal dispensing, thereby reducing the risk of display spots on the display panel.

[0049] In this embodiment, the array substrate 100 further includes a second insulating layer 20 located between the pad layer 50 and the insulating substrate 10. The second insulating layer 20 includes a boss 22 corresponding to the through hole 31. The alignment mark 40A is located on the upper surface 22A of the boss 22. The material of the second insulating layer 20 includes, but is not limited to, monolayer silicon nitride (Si3N4), monolayer silicon dioxide (SiO2), and monolayer silicon oxynitride (SiON). xThe second insulating layer 20 can be a gate insulating layer, or a double-layer structure of the above films. Specifically, the array substrate 100 further includes a second electrode 62 located between the second insulating layer 20 and the insulating substrate 10. The second insulating layer 20 covers the second electrode 62, and the second electrode 62 is located within the alignment mark region MD, thereby forming the protrusion 22 at the position corresponding to the second electrode 62 in the second insulating layer 20. The material of the second electrode 62 includes, but is not limited to, indium tin oxide (ITO), and the second electrode 62 includes, but is not limited to, a common electrode. Therefore, the technical means adopted in this embodiment does not add any additional processes, and the process is mature and easy to mass-produce.

[0050] It is understood that in this embodiment, by providing a second insulating layer 20 between the pad layer 50 and the insulating substrate 10, the second insulating layer 20 includes a boss 22 corresponding to the through hole 31, and the alignment mark 40A is located on the upper surface 22A of the boss 22, thereby further reducing the step height P between the alignment mark 40A and the first insulating layer 30 on its adjacent sides. This is to improve the situation where, during the friction alignment process of the array substrate 100, the friction cloth is deformed or even damaged when passing the position of the alignment mark 40A, which affects the formation of the alignment layer trench of the array substrate 100 and the subsequent liquid crystal dispensing, thereby reducing the risk of display spots on the display panel.

[0051] Please combine Figure 4 and Figure 5 ;in, Figure 4 This is a second cross-sectional schematic diagram of the array substrate provided in the embodiments of this application; Figure 5 This is a top cross-sectional view of the array substrate provided in an embodiment of this application.

[0052] In this embodiment, the structure of the array substrate 100 is similar to / the same as the structure of the array substrate 100 provided in the above embodiments. Please refer to the description of the array substrate 100 in the above embodiments for details, which will not be repeated here. The only difference between the two is:

[0053] In this embodiment, the array substrate 100 includes a first metal layer 40 located on the insulating substrate 10. The first metal layer 40 includes a gate (not shown in the figure) located in the display area and a first metal sub-layer 41 located in the non-display area ND. In the first direction X, the shape of the cross-section of the gate is the same as the shape of the cross-section of the first metal sub-layer 41. The first metal sub-layer 41 includes the alignment mark 40A located in the alignment mark area MD. The first direction X is parallel to the side of the insulating substrate 10 near the first metal sub-layer 41.

[0054] In this embodiment, the material of the first metal layer 40 includes, but is not limited to, at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).

[0055] In this embodiment, the shape of the through hole 31 includes, but is not limited to, a cross shape, a triangle shape, a circle, or an "L" shape. Preferably, in this embodiment, the shape of the through hole 31 is an "L" shape. The through hole 31 is located on the side of the first metal sublayer 41 away from the insulating substrate 10, and the through hole 31 exposes at least a portion of the first metal sublayer 41. The portion of the first metal sublayer 41 exposed by the through hole 31 is the alignment mark 40A. The shape of the through hole 31 is the same as the shape of the alignment mark 40A projected onto the insulating substrate 10.

[0056] It is understood that, in this embodiment, by setting the first metal layer 40 to include a gate located in the display area and a first metal sub-layer 41 located in the non-display area ND, the shape of the cross-section of the gate is the same as the shape of the cross-section of the first metal sub-layer 41, and the first metal sub-layer 41 includes the alignment mark 40A located in the alignment mark area MD, no additional process steps are required, saving process time and process cost, and simplifying the process flow of the alignment mark 40A; furthermore, by setting the via 31 to be located on the side of the first metal sub-layer 41 away from the insulating substrate 10, and the via 31 to expose at least part of the first metal sub-layer 41, and the shape of the via 31 is the same as the shape of the alignment mark 40A projected onto the insulating substrate 10, the shape of the alignment mark 40A can be controlled simply by controlling the shape of the via 31, making the operation simple.

[0057] This embodiment provides a display panel, which includes the array substrate described in any of the above embodiments.

[0058] It is understood that the array substrate has been described in detail in the above embodiments, and will not be repeated here.

[0059] Furthermore, this embodiment also provides a mobile terminal, which includes a terminal body and a display panel. The display panel includes the array substrate described in any of the above embodiments, and the terminal body and the display panel are integrated into one unit.

[0060] In specific applications, the mobile terminal can be the display screen of devices such as smartphones, tablets, laptops, smart bracelets, smartwatches, smart glasses, smart helmets, desktop computers, smart TVs, or digital cameras, and can even be applied to electronic devices with flexible displays.

[0061] In summary, this application provides an array substrate and a display panel. The array substrate includes an insulating substrate, alignment marks disposed on the insulating substrate, and a first insulating layer. The first insulating layer is disposed on the side of the alignment marks away from the insulating substrate, and the first insulating layer has through holes exposing the alignment marks. In this embodiment, a padding layer is disposed between the alignment marks and the insulating substrate, the padding layer corresponding to the through holes, and the alignment marks cover the padding layer. This reduces the step height between the alignment marks and the first insulating layers on their adjacent sides, thereby improving the situation where, during the rubbing alignment of the array substrate, the rubbing cloth deforms or even breaks when passing through the mark pattern position, which affects the formation of alignment layer trenches and subsequent liquid crystal dispensing. This reduces the risk of display spots on the display panel and improves the display effect.

[0062] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0063] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, include: Insulating substrate; Alignment marks are provided on the insulating substrate; A first insulating layer is disposed on the insulating substrate, and the first insulating layer has through holes that expose the alignment marks; A second insulating layer is disposed between the insulating substrate and the first insulating layer; A first electrode is disposed on the side of the first insulating layer away from the insulating substrate. One side of the first electrode passes through the sidewall of the through hole and is connected to the alignment mark. The other side of the first electrode is located on the side of the first insulating layer away from the insulating substrate. The second electrode is disposed between the second insulating layer and the insulating substrate, and the second electrode is disposed corresponding to the through hole; The second insulating layer includes a boss corresponding to the second electrode. The array substrate also includes a pad layer located between the alignment mark and the insulating substrate. The pad layer is located on the boss. Both the pad layer and the alignment mark are located in the through hole, and the alignment mark covers the pad layer.

2. The array substrate according to claim 1, characterized in that, The shape of the through hole is the same as the shape of the cross-section of the alignment mark in a first direction; wherein the first direction is parallel to the side of the insulating substrate near the alignment mark.

3. The array substrate according to claim 2, characterized in that, The orthographic projection of the first insulating layer on the insulating substrate does not overlap with the orthographic projection of the alignment mark on the insulating substrate.

4. The array substrate according to claim 1, characterized in that, The first electrode includes a first sub-electrode located on the side of the insulating layer away from the insulating substrate and a second sub-electrode located at the bottom of the through hole, the second sub-electrode being connected to the alignment mark; wherein, in a direction perpendicular to the insulating substrate, the vertical distance between the side of the first sub-electrode away from the insulating substrate and the side of the second sub-electrode away from the first insulating layer is greater than or equal to 150 angstroms and less than or equal to 6000 angstroms.

5. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a non-display area adjacent to the display area, the non-display area including an alignment mark area; The array substrate includes a first metal layer on the insulating substrate. The first metal layer includes a gate in the display area and a first metal sublayer in the non-display area. In a first direction, the shape of the cross-section of the gate is the same as the shape of the cross-section of the first metal sublayer. The first metal sublayer includes an alignment mark in the alignment mark area. The first direction is parallel to the side of the insulating substrate near the first metal sublayer.

6. The array substrate according to claim 5, characterized in that, The via is located on the side of the first metal sublayer away from the insulating substrate, and the via exposes at least a portion of the first metal sublayer.

7. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-6.

Images