A simulation scheduling method and system

Abstract

The application provides a simulation scheduling method and system, and belongs to the technical field of control simulation. The method comprises the following steps: constructing a Simulink mathematical model and generating an initial model file; converting the initial model file into an RTW file; calling a target language compiler to convert the RTW file into a to-be-called model file; calling a make tool to automatically generate a code and to compile the to-be-called model file to generate an execution model file; and executing closed-loop simulation in a Vxworks system according to the execution model file. The application realizes simulation scheduling distribution of the whole system in the form of auxiliary clock scheduling tasks, realizes simulation scheduling between a Simulink simulation system and a Vxworks operating system, and improves the real-time performance of the Simulink simulation process.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of control simulation, and relates to a control simulation scheduling technology, in particular to a simulation scheduling method and system. BACKGROUND

[0002] RTW is a Simulink-based code generation environment, which can directly generate optimized and portable embedded real-time codes from Simulink models, and can automatically generate executable programs suitable for the software and hardware environment of the target machine according to the target machine configuration. The VxWorks operating system is widely used in high-precision and high-tech fields such as communication, military, aviation and aerospace, and fields with extremely high real-time requirements due to its good reliability and excellent real-time performance.

[0003] As the real-time requirement of the simulation system in the prior art is gradually improved, the simulation under Simulink alone uses the Windows operating system, which is often interfered by other tasks and delayed in execution, resulting in a large error and failing to accurately complete the real-time task. The real-time performance of the VxWorks operating system is good, and the process scheduling, inter-process communication and interrupt handling of the system itself are refined, and the delay caused is very short. However, how to realize simulation scheduling between the Simulink simulation system and the VxWorks operating system to realize the real-time performance of the Simulink simulation process is a difficulty in the technical field. SUMMARY

[0004] In view of the poor real-time performance of the Simulink simulation process in the prior art, which leads to task delay, large error and failure to accurately complete the task, the application provides a simulation scheduling method and system.

[0005] In use, the user only needs to build a mathematical simulation model in Simulink, and compile and download it to a target machine running the VxWorks real-time operating system through RTW; the application realizes simulation scheduling distribution of the overall system by using the form of auxiliary clock scheduling tasks, and the VxWorks real-time operating system controls the overall simulation through the form of auxiliary clock; the application reduces the amount of simulation code writing, guarantees the real-time performance of system simulation, and improves the performance of system simulation; and the specific technical scheme is as follows:

[0006] A simulation scheduling method, comprising the following steps:

[0007] building a Simulink mathematical model and generating an initial model file;

[0008] converting the initial model file into an RTW file;

[0009] calling a target language compiler to convert the RTW file into a to-be-called model file;

[0010] calling a make tool to automatically compile codes, and solving the to-be-called model file to generate an execution model file;

[0011] performing closed-loop simulation in a Vxworks system according to the execution model file.

[0012] Further limitation, the process of building a Simulink mathematical model and generating a model file further comprises

[0013] defining, building and / or packaging a hardware driver file based on a VxWorks kernel program;

[0014] establishing communication between the driver module and the simulation board card.

[0015] Further limitation, the process of calling a make tool to automatically compile codes, and solving the to-be-called model file to generate an execution model file specifically comprises:

[0016] calling a make tool to automatically compile codes, and identifying and checking the to-be-called model file through the codes;

[0017] setting a priority of a Simulink mathematical model solving task;

[0018] initializing a memory space, a sampling step, a semaphore and a solving running parameter of the Simulink mathematical model;

[0019] creating a solving task of the Simulink mathematical model, and controlling the solving process through an auxiliary clock, finally generating an execution model file, ending the solving task, and deleting the task and releasing the memory.

[0020] Further limitation, the process of creating a solving task of the Simulink mathematical model, and controlling the solving process through an auxiliary clock specifically comprises:

[0021] creating a solving task of the Simulink mathematical model;

[0022] judging a type of the solving task;

[0023] if it is a single-task solving, detecting a running state of the Simulink mathematical model, calling the to-be-called model file to calculate the Simulink mathematical model according to the running state, and releasing a semaphore of the single-task solving;

[0024] If the multi-task solution is calculated, the solution task of the Simulink mathematical model is divided into multiple sub-task solutions and is detected respectively, the to-be-called model file is called according to the running state of each sub-task solution to calculate the Simulink mathematical model, and the semaphores of each sub-task solution are released.

[0025] With further limitation, the process of executing the closed-loop simulation in the Vxworks system according to the execution model file specifically includes:

[0026] The entry function in the execution model file is called to initialize the interrupt function of the auxiliary clock;

[0027] The to-be-executed model file is calculated by the clock function of the auxiliary clock, and whether the sampling time point of the sub-task is reached is detected;

[0028] If the detection result is that the sampling time point of the sub-task is not reached, the detection step is repeated;

[0029] If the detection result is that the sampling time point of the sub-task is reached, the semaphore of the sampling time point is released;

[0030] The type of the semaphore of the sampling time point is judged;

[0031] If it is an interrupt solution semaphore, the calculation of the to-be-executed model file is suspended by the interrupt function of the auxiliary clock according to the interrupt solution semaphore;

[0032] If it is a stop solution semaphore, the termination function of the model solution is called and the memory is released according to the stop solution semaphore, and the closed-loop simulation is completed.

[0033] With further limitation, the RTW file contains the description content of the Simulink mathematical model, and the description content includes data type, data input, data output and internal logic.

[0034] An emulation scheduling system comprises

[0035] A model building module is configured to build a Simulink mathematical model and generate an initial model file;

[0036] An RTW file generating module is configured to convert the initial model file into an RTW file;

[0037] A conversion module is configured to call a target language compiler to convert the RTW file into a to-be-called model file;

[0038] A code linking module is configured to call a make tool to automatically generate and link codes, and calculate the to-be-called model file to generate an execution model file;

[0039] and an emulation module: for executing closed loop emulation in the Vxworks system according to the execution model file.

[0040] With further limitation, the model construction module further comprises defining, constructing and / or packaging hardware driver files based on VxWorks kernel program before constructing the Simulink mathematical model and generating the initial model file; and establishing communication between the driver module and the emulation board.

[0041] With further limitation, the code linking module comprises:

[0042] a detection module: for calling the make tool to automatically link the code, and identifying and checking the to-be-called model file through the code;

[0043] a priority design module: for setting the priority of the Simulink mathematical model solving task;

[0044] an initialization module: for initializing the memory space, sampling step, semaphore and solving running parameters of the Simulink mathematical model;

[0045] and a solving task creation module: for creating the solving task of the Simulink mathematical model, controlling the solving process through the auxiliary clock, finally generating the execution model file, ending the solving task, and deleting the task and releasing the memory.

[0046] A computer readable storage medium, which stores a program file, the program file is executed to realize the simulation scheduling method.

[0047] Compared with the prior art, the simulation scheduling method has the advantages that:

[0048] 1. The simulation scheduling method can be compiled and downloaded to the target machine of the VxWorks real-time operating system through RTW; the Simlink model generates the code which is called by the to-be-called model file through the automatic code generation of RTW; the to-be-called model file is modified; the simulation scheduling distribution of the whole system is realized in the form of auxiliary clock scheduling task; the simulation scheduling is realized between the Simulink simulation system and the VxWorks operating system; and the real-time performance of the Simulink simulation process is improved.

[0049] 2. The simulation scheduling method provides a new method, which controls the simulation system as a whole through the form of auxiliary clock scheduling, is beneficial to the control of the model solving operation by the peripheral device, and improves the performance of the system simulation.

[0050] 3、The application modifies the entry function of the model file to be called, so that it has three functions of program initialization, model running calculation and program ending, and is used for calling by the VxWorks operating system, and the model file to be called is generated by the method.

[0051] 4、The application sets the priority of the Simulink mathematical model checking processing task, processes the task in time, and accelerates the calculation process of the model file.

[0052] 5、The code generated by the Simulink mathematical model is called by the model file to be called in the form of a function to realize the scheduling and distribution of the whole simulation task. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 It is a process schematic diagram of the simulation scheduling method of the application;

[0054] Figure 2 It is a process schematic diagram of generating the execution model file by calculating the model file to be called;

[0055] Figure 3 It is a process schematic diagram of the closed loop simulation;

[0056] Figure 4 It is a schematic diagram of the simulation scheduling system of the application;

[0057] Figure 5 It is a schematic diagram of the code linking module. DETAILED DESCRIPTION

[0058] The technical solutions of the application will be further explained and described below in combination with the drawings and embodiments, but the application is not limited to the following described embodiments.

[0059] Embodiment 1

[0060] Referring to Figure 1 The simulation scheduling method of the embodiment comprises the following steps:

[0061] S0: defining, constructing and / or encapsulating the hardware driver file based on the VxWorks kernel program; and establishing the communication between the driver module and the simulation board card.

[0062] Specifically, the VxWorks kernel program defines, constructs and / or encapsulates hardware driver files, and establishes communication between the VxWorks driver module and the VxWorks simulation board card; the driver module is an auxiliary call hardware interface, and the relevant driver module is constructed through S function, and the corresponding board card and network call function encapsulated in the VxWorks are called to ensure the communication of the system.

[0063] S1: constructing a Simulink mathematical model and generating an initial model file;

[0064] Specifically, the step of constructing a Simulink mathematical model and generating an initial model file is as follows:

[0065] According to the requirement, a Simulink mathematical model is constructed through a Simulink model library, and an initial model file is generated. In the initial debugging, the initial model file can be run on the Simulink platform, and appropriate modification and adjustment can be made. When the simulation result is consistent with the requirement, step S2 can be performed. The method of constructing a Simulink mathematical model can be various, for example, a user can select through a Simulink model library according to actual requirement, or can construct individually according to the simulation test requirement.

[0066] S2: converting the initial model file into an RTW file through RTW; wherein the RTW file contains the description content of the Simulink mathematical model, and the description content includes data type, data input, data output and internal logic;

[0067] S3: converting the RTW file into a to-be-called model file through a target language compiler;

[0068] S4: automatically generating code through a make tool, identifying and checking the entry function of the to-be-called model file through the code, calling the to-be-called model file to solve, and generating an execution model file from the to-be-called model file; specifically, step S4 is: through a target language compiler-TLC language, a tornado.tlc file is selected in the embodiment, and the to-be-called model file is converted into an execution model file.

[0069] Referring to Figure 2 , specifically, step S4 is:

[0070] S4.1: calling the make tool to automatically generate the code, identifying the entry function of the called model file through the code, checking the identified called model file, converting the un-identified called model file to the external mode for interpretation, and checking the called model file; specifically, parsing the Simulink mathematical model, the parsing content including the stop time of the Simulink mathematical model and the waiting information before the simulation in the external mode starts; and identifying the entry function of the called model file, converting the un-identified called model file to the external mode for interpretation, and checking the called model file; wherein the external mode refers to the communication between the host and the target machine, the host refers to the computer running the MATLAB and Simulink environment, and the target machine refers to the computer running the execution model file generated by the RTW;

[0071] S4.2: setting the priority of the Simulink mathematical model checking processing task; the principle of setting the priority is that the calculation process of the model file is prior to the calling process of the hardware board;

[0072] S4.3: initializing the memory space, sampling step, semaphore and calculation running parameters of the Simulink mathematical model;

[0073] S4.4: creating the calculation task of the Simulink mathematical model, and calculating by calling the called model file; wherein the calculation task is divided into single task calculation and multi-task calculation, and the single task calculation and multi-task calculation need to be judged; if the calculation task is judged as single task calculation, the running state of the Simulink mathematical model is detected, the running state including normal running state, end state or error state, the model calculation running function is called according to the running state to calculate the Simulink mathematical model, and the semaphore of the single task calculation is released; if the calculation task is judged as multi-task calculation, the calculation task of the Simulink mathematical model is decomposed to form multiple sub-task calculations, the running state of the multiple sub-task calculations is detected respectively, the running state of the multiple sub-task calculations including normal running state, end state or error state, the model calculation running function is called according to the running state of each sub-task calculation to calculate the Simulink mathematical model, and the semaphore of each sub-task calculation is released; the calculation process of the called model file is controlled through the auxiliary clock, the execution model file is generated, the calculation task is ended, and the task is deleted and the memory is released. The auxiliary clock is another timer in the CPU of the target machine in addition to the system clock. Vxworks provides a series of operation interfaces same as the system clock, and the precise delay can be realized by hanging the interrupt service program, and the interrupt service is started when the timing period of the auxiliary clock is reached.

[0074] S5: download the generated execution model file to the Vxworks system, and perform closed-loop system simulation.

[0075] Referring to Figure 3 , specifically, step S5 is:

[0076] S5.1: call the entry function of the generated execution model file, and initialize the interrupt function of the auxiliary clock;

[0077] S5.3: solve the execution model file through the clock function of the auxiliary clock, and detect whether the sampling time point of the subtask is reached, if the detection result is that the sampling time point of the subtask is not reached, continue to detect, if the detection result is that the sampling time point of the subtask is reached, release the semaphore of the sampling time point; the sampling time point (including the start time, the end time, etc.) is set through the model internally, and the file generated by RTW is set according to the start time and the end time of each subtask, and the corresponding start semaphore and the end semaphore are released.

[0078] S5.4: receive the semaphore of S5.3, and judge the received semaphore of the sampling time point, if the semaphore of the sampling time point is the interrupt solving semaphore, pause the solving of the execution model file according to the interrupt solving semaphore through the interrupt function of the auxiliary clock, if the semaphore of the sampling time point is the stop solving semaphore, call the termination function of the model solving according to the stop solving semaphore and release the memory, and complete the closed-loop simulation.

[0079] Embodiment 2

[0080] Referring to Figure 4 , the simulation scheduling system of the embodiment is formed based on the simulation scheduling method of embodiment 1, and includes a model construction module, an RTW file generation module, a conversion module, a code linking module and a simulation module,

[0081] Based on the VxWorks kernel program definition, construction and / or encapsulation of the hardware driver file, the communication between the VxWorks driver module and the VxWorks simulation board card is established; the driver module is an auxiliary call hardware interface, the related driver module is constructed through the S function, and the communication of the system is ensured by calling the corresponding board card and network calling function encapsulated in VxWorks;

[0082] Model building module: used for building Simulink mathematical model and generating initial model file; specifically, building Simulink mathematical model through Simulink model library and generating initial model file, in initial debugging, running initial model file under Simulink platform and making corresponding modification and adjustment, when simulation result is consistent with requirement, running RTW file generation module; there are multiple methods for building Simulink mathematical model, for example, user can select through Simulink model library according to actual requirement, also can make individualized construction combining with simulation test requirement, etc.

[0083] RTW file generation module: used for converting initial model file into RTW file by RTW; wherein, RTW file contains description content of Simulink mathematical model, the description content includes data type, data input, data output and internal logic;

[0084] Conversion module: used for calling target language compiler to convert RTW file into called model file;

[0085] Code linking module: used for calling make tool to automatically generate code linking, identifying and checking processing of entry function of called model file through code, calling called model file to solve, generating execution model file from called model file; specifically, through target language compiler-TLC language, in the embodiment, tornado.tlc file is selected to convert called model file into execution model file;

[0086] Simulation module: used for downloading generated execution model file into Vxworks system to carry out closed loop system simulation.

[0087] Referring to Figure 5 , code linking module of the embodiment includes detection module, priority design module, initialization module and solving task creation module,

[0088] The detection module is used to call the make tool to automatically generate code, identify the entry function of the model file to be called through the code, check the identified model file to be called, convert the un-identified model file to be called to an external mode for interpretation, and check the model file to be called; specifically, the Simulink mathematical model is parsed, and the parsed content includes the stop time of the Simulink mathematical model and the waiting information before the simulation in the external mode starts; the entry function of the model file to be called is identified, the un-identified model file to be called is converted to the external mode for interpretation, and the model file to be called is checked; wherein the external mode refers to the communication between the host and the target machine, the host refers to the computer running the MATLAB and Simulink environment, and the target machine refers to the computer running the model file to be called generated by the RTW;

[0089] The priority design module is used to set the priority of the Simulink mathematical model checking processing task; the setting principle of the priority is that the calculation process of the model file is prior to the calling process of the hardware board card;

[0090] The initialization module is used to initialize the memory space, sampling step, semaphore and calculation running parameter of the Simulink mathematical model;

[0091] The calculation task creation module is used to create the calculation task of the Simulink mathematical model, and calculate through the calling of the model file to be called; wherein the calculation task is divided into single task calculation and multi-task calculation, and the single task calculation and the multi-task calculation need to be judged; if the calculation task is judged as the single task calculation, the running state of the Simulink mathematical model is detected, the running state includes the normal running state, the end state or the error state, the model calculation running function is called according to the running state to calculate the Simulink mathematical model, and the semaphore of the single task calculation is released; if the calculation task is judged as the multi-task calculation, the calculation task of the Simulink mathematical model is decomposed to form multiple sub-task calculations, the running state of the multiple sub-task calculations is detected respectively, the running state of the multiple sub-task calculations includes the normal running state, the end state or the error state, the model calculation running function is called according to the running state of each sub-task calculation to calculate the Simulink mathematical model, and the semaphore of each sub-task calculation is released; the calculation process of the model file to be called is controlled through the auxiliary clock, the execution model file is generated, the calculation task is ended, and the task is deleted and the memory is released. The auxiliary clock is another timer of the CPU of the target machine except the system clock. Vxworks provides a series of operation interfaces same as the system clock, and the precise delay can be realized by hanging the interrupt service program, and when the timing period of the auxiliary clock is reached, the interrupt service is started.

[0092] Embodiment 3

[0093] This embodiment is a computer readable storage medium storing a program file, and the program file is executed to implement the simulation scheduling method of embodiment 1.

Claims

1. A method of emulating scheduling, the method comprising: The method comprises the following steps: constructing a Simulink mathematical model and generating an initial model file; transforming the initial model file into an RTW file; calling a target language compiler to convert the RTW file into a callable model file; calling a make tool to automatically generate code for linking, solving the callable model file to generate an execution model file; wherein the process of calling the make tool to automatically generate code for linking, solving the callable model file to generate the execution model file specifically comprises: calling the make tool to automatically generate code for linking, identifying and checking the callable model file through code; setting the priority of the Simulink mathematical model solving task; initializing the memory space, sampling step, semaphore and solving running parameters of the Simulink mathematical model; creating a solving task of the Simulink mathematical model and controlling the solving process through an auxiliary clock, finally generating an execution model file, ending the solving task and deleting the task and releasing the memory; the process of creating a solving task of the Simulink mathematical model and controlling the solving process through an auxiliary clock specifically comprises: creating a solving task of the Simulink mathematical model; judging the type of the solving task; if it is a single-task solving, detecting the running state of the Simulink mathematical model, calling the callable model file for Simulink mathematical model calculation according to the running state and releasing the semaphore of the single-task solving; if it is a multi-task solving, decomposing the solving task of the Simulink mathematical model into multiple sub-task solvings and detecting them respectively, calling the callable model file for Simulink mathematical model calculation according to the running state of each sub-task solving and releasing the semaphore of each sub-task solving; performing closed-loop simulation in a Vxworks system according to the execution model file; the process of performing closed-loop simulation in a Vxworks system according to the execution model file specifically comprises: calling an entry function in the execution model file, initializing an interrupt function of the auxiliary clock; solving the execution model file through a clock function of the auxiliary clock and detecting whether the sampling time point of the sub-task is reached; if the detection result is that the sampling time point of the sub-task is not reached, repeating the detection step; if the detection result is that the sampling time point of the sub-task is reached, releasing the semaphore of the sampling time point; judging the type of the semaphore of the sampling time point; if it is an interrupt solving semaphore, pausing the solving of the execution model file through the interrupt function of the auxiliary clock according to the interrupt solving semaphore; if it is a stop solving semaphore, calling a termination function of model solving according to the stop solving semaphore and releasing the memory, completing the closed-loop simulation.

2. The emulation scheduling method of claim 1, wherein, Before the step of constructing the Simulink mathematical model and generating the model file, the method further comprises: defining, constructing and / or packaging a hardware driver file based on a VxWorks kernel program; establishing communication between a driver module and a simulation board card.

3. The emulation scheduling method of claim 1, wherein, The RTW file contains description of the Simulink mathematical model, including data type, data input, data output and internal logic.

4. A simulation dispatch system characterized by, The method comprises the following steps: a model building module for building a Simulink mathematical model and generating an initial model file; an RTW file generating module for converting the initial model file into an RTW file; a conversion module for calling a target language compiler to convert the RTW file into a to-be-called model file; a code linking module for calling a make tool to automatically generate code and link the to-be-called model file to generate an execution model file; the code linking module comprises a detection module for calling the make tool to automatically generate code and link the to-be-called model file; a priority design module for setting the priority of the Simulink mathematical model solving task; an initialization module for initializing the memory space, sampling step, signal quantity and solving running parameters of the Simulink mathematical model; and a solving task creating module for creating the solving task of the Simulink mathematical model, controlling the solving process through an auxiliary clock, finally generating the execution model file, ending the solving task and deleting the task and releasing the memory; the process of creating the solving task of the Simulink mathematical model and controlling the solving process through the auxiliary clock comprises the following steps: creating the solving task of the Simulink mathematical model; judging the type of the solving task; if it is single-task solving, detecting the running state of the Simulink mathematical model, calling the to-be-called model file to calculate the Simulink mathematical model according to the running state and releasing the signal quantity of the single-task solving; if it is multi-task solving, decomposing the solving task of the Simulink mathematical model into multiple sub-task solving and detecting each sub-task solving, calling the to-be-called model file to calculate the Simulink mathematical model according to the running state of each sub-task solving and releasing the signal quantity of each sub-task solving; and a simulation module for performing closed-loop simulation in a Vxworks system according to the execution model file, the simulation module comprising: calling an entry function in the execution model file and initializing an interrupt function of the auxiliary clock; solving the execution model file through a clock function of the auxiliary clock and detecting whether the sampling time point of the sub-task is reached; if the detection result is that the sampling time point of the sub-task is not reached, repeating the detection step; if the detection result is that the sampling time point of the sub-task is reached, releasing the signal quantity of the sampling time point; judging the type of the signal quantity of the sampling time point; if it is an interrupt solving signal quantity, pausing the solving of the execution model file according to the interrupt solving signal quantity through the interrupt function of the auxiliary clock; if it is a stop solving signal quantity, calling a termination function of the model solving according to the stop solving signal quantity and releasing the memory, thus completing the closed-loop simulation.

5. The simulation dispatch system of claim 4, wherein, The model building module further comprises defining, building and / or packaging hardware driver files based on VxWorks kernel program before building the Simulink mathematical model and generating the initial model file; and establishing communication between the driver module and the simulation board.

6. A computer-readable storage medium, characterized in that, The program file is stored and executed to implement the simulation scheduling method according to any one of claims 1-3.

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