Pulse neural network chip architecture, chip and system

Abstract

The application discloses a pulse neural network chip architecture, a chip and a system, wherein the pulse neural network chip architecture comprises a threshold-crossing data converter, an event pre-detector, a decision determinator and at least two layers of pulse neural networks; the threshold-crossing data converter is used for encoding input analog signals in a time domain, and outputs a first pulse signal of an analog signal crossing each voltage threshold and a second pulse signal of an analog signal crossing each voltage threshold direction; the event pre-detector is used for determining the start time and the end time of an event according to the first pulse signal and the second pulse signal; wherein the layers of the pulse neural network are fully connected, the first layer of neurons is driven by the two pulse output signals of the threshold-crossing data converter, the neurons of other layers are driven by the output pulses of the previous layer, and the decision determinator outputs an inference result according to the output pulse signal of the last layer of neurons. The application can be free from clock synchronization, reduce power consumption and realize ultimate event driving.

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