Pixel circuit, driving method, display panel and display device

Abstract

The pixel circuit, the driving method, the display panel and the display device provided by the embodiments of the present disclosure comprise a light emitting device, a driving transistor, a first control circuit, a second control circuit, an initialization circuit, a data writing circuit and a light emitting control circuit. Through mutual cooperation of the first control circuit, the second control circuit, the initialization circuit, the data writing circuit and the light emitting control circuit, the threshold voltage of the driving transistor can be compensated, the driving current for driving the light emitting device to emit light is independent of the threshold voltage of the driving transistor, the influence of threshold voltage drift of the driving transistor on the light emitting of the light emitting device can be avoided, and the light emitting stability is further improved and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a driving method, a display panel and a display device. BACKGROUND

[0002] An organic light emitting diode (OLED) display is one of the hotspots in the field of flat panel display research at present. Compared with a liquid crystal display (LCD), the OLED display has the advantages of low energy consumption, low production cost, self-luminous, wide viewing angle and fast response speed. The OLED display device has a light emitting device and a pixel circuit. Generally, the pixel circuit is used to drive the light emitting device to emit light in the OLED display device. The pixel circuit for controlling the light emitting device to emit light is the core technical content of the OLED display device. SUMMARY

[0003] The pixel circuit provided by the embodiments of the present disclosure comprises:

[0004] a light emitting device;

[0005] a driving transistor, coupled with the light emitting device, configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0006] a first control circuit, configured to stabilize a voltage of a gate of the driving transistor in response to a signal of a first scan signal terminal, and adjust the voltage of the gate of the driving transistor according to a signal of a first node;

[0007] a second control circuit, configured to turn on a first pole of the driving transistor and the gate of the driving transistor in response to a signal of a second scan signal terminal, and turn on the first node and a second pole of the driving transistor in response to a signal of a third scan signal terminal;

[0008] an initialization circuit, configured to provide a signal of an initialization signal terminal to the light emitting device in response to a signal of a fourth scan signal terminal, and provide the signal of the initialization signal terminal to the first node in response to a signal of a fifth scan signal terminal;

[0009] a data writing circuit, configured to provide a data voltage signal of a data signal terminal to the first node in response to a signal of a sixth scan signal terminal;

[0010] a light emitting control circuit, configured to turn on the first pole of the driving transistor and the first power supply terminal in response to a signal of a light emitting control signal terminal, so that the driving current generated by the driving transistor is provided to the light emitting device to drive the light emitting device to emit light.

[0011] In some possible implementation manners, the first control circuit comprises a first sub-circuit, a second sub-circuit and a third sub-circuit;

[0012] The first sub-circuit is configured to turn on the gate of the driving transistor and the third sub-circuit in response to the signal of the first scan signal terminal;

[0013] The second sub-circuit is configured to keep the voltage difference between the first node and the gate of the driving transistor stable;

[0014] The third sub-circuit is configured to keep the voltage difference between the first power supply terminal and the gate of the driving transistor stable when the gate of the driving transistor is turned on by the first sub-circuit.

[0015] In some possible implementation manners, the first sub-circuit comprises a first transistor, the gate of the first transistor is coupled with the first scan signal terminal, the first pole of the first transistor is coupled with the third sub-circuit, and the second pole of the first transistor is coupled with the gate of the driving transistor.

[0016] In some possible implementation manners, the second sub-circuit comprises a first capacitor, the first electrode of the first capacitor is coupled with the gate of the driving transistor, and the second electrode of the first capacitor is coupled with the first node.

[0017] In some possible implementation manners, the third sub-circuit comprises a second capacitor, the first electrode of the second capacitor is coupled with the first power supply terminal, and the second electrode of the second capacitor is coupled with the first sub-circuit.

[0018] In some possible implementation manners, the second control circuit comprises a second transistor and a third transistor;

[0019] The gate of the second transistor is coupled with the second scan signal terminal, the first pole of the second transistor is coupled with the first pole of the driving transistor, and the second pole of the second transistor is coupled with the gate of the driving transistor;

[0020] The gate of the third transistor is coupled with the third scan signal terminal, the first pole of the third transistor is coupled with the second pole of the driving transistor, and the second pole of the third transistor is coupled with the first node.

[0021] In some possible implementation manners, the initialization circuit comprises a fourth transistor and a fifth transistor;

[0022] A gate of the fourth transistor is coupled with the fourth scan signal terminal, a first electrode of the fourth transistor is coupled with the light emitting device, and a second electrode of the fourth transistor is coupled with the initialization signal terminal.

[0023] A gate of the fifth transistor is coupled with the fifth scan signal terminal, a first electrode of the fifth transistor is coupled with the first node, and a second electrode of the fifth transistor is coupled with the initialization signal terminal.

[0024] In some possible implementation manners, the data writing circuit includes a sixth transistor.

[0025] A gate of the sixth transistor is coupled with the sixth scan signal terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the data signal terminal.

[0026] In some possible implementation manners, the light emitting control circuit includes a seventh transistor.

[0027] A gate of the seventh transistor is coupled with the light emitting control signal terminal, a first electrode of the seventh transistor is coupled with the first electrode of the driving transistor, and a second electrode of the seventh transistor is coupled with the first power supply terminal.

[0028] In some possible implementation manners, the first scan signal terminal and the fourth scan signal terminal are the same signal terminal.

[0029] The display panel provided by the embodiments of the present disclosure includes the pixel circuit.

[0030] The display device provided by the embodiments of the present disclosure includes the display panel.

[0031] The driving method for the pixel circuit provided by the embodiments of the present disclosure includes an initialization stage, a threshold voltage compensation stage, a data writing stage, and a light emitting stage.

[0032] In the initialization stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal; the second control circuit turns on the first electrode of the driving transistor and the gate of the driving transistor in response to the signal of the second scan signal terminal; the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal, and provides the signal of the initialization signal terminal to the first node in response to the signal of the fifth scan signal terminal; and the light emitting control circuit turns on the first power supply terminal and the first electrode of the driving transistor in response to the signal of the light emitting control signal terminal.

[0033] In the threshold voltage compensation stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal; the second control circuit turns on the first electrode of the driving transistor and the gate of the driving transistor in response to the signal of the second scan signal terminal; the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal; and provides the signal of the initialization signal terminal to the first node in response to the signal of the fifth scan signal terminal;

[0034] In the data writing stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal, and adjusts the voltage of the gate of the driving transistor according to the signal of the first node; the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal; and the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the sixth scan signal terminal;

[0035] In the light emitting stage, the second control circuit turns on the first node and the second electrode of the driving transistor in response to the signal of the third scan signal terminal; and the light emitting control circuit turns on the first electrode of the driving transistor and the first power supply terminal in response to the signal of the light emitting control signal terminal, so that the driving current generated by the driving transistor is provided to the light emitting device to drive the light emitting device to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 Some structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0037] Figure 2 Some structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0038] Figure 3 Some structural schematic diagrams of the pixel circuit provided by the embodiments of the present disclosure;

[0039] Figure 4 Flow chart of the driving method of the pixel circuit provided by the embodiments of the present disclosure;

[0040] Figure 5 Some signal timing diagrams provided by the embodiments of the present disclosure;

[0041] Figure 6 Some structural schematic diagrams of the pixel driving circuit provided by the embodiments of the present disclosure;

[0042] Figure 7 Some signal timing diagrams provided by the embodiments of the present disclosure; Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0045] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0046] The display device provided in this disclosure includes: a display panel, wherein the display area of ​​the display panel includes a plurality of pixel units arranged in an array, and each pixel unit includes a plurality of sub-pixels. Exemplarily, each pixel unit includes a plurality of sub-pixels. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, so that red, green, blue, and white can be mixed to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0047] In the embodiments of the present disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light emitting device to control the light emitting device to emit light, so that the display panel realizes the function of picture display. Due to process and device aging, etc., the threshold voltage Vth of the driving transistor driving the light emitting device to emit light is not uniform, which causes the current flowing through different light emitting devices to change, resulting in uneven display brightness, thereby affecting the display effect of the entire image.

[0048] The embodiments of the present disclosure provide a pixel circuit, as shown in the accompanying drawings, comprising: a light emitting device L, a driving transistor M0, a first control circuit 10, a second control circuit 20, an initialization circuit 30, a data writing circuit 40, and a light emitting control circuit 50; wherein the driving transistor M0 is coupled with the light emitting device L and is configured to generate a driving current for driving the light emitting device L to emit light according to a data voltage signal; Figure 1

[0049] The first control circuit 10 is configured to stabilize the voltage at the gate of the driving transistor M0 in response to the signal of the first scan signal end SS1, and adjust the voltage at the gate of the driving transistor M0 according to the signal of the first node N1;

[0050] The second control circuit 20 is configured to turn on the first pole of the driving transistor M0 and the gate of the driving transistor M0 in response to the signal of the second scan signal end SS2, and turn on the first node N1 and the second pole of the driving transistor M0 in response to the signal of the third scan signal end SS3;

[0051] The initialization circuit 30 is configured to provide the signal of the initialization signal end Vini to the light emitting device L in response to the signal of the fourth scan signal end SS4, and provide the signal of the initialization signal end Vini to the first node N1 in response to the signal of the fifth scan signal end SS5;

[0052] The data writing circuit 40 is configured to provide the data voltage signal of the data signal end DA to the first node N1 in response to the signal of the sixth scan signal end SS6;

[0053] The light emitting control circuit 50 is configured to turn on the first pole of the driving transistor M0 and the first power supply end VDD in response to the signal of the light emitting control signal end EM, so that the driving current generated by the driving transistor M0 is provided to the light emitting device L to drive the light emitting device L to emit light.

[0054] ​In the embodiments of the present disclosure, through the cooperation of the first control circuit, the second control circuit, the initialization circuit, the data writing circuit and the light emitting control circuit, the threshold voltage of the driving transistor can be compensated, the driving current for driving the light emitting device to emit light is independent of the threshold voltage of the driving transistor, the influence of the threshold voltage drift of the driving transistor on the light emitting of the light emitting device can be avoided, and the light emitting stability is further improved and the display effect of the display panel is improved.

[0055] In the embodiments of the present disclosure, as shown in Figure 1 The driving transistor M0 can be an N-type transistor; the first electrode of the driving transistor M0 can be the drain electrode thereof, the second electrode of the driving transistor M0 can be the source electrode thereof, and when the driving transistor M0 is in a saturation state, the current flows from the drain electrode to the source electrode of the driving transistor M0. Of course, the driving transistor M0 can also be a P-type transistor, which is not limited herein.

[0056] In the embodiments of the present disclosure, as shown in Figure 1 The second electrode of the driving transistor M0 is coupled with the anode of the light emitting device L, the initialization circuit 30 is coupled with the anode of the light emitting device L, and the cathode of the light emitting device L is coupled with the second power supply end VSS. Illustratively, the light emitting device L can include at least one of a Micro Light Emitting Diode (Micro LED), an Organic Light Emitting Diode (OLED) and a Quantum Dot Light Emitting Diode (QLED). Illustratively, the light emitting device L can include an anode, a light emitting layer and a cathode which are stacked. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer and the like. In actual application, the specific structure of the light emitting device L can be designed and determined according to the actual application environment, which is not limited herein.

[0057] In the embodiments of the present disclosure, as shown in Figure 2 The first control circuit 10 includes a first sub-circuit 101, a second sub-circuit 102 and a third sub-circuit 103; the first sub-circuit 101 is configured to turn on the gate of the driving transistor M0 and the third sub-circuit 103 in response to the signal of the first scan signal end SS1; the second sub-circuit 102 is configured to keep the voltage difference between the first node N1 and the gate of the driving transistor M0 stable; and the third sub-circuit 103 is configured to keep the voltage difference between the first power supply end VDD and the gate of the driving transistor M0 stable when the gate of the driving transistor M0 is turned on through the first sub-circuit 101.

[0058] In the embodiments of the present disclosure, asFigure 3 As shown in FIG. 1, the first sub-circuit 101 comprises a first transistor M1; wherein a gate of the first transistor M1 is coupled with a first scan signal terminal SS1, a first pole of the first transistor M1 is coupled with the third sub-circuit 103, and a second pole of the first transistor M1 is coupled with a gate of the driving transistor M0.

[0059] Exemplarily, the first transistor M1 can be turned on under control of an effective level of a first scan signal transmitted by the first scan signal terminal SS1, and can be turned off under control of an ineffective level of the first scan signal. Exemplarily, the first transistor M1 is set as an N-type transistor, and the effective level of the first scan signal is high level and the ineffective level of the first scan signal is low level. Alternatively, the first transistor M1 is set as a P-type transistor, and the effective level of the first scan signal is low level and the ineffective level of the first scan signal is high level.

[0060] In the embodiment of the present disclosure, as shown in FIG. 1, Figure 3 As shown in FIG. 1, the second sub-circuit 102 comprises a first capacitor C1; wherein a first electrode of the first capacitor C1 is coupled with the gate of the driving transistor M0, and a second electrode of the first capacitor C1 is coupled with the first node N1.

[0061] In the embodiment of the present disclosure, as shown in FIG. 1, Figure 3 As shown in FIG. 1, the third sub-circuit 103 comprises a second capacitor C2; wherein a first electrode of the second capacitor C2 is coupled with a first power supply terminal VDD, and a second electrode of the second capacitor C2 is coupled with the first sub-circuit 101.

[0062] In the embodiment of the present disclosure, as shown in FIG. 1, Figure 3 As shown in FIG. 1, the second control circuit 20 comprises a second transistor M2 and a third transistor M3; wherein a gate of the second transistor M2 is coupled with a second scan signal terminal SS2, a first pole of the second transistor M2 is coupled with the first pole of the driving transistor M0, and a second pole of the second transistor M2 is coupled with the gate of the driving transistor M0; a gate of the third transistor M3 is coupled with a third scan signal terminal SS3, a first pole of the third transistor M3 is coupled with the second pole of the driving transistor M0, and a second pole of the third transistor M3 is coupled with the first node N1.

[0063] Exemplarily, the second transistor M2 can be turned on under control of an effective level of a second scan signal transmitted by the second scan signal terminal SS2, and can be turned off under control of an ineffective level of the second scan signal. Exemplarily, the second transistor M2 is set as an N-type transistor, and the effective level of the second scan signal is high level and the ineffective level of the second scan signal is low level. Alternatively, the second transistor M2 is set as a P-type transistor, and the effective level of the second scan signal is low level and the ineffective level of the second scan signal is high level.

[0064] Exemplarily, the third transistor M3 can be turned on under the control of an effective level of the third scan signal transmitted by the third scan signal terminal SS3, and can be turned off under the control of an ineffective level of the third scan signal. Exemplarily, the third transistor M3 is configured as an N-type transistor, and the effective level of the third scan signal is a high level, and the ineffective level of the third scan signal is a low level. Alternatively, the third transistor M3 is configured as a P-type transistor, and the effective level of the third scan signal is a low level, and the ineffective level of the third scan signal is a high level.

[0065] In the embodiment of the present disclosure, as shown in Figure 3 The initialization circuit 30 includes a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is coupled with the fourth scan signal terminal SS4, the first pole of the fourth transistor M4 is coupled with the light emitting device L, and the second pole of the fourth transistor M4 is coupled with the initialization signal terminal Vini. The gate of the fifth transistor M5 is coupled with the fifth scan signal terminal SS5, the first pole of the fifth transistor M5 is coupled with the first node N1, and the second pole of the fifth transistor M5 is coupled with the initialization signal terminal Vini.

[0066] Exemplarily, the fourth transistor M4 can be turned on under the control of an effective level of the fourth scan signal transmitted by the fourth scan signal terminal SS4, and can be turned off under the control of an ineffective level of the fourth scan signal. Exemplarily, the fourth transistor M4 is configured as an N-type transistor, and the effective level of the fourth scan signal is a high level, and the ineffective level of the fourth scan signal is a low level. Alternatively, the fourth transistor M4 is configured as a P-type transistor, and the effective level of the fourth scan signal is a low level, and the ineffective level of the fourth scan signal is a high level.

[0067] Exemplarily, the fifth transistor M5 can be turned on under the control of an effective level of the fifth scan signal transmitted by the fifth scan signal terminal SS5, and can be turned off under the control of an ineffective level of the fifth scan signal. Exemplarily, the fifth transistor M5 is configured as an N-type transistor, and the effective level of the fifth scan signal is a high level, and the ineffective level of the fifth scan signal is a low level. Alternatively, the fifth transistor M5 is configured as a P-type transistor, and the effective level of the fifth scan signal is a low level, and the ineffective level of the fifth scan signal is a high level.

[0068] In the embodiment of the present disclosure, as shown in Figure 3 The data writing circuit 40 includes a sixth transistor M6. The gate of the sixth transistor M6 is coupled with the sixth scan signal terminal SS6, the first pole of the sixth transistor M6 is coupled with the first node N1, and the second pole of the sixth transistor M6 is coupled with the data signal terminal DA.

[0069] Exemplarily, the sixth transistor M6 can be turned on under the control of an active level of the sixth scan signal transmitted by the sixth scan signal end SS6, and can be turned off under the control of an inactive level of the sixth scan signal. Exemplarily, the sixth transistor M6 is set as an N-type transistor, and the active level of the sixth scan signal is a high level and the inactive level of the sixth scan signal is a low level. Alternatively, the sixth transistor M6 is set as a P-type transistor, and the active level of the sixth scan signal is a low level and the inactive level of the sixth scan signal is a high level.

[0070] In the embodiments of the present disclosure, as shown in Figure 3 The light emitting control circuit 50 includes a seventh transistor M7, wherein a gate of the seventh transistor M7 is coupled with the light emitting control signal end EM, a first pole of the seventh transistor M7 is coupled with the first pole of the driving transistor M0, and a second pole of the seventh transistor M7 is coupled with the first power supply end VDD.

[0071] Exemplarily, the seventh transistor M7 can be turned on under the control of an active level of the light emitting control signal transmitted by the light emitting control signal end EM, and can be turned off under the control of an inactive level of the light emitting control signal. Exemplarily, the seventh transistor M7 is set as an N-type transistor, and the active level of the light emitting control signal is a high level and the inactive level of the light emitting control signal is a low level. Alternatively, the seventh transistor M7 is set as a P-type transistor, and the active level of the light emitting control signal is a low level and the inactive level of the light emitting control signal is a high level.

[0072] Exemplarily, the first pole of the above-mentioned transistor can be its source, and the second pole can be its drain. Alternatively, the first pole is its drain, and the second pole is its source. This is not limited herein.

[0073] Generally, the Low Temperature Poly-Silicon (LTPS) material is used as the active layer of the transistor, which has high mobility and can be made thinner and smaller, and has lower power consumption, etc. In the specific implementation, the material of the active layer of the above-mentioned at least one transistor can be set as the low temperature poly-silicon material. In this way, the above-mentioned transistor can be set as the LTPS transistor, so that the pixel circuit has high mobility and can be made thinner and smaller, and has lower power consumption, etc.

[0074] Generally, the leakage current of the transistor using metal oxide semiconductor material as the active layer is small, and therefore, in order to reduce the leakage current, the material of the active layer of the at least one transistor can also include metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor material, which is not limited herein. In this way, the transistor can be configured as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0075] For example, all the transistors can be configured as LTPS transistors. Alternatively, all the transistors can be configured as oxide transistors. Alternatively, part of the transistors can be configured as oxide transistors, and the remaining transistors can be configured as LTPS transistors.

[0076] In the embodiment of the present disclosure, the first power supply end VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally positive. In addition, the second power supply end VSS can load a constant second power supply voltage vss, and the second power supply voltage vss can generally be a ground voltage or a negative value. In actual application, the specific values of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, which is not limited herein.

[0077] In the embodiment of the present disclosure, as shown in Figure 3 , the pixel circuit further includes a second node N2, a third node N3 and a fourth node N4; the second node N2 is coupled with the gate of the driving transistor M0, the third node N3 is coupled with the first electrode of the driving transistor M0, and the fourth node N4 is coupled with the second electrode of the driving transistor M0.

[0078] The above is only an example to illustrate the specific structure of each circuit in the pixel circuit provided by the embodiment of the present disclosure. In the specific implementation, the specific structure of the above circuit is not limited to the above structure provided by the embodiment of the present disclosure, but can also be other structures known by those skilled in the art, which are within the protection scope of the present disclosure, and the specific structure is not limited herein.

[0079] In the embodiment of the present disclosure, as shown in Figure 4 , the driving method of the pixel circuit provided by the embodiment of the present disclosure can include the following steps:

[0080] S100, in the initialization stage, the first control circuit responds to the signal of the first scan signal end to stabilize the voltage of the gate of the driving transistor; the second control circuit responds to the signal of the second scan signal end to turn on the first electrode of the driving transistor and the gate of the driving transistor; the initialization circuit responds to the signal of the fourth scan signal end to provide the signal of the initialization signal end to the light emitting device; and responds to the signal of the fifth scan signal end to provide the signal of the initialization signal end to the first node; the light emitting control circuit responds to the signal of the light emitting control signal end to turn on the first power supply end and the first electrode of the driving transistor;

[0081] S200, in the threshold voltage compensation stage, the first control circuit responds to the signal of the first scan signal end to stabilize the voltage of the gate of the driving transistor; the second control circuit responds to the signal of the second scan signal end to turn on the first electrode of the driving transistor and the gate of the driving transistor; the initialization circuit responds to the signal of the fourth scan signal end to provide the signal of the initialization signal end to the light emitting device; and responds to the signal of the fifth scan signal end to provide the signal of the initialization signal end to the first node;

[0082] S300, in the data writing stage, the first control circuit responds to the signal of the first scan signal end to stabilize the voltage of the gate of the driving transistor, and adjusts the voltage of the gate of the driving transistor according to the signal of the first node; the initialization circuit responds to the signal of the fourth scan signal end to provide the signal of the initialization signal end to the light emitting device; the data writing circuit responds to the signal of the sixth scan signal end to provide the data voltage signal of the data signal end to the first node;

[0083] S400, in the light emitting stage, the second control circuit responds to the signal of the third scan signal end to turn on the first node and the second electrode of the driving transistor; the light emitting control circuit responds to the signal of the light emitting control signal end to turn on the first power supply end and the first electrode of the driving transistor, so that the driving current generated by the driving transistor is provided to the light emitting device to drive the light emitting device to emit light.

[0084] The working process of the pixel circuit provided in the embodiment of the present disclosure will be described below taking the pixel circuit shown in Figure 3 as an example in combination with the signal timing diagram shown in Figure 5 .

[0085] In the embodiment of the present disclosure, as Figure 5As shown, em represents the light emitting control signal of the light emitting control signal terminal EM, ss1 represents the first scanning signal of the first scanning signal terminal SS1, ss2 represents the second scanning signal of the second scanning signal terminal SS2, ss3 represents the third scanning signal of the third scanning signal terminal SS3, ss4 represents the fourth scanning signal of the fourth scanning signal terminal SS4, ss5 represents the fifth scanning signal of the fifth scanning signal terminal SS5, ss6 represents the sixth scanning signal of the sixth scanning signal terminal SS6, and da represents the signal of the data signal terminal DA.

[0086] In addition, the initialization stage P1, the threshold compensation stage P2, the data writing stage P3 and the light emitting stage P4 in one display frame are selected.

[0087] In the initialization stage P1, the first transistor M1 is turned on under the control of the high level of the first scanning signal ss1, the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2, the third transistor M3 is turned off under the control of the low level of the third scanning signal ss3, the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4, the fifth transistor M5 is turned on under the control of the high level of the fifth scanning signal ss5, the sixth transistor M6 is turned off under the control of the low level of the sixth scanning signal ss6, and the seventh transistor M7 is turned on under the control of the high level of the light emitting control signal em. The turned-on fourth transistor M4 inputs the initialization signal of the initial voltage signal terminal Vini to the anode of the light emitting device L, and initializes the anode of the light emitting device L. Then, VN4=Vvini, wherein VN4 represents the voltage of the fourth node N4, and Vvini represents the voltage of the initialization signal output by the initial voltage signal terminal Vini. The turned-on fifth transistor M5 inputs the initialization signal of the initial voltage signal terminal Vini to the first node N1, and then VN1=Vvini, wherein VN1 represents the voltage of the first node N1. The turned-on seventh transistor M7 inputs the signal of the first power supply terminal VDD to the third node N3, and then VN3=vdd, wherein VN3 represents the voltage of the third node N3, and vdd represents the voltage of the first power supply voltage signal of the first power supply terminal VDD, so as to initialize the first electrode of the second transistor M2. The turned-on second transistor M2 inputs the signal of the third node N3 to the second node N2, and then VN2=vdd, wherein VN2 represents the voltage of the second node N2, so as to initialize the second electrode of the second capacitor C2. In addition, the first capacitor C1 and the second capacitor C2 stabilize the voltage difference between their respective two electrodes.

[0088] In the threshold compensation stage P2, the first transistor Ml is turned on under the control of the high level of the first scanning signal ss 1, the second transistor M2 is turned on under the control of the high level of the second scanning signal ss2, the third transistor M3 is turned off under the control of the low level of the third scanning signal ss3, the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4, the fifth transistor M5 is turned on under the control of the high level of the fifth scanning signal ss5, the sixth transistor M6 is turned off under the control of the low level of the sixth scanning signal ss6, and the seventh transistor M7 is turned off under the control of the low level of the light-emitting control signal em. The turned-on fourth transistor M4 inputs the initialization signal of the initial voltage signal terminal Vini to the anode of the light-emitting device L, and initializes the anode of the light-emitting device L. Thus, VN4 = Vvini. The turned-on fifth transistor M5 inputs the initialization signal of the initial voltage signal terminal Vini to the first node Nl, and thus VNl = Vvini. The turned-on second transistor M2 connects the gate of the driving transistor M0 with the first pole of the driving transistor M0, and makes the driving transistor M0 form a diode connection mode, so as to perform threshold voltage Vth compensation. The voltage VN2 of the second node N2 changes to VN2 = Vvini + Vth, and Vth represents the threshold voltage of the driving transistor M0. Moreover, the first capacitor Cl and the second capacitor C2 stabilize the voltage difference between the two electrodes thereof. Moreover, the turned-on first transistor Ml connects the second node N2 with the second electrode of the second capacitor C2, so as to make the voltage of the second electrode of the second capacitor C2 be VN2.

[0089] In the data writing stage P3, the first transistor Ml is turned on under the control of the high level of the first scanning signal ss 1, the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2, the third transistor M3 is turned off under the control of the low level of the third scanning signal ss3, the fourth transistor M4 is turned on under the control of the high level of the fourth scanning signal ss4, the fifth transistor M5 is turned off under the control of the low level of the fifth scanning signal ss5, the sixth transistor M6 is turned on under the control of the high level of the sixth scanning signal ss6, and the seventh transistor M7 is turned off under the control of the low level of the light emitting control signal em. The turned-on fourth transistor M4 inputs the initialization signal of the initial voltage signal terminal Vini to the anode of the light emitting device L, and the anode of the light emitting device L is initialized. Thus, VN4=Vvini. The turned-on sixth transistor M6 inputs the data voltage signal of the data signal terminal DA to the first node Nl, and thus the voltage VNl of the first node Nl changes by Vda-Vvini. The turned-on first transistor Ml connects the second node N2 with the second electrode of the second capacitor C2, and thus the voltage VN2 of the second node changes to VN2=Vvini+Vth+(Vda-Vvini)[c1 / (c1+c2)] by the coupling effect of the first capacitor and the second capacitor. Here, c1 represents the capacitance of the first capacitor Cl, and c2 represents the capacitance of the second capacitor C2.

[0090] In the light emitting stage P4, the first transistor Ml is turned off under the control of the low level of the first scanning signal ss 1, the second transistor M2 is turned off under the control of the low level of the second scanning signal ss2, the third transistor M3 is turned on under the control of the high level of the third scanning signal ss3, the fourth transistor M4 is turned off under the control of the low level of the fourth scanning signal ss4, the fifth transistor M5 is turned off under the control of the low level of the fifth scanning signal ss5, the sixth transistor M6 is turned off under the control of the low level of the sixth scanning signal ss6, and the seventh transistor M7 is turned on under the control of the high level of the light emitting control signal em. The turned-on third transistor M3 connects the fourth node N4 with the first node Nl. Thus, the voltage VN3 of the third node N3 is vdd, the voltage of the fourth node is VN4, and the voltage VNl of the first node Nl changes by VN4-Vda. The voltage VNl of the first node Nl is coupled to the gate of the driving transistor M0 (i.e. the second node N2) through the first capacitor Cl, and thus,

[0091] VN2=Vvini+Vth+(Vda-Vvini)[c1 / (c1+c2)]+VN4-Vda

[0092] = VN4+Vth-[c2 / (c1+c2)]Vda-[c1 / (c1+c2)]Vvini.

[0093] The seventh transistor M7 is turned on to connect the first electrode of the driving transistor M0 to the first power supply terminal VDD and connect the second electrode of the driving transistor M0 to the anode of the light emitting device L, so that the driving transistor M0 generates a driving current I DS to control the light emitting device L to emit light. Wherein, I DS represents the driving current for driving the light emitting device L to emit light, and, wherein, Vgs represents the voltage difference between the gate and the source of the driving transistor M0, l represents the length of the channel of the driving transistor M0, W represents the width of the channel of the driving transistor M0, C ox represents the unit area capacitance of the gate insulating layer of the driving transistor M0, and μ represents the mobility of the driving transistor M0.

[0094] The embodiment of the present disclosure provides another structural schematic diagram of the pixel driving circuit, as shown in Figure 6 , which is transformed for the implementation of the above embodiment. Only the differences between the present embodiment and the above embodiment are described below, and the substantially same parts are not described herein.

[0095] In the embodiment of the present disclosure, the first scan signal terminal SS1 and the fourth scan signal terminal SS4 are the same signal terminal. For example, as shown in Figure 6 , the gate of the fourth transistor M4 is coupled to the first scan signal terminal SS1.

[0096] Figure 6 The signal timing diagram corresponding to the pixel circuit shown in Figure 7 may be as shown. The driving process of the present embodiment is similar to that of the foregoing pixel circuit, and therefore the driving process of the present embodiment can be implemented by referring to the driving process of the foregoing pixel circuit, and the repeated parts are not described herein.

[0097] The embodiment of the present disclosure also provides a display panel, which includes a plurality of pixel units arranged in an array in a display area of the display panel, and each pixel unit includes a plurality of sub-pixels. Each sub-pixel includes the pixel circuit described above. The principle of solving the problem of the display panel is similar to that of the foregoing pixel circuit, and therefore the implementation of the display panel can be implemented by referring to the implementation of the foregoing pixel circuit, and the repeated parts are not described herein.

[0098] The embodiment of the present disclosure also provides a display device, which includes the display panel described above. The principle of solving the problem of the display device is similar to that of the foregoing pixel circuit, and therefore the implementation of the display device can be implemented by referring to the implementation of the foregoing pixel circuit, and the repeated parts are not described herein.

[0099] In specific implementation, in the embodiments of the present disclosure, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein, nor should they be construed as a limitation on the present disclosure.

[0100] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who have the basic inventive concept can make further changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0101] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A pixel circuit, characterized by comprising: The application relates to a light emitting device, a driving transistor, a first control circuit, a second control circuit, an initialization circuit, a data writing circuit and a light emitting control circuit. The light emitting device comprises: a light emitting device; a driving transistor coupled with the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal; a first control circuit configured to stabilize a voltage of a gate of the driving transistor in response to a signal of a first scan signal terminal and adjust the voltage of the gate of the driving transistor according to a signal of a first node; a second control circuit configured to turn on a first electrode of the driving transistor and the gate of the driving transistor in response to a signal of a second scan signal terminal and turn on the first node and a second electrode of the driving transistor in response to a signal of a third scan signal terminal; an initialization circuit configured to provide a signal of an initialization signal terminal to the light emitting device in response to a signal of a fourth scan signal terminal and provide the signal of the initialization signal terminal to the first node in response to a signal of a fifth scan signal terminal; a data writing circuit configured to provide a data voltage signal of a data signal terminal to the first node in response to a signal of a sixth scan signal terminal; a light emitting control circuit configured to turn on a first power supply terminal and the first electrode of the driving transistor in response to a signal of a light emitting control signal terminal, so that the driving current generated by the driving transistor is provided to the light emitting device to drive the light emitting device to emit light. The first control circuit comprises a first sub-circuit, a second sub-circuit and a third sub-circuit. The first sub-circuit is configured to turn on the gate of the driving transistor and the third sub-circuit in response to the signal of the first scan signal terminal. The second sub-circuit is configured to keep a voltage difference between the first node and the gate of the driving transistor stable. The third sub-circuit is configured to keep a voltage difference between the first power supply terminal and the gate of the driving transistor stable when the gate of the driving transistor is turned on through the first sub-circuit. The first sub-circuit comprises a first transistor.

2. The pixel circuit of claim 1, wherein, The gate of the first transistor is coupled with the first scan signal terminal, the first electrode of the first transistor is coupled with the third sub-circuit, and the second electrode of the first transistor is coupled with the gate of the driving transistor. The second sub-circuit comprises a first capacitor.

3. The pixel circuit of claim 1, wherein, The first electrode of the first capacitor is coupled with the gate of the driving transistor, and the second electrode of the first capacitor is coupled with the first node. The third sub-circuit comprises a second capacitor.

4. The pixel circuit of claim 1, wherein, The first electrode of the second capacitor is coupled with the first power supply terminal, and the second electrode of the second capacitor is coupled with the first sub-circuit. The second control circuit comprises a second transistor and a third transistor.

5. The pixel circuit according to any one of claims 1 to 4, wherein The gate of the second transistor is coupled with the second scan signal terminal, the first electrode of the second transistor is coupled with the first electrode of the driving transistor, and the second electrode of the second transistor is coupled with the gate of the driving transistor. The gate of the third transistor is coupled with the third scan signal terminal, the first electrode of the third transistor is coupled with the second electrode of the driving transistor, and the second electrode of the third transistor is coupled with the first node. The initialization circuit comprises a fourth transistor and a fifth transistor.

6. The pixel circuit of any one of claims 1-4, wherein, ​ A gate of the fourth transistor is coupled with the fourth scan signal terminal, a first electrode of the fourth transistor is coupled with the light emitting device, and a second electrode of the fourth transistor is coupled with the initialization signal terminal; A gate of the fifth transistor is coupled with the fifth scan signal terminal, a first electrode of the fifth transistor is coupled with the first node, and a second electrode of the fifth transistor is coupled with the initialization signal terminal.

7. The pixel circuit of any one of claims 1-4, wherein, The data writing circuit comprises a sixth transistor; A gate of the sixth transistor is coupled with the sixth scan signal terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the data signal terminal.

8. The pixel circuit of any one of claims 1-4, wherein, The light emitting control circuit comprises a seventh transistor; A gate of the seventh transistor is coupled with the light emitting control signal terminal, a first electrode of the seventh transistor is coupled with the first electrode of the driving transistor, and a second electrode of the seventh transistor is coupled with the first power supply terminal.

9. The pixel circuit of any one of claims 1-4, wherein, The first scan signal terminal and the fourth scan signal terminal are the same signal terminal.

10. A display panel, characterized by, The pixel circuit comprises any one of claims 1-9.

11. A display device, characterized by comprising: The display panel comprises claim 10.

12. A driving method for the pixel circuit according to any one of claims 1 to 9, characterized by, Comprises: An initialization stage, a threshold voltage compensation stage, a data writing stage, and a light emitting stage; In the initialization stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal; the second control circuit turns on the first electrode of the driving transistor and the gate of the driving transistor in response to the signal of the second scan signal terminal; and the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal; and provides the signal of the initialization signal terminal to the first node in response to the signal of the fifth scan signal terminal; and the light emitting control circuit turns on the first power supply terminal and the first electrode of the driving transistor in response to the signal of the light emitting control signal terminal; In the threshold voltage compensation stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal; the second control circuit turns on the first electrode of the driving transistor and the gate of the driving transistor in response to the signal of the second scan signal terminal; and the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal; and provides the signal of the initialization signal terminal to the first node in response to the signal of the fifth scan signal terminal; In the data writing stage, the first control circuit stabilizes the voltage of the gate of the driving transistor in response to the signal of the first scan signal terminal, and adjusts the voltage of the gate of the driving transistor according to the signal of the first node; the initialization circuit provides the signal of the initialization signal terminal to the light emitting device in response to the signal of the fourth scan signal terminal; and the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the sixth scan signal terminal; In the light emitting stage, the second control circuit turns on the first node and the second electrode of the driving transistor in response to the signal of the third scan signal terminal; the light emitting control circuit turns on the first power supply terminal and the first electrode of the driving transistor in response to the signal of the light emitting control signal terminal, so that the driving current generated by the driving transistor is provided to the light emitting device to drive the light emitting device to emit light.

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