Semiconductor structure and its formation method

Abstract

A semiconductor structure according to an embodiment of the present disclosure includes a circuit region disposed above a substrate and a sealing ring region disposed above the substrate and completely surrounding the circuit region. The circuit region includes a plurality of first fins, a plurality of second fins, a plurality of n-type epitaxial structures above the first fins, and a plurality of p-type epitaxial structures above the second fins. The sealing ring region includes a plurality of fin rings extending completely around the circuit region and a plurality of epitaxial rings disposed above the fin rings and extending parallel to the fin rings. All epitaxial rings above all fin rings in the sealing ring region are p-type epitaxial rings.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a sealing ring structure for a semiconductor device. Background Technology

[0002] In semiconductor technology, semiconductor wafers are processed through various manufacturing steps to form integrated circuits (ICs). Typically, multiple circuits or IC dies are formed on the same semiconductor wafer. The wafer is then diced to cut out the circuits formed thereon. To protect the circuits from moisture degradation, ion contamination, and the effects of the dicing process, a sealing ring is formed around each IC die. This sealing ring is formed during the fabrication of many layers containing the circuitry, including front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. The front-end process includes forming transistors, capacitors, diodes, and / or resistors on the semiconductor substrate. The back-end process includes forming metal interconnects and vias to provide wiring for the components from the front-end process.

[0003] While existing sealing ring structures and manufacturing methods are generally sufficient to meet their intended purpose, improvements are still needed. For example, there is a desire to improve the stability and reliability of the sealing rings. Summary of the Invention

[0004] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a circuit region disposed above a substrate and a sealing ring region disposed above the substrate and completely surrounding the circuit region. The circuit region includes a plurality of first fins, a plurality of second fins, a plurality of n-type epitaxial structures above the first fins, and a plurality of p-type epitaxial structures above the second fins. The sealing ring region includes a plurality of fin rings extending completely around the circuit region and a plurality of epitaxial rings disposed above the fin rings and extending parallel to the fin rings. All epitaxial rings above all fin rings in the sealing ring region are p-type epitaxial rings.

[0005] In another exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate, a circuit region above the substrate, and a sealing ring region above the substrate and completely surrounding the circuit region. The sealing ring region includes: a plurality of first fin rings and a plurality of second fin rings disposed on the substrate and completely surrounding the circuit region, and a plurality of epitaxial rings disposed above the first fin rings. Each epitaxial ring extends the entire length of the first fin rings and completely surrounds the circuit region. All epitaxial rings in the sealing ring region comprise the same material, and the second fin rings do not contain epitaxial rings.

[0006] In yet another exemplary embodiment, this disclosure relates to a method of forming a semiconductor structure. The method includes: providing a semiconductor substrate including a sealing ring region surrounding a device region; forming a plurality of fins protruding from the semiconductor substrate in the device region and forming a plurality of fin rings in the sealing ring region, wherein each fin ring completely surrounds the device region; recessing the top portions of the fins and fin rings; simultaneously growing a plurality of first epitaxial structures over the recessed fins and growing a plurality of epitaxial rings over the recessed fin rings, wherein the first epitaxial structures and epitaxial rings include a first material; subsequently forming a mask covering the entire sealing ring region and exposing a plurality of portions of the device region; etching the exposed portions of the device region to form a plurality of recesses; and growing a plurality of second epitaxial structures in the recesses, wherein the second epitaxial structures include a second material different from the first material. Attached Figure Description

[0007] The complete disclosure is based on the following detailed description and accompanying drawings. It should be emphasized that, in accordance with the general practice of the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity.

[0008] Figure 1 This is a top plan view of a semiconductor structure including a sealing ring structure according to various embodiments of the present disclosure.

[0009] Figure 2 and Figure 3 These are various embodiments according to the present disclosure. Figure 1 Enlarged top view of regions A and B.

[0010] Figure 4 According to various embodiments of this disclosure, along Figure 1 and Figure 3 Line segment 1-1 in the middle, Figure 1 Cross-sectional view of a semiconductor structure.

[0011] Figure 5 and Figure 6 According to various embodiments of this disclosure, along Figure 1 , Figure 3 and Figure 4 Line segments 2-2 and 3-3 in the text. Figure 1 Cross-sectional view of a semiconductor structure.

[0012] Figure 7 and Figure 8 According to various embodiments of this disclosure, along Figure 4 Line segment 4-4 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0013] Figure 9 According to various embodiments of this disclosure, Figure 4 Enlarged cross-sectional view of region D.

[0014] Figure 10 To replace according to this disclosure Figures 4 to 9 The embodiment shown, along line segment 1-1, Figure 1 A cross-sectional view of a semiconductor structure.

[0015] Figure 11 According to various embodiments of this disclosure, along Figure 1 and Figure 10 Line segment 2-2 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0016] Figure 12 and Figure 13 According to various embodiments of this disclosure, along Figure 10 Line segment 4-4 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0017] Figure 14 To replace according to this disclosure Figures 4 to 9 The embodiment shown, along line segment 1-1, Figure 1 A cross-sectional view of a semiconductor structure.

[0018] Figure 15 and Figure 16 According to various embodiments of this disclosure, along Figure 14 Line segment 4-4 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0019] Figure 17 According to various embodiments of this disclosure, Figure 1 Enlarged top view of region C.

[0020] Figure 18 and Figure 19 According to various embodiments of this disclosure, along Figure 17 Line segment 5-5 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0021] Figure 20 To make Figure 1 A flowchart of a method for constructing semiconductor structures.

[0022] Figure 21 According to various embodiments of this disclosure, in Figure 20 The intermediate stage of the method shown. Figure 1 A three-dimensional view of region A of the semiconductor structure.

[0023] Figure 22 According to various embodiments of this disclosure, in Figure 20The intermediate stage of the method shown. Figure 1 A three-dimensional view of region B of the semiconductor structure.

[0024] Figure 23 , Figure 27 , Figure 31 , Figure 35 , Figure 39 , Figure 43 , Figure 47 and Figure 51 According to various embodiments of this disclosure, in Figure 20 The intermediate stage of the method shown, along Figure 21 Line segment 6-6 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0025] Figure 24 , Figure 28 , Figure 32 , Figure 36 , Figure 40 , Figure 44 , Figure 48 and Figure 52 According to various embodiments of this disclosure, in Figure 20 The intermediate stage of the method shown, along Figure 22 Line segment 2-2 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0026] Figure 25 , Figure 29 , Figure 33 , Figure 37 , Figure 41 , Figure 45 , Figure 49 and Figure 53 According to various embodiments of this disclosure, in Figure 20 The intermediate stage of the method shown, along Figure 21 Line segment 7-7, Figure 1 A cross-sectional view of a semiconductor structure.

[0027] Figure 26 , Figure 30 , Figure 34 , Figure 38 , Figure 42 , Figure 46 , Figure 50 and Figure 54 According to various embodiments of this disclosure, in Figure 20 The intermediate stage of the method shown, along Figure 22 Line segment 1-1 in the middle, Figure 1 A cross-sectional view of a semiconductor structure.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1-1, 2-2, 3-3, 4-4, 5-5, 6-6, 7-7: Line segments

[0030] 100: Semiconductor Structure

[0031] 102: Semiconductor substrate

[0032] 200: Circuit area

[0033] 220: Fins

[0034] 220a: Fins

[0035] 220b: Fins

[0036] 222: concave part

[0037] 224: concave part

[0038] 230: Isolation Structure

[0039] 240: Gate structure

[0040] 241: Dummy Gate Structure

[0041] 242: Gate dielectric layer

[0042] 243: Opening

[0043] 244: Gate electrode

[0044] 246: Gate spacer

[0045] 250a: Epitaxial structure

[0046] 250b: Epitaxial structure

[0047] 252: Silicide layer

[0048] 260: Contact Structure

[0049] 300: Sealing ring area (sealing ring)

[0050] 302: Sealing ring structure

[0051] 304: Outer corner area

[0052] 306: Inner corner area

[0053] 320: Fin-type structure (fin ring)

[0054] 320': Fin ring

[0055] 322: First semiconductor layer

[0056] 323: Second semiconductor layer

[0057] 324: concave part

[0058] 330: Isolation structure (isolation ring)

[0059] 332: Fictitious fin ring

[0060] 340: Gate-type structure (gate ring)

[0061] 340': Gate ring

[0062] 341: Dummy gate ring

[0063] 342: Gate dielectric layer

[0064] 343: Opening

[0065] 344: Gate electrode

[0066] 346: Gate spacer

[0067] 348: Inner spacer

[0068] 350: Epitaxial structure (epitaxy ring) (epitaxy pair)

[0069] 350': Extensional ring

[0070] 350a: Epitaxial ring

[0071] 350b: Epitaxial ring

[0072] 352: Silicide layer (silicide ring)

[0073] 353: Emphasis on epitaxial rings

[0074] 360°: Contact structure (contact ring)

[0075] 420: Fins

[0076] 430: Isolation structure (isolation line)

[0077] 440: Gate structure (gate line)

[0078] 450: Epitaxial Structure

[0079] 452: Silice layer (silicide line)

[0080] 460: Contact structure (contact wire)

[0081] 465: Gap area (gap)

[0082] 500: Methods

[0083] 502, 504, 506, 508, 510, 512, 514: Operations

[0084] 600: Mask

[0085] 620: Mask

[0086] 640: Interlayer dielectric characteristics (interlayer dielectric layer)

[0087] A, B, C, D: Regions

[0088] G1, G2: Gap Detailed Implementation

[0089] The following disclosure provides numerous different embodiments or examples to implement various features of this disclosure. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where additional features are formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in different examples of the following disclosure. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or structures discussed.

[0090] Furthermore, spatially related terms, such as “below,” “under,” “lower,” “above,” “higher,” and similar terms, are used to facilitate the description of the relationship between one element or feature and another element(s) in the illustrations. In addition to the orientations shown in the figures, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way. Further, unless otherwise specified, according to the scope understood by one of skill in the specific art disclosed herein, when using terms such as “approximately,” “about,” etc., to describe numbers or ranges of numbers, this terminology covers a reasonable range including the described number, for example, within + / - 10% of the described number. For example, the term “approximately 5 nanometers” can cover size ranges from 4.5 nanometers to 5.5 nanometers, from 4.0 nanometers to 5.0 nanometers, etc.

[0091] The sealing ring structure can be formed simultaneously with structures in the circuit region (or chip region, device region) and may include transistor components similar to those in the transistors of the chip region. The transistor components in the sealing ring structure do not provide electrical functionality to the chip as they do in the device region. Instead, the transistor components in the sealing ring structure surround and protect the chip region from moisture, mechanical stress, or other defect-causing mechanisms. When the chip region includes n-type transistors with n-type epitaxial structures (or source / drain structures) and p-type transistors with p-type epitaxial structures, the corresponding n-type and p-type epitaxial structures may also be located in the sealing ring region. The n-type and p-type epitaxial structures are formed in different processes. In subsequent processes forming different types of epitaxial structures, previously formed epitaxial structures may be damaged due to process limitations, such as misalignment and over-etching, thereby jeopardizing the stability and reliability of the previously formed epitaxial structures. For example, if p-type epitaxial structures are formed first, they may be inadvertently etched due to misalignment during the formation of the n-type epitaxial structure. Inadvertent etching may affect the stability and / or reliability of the p-type epitaxial structure used as part of the sealing ring structure.

[0092] This disclosure generally relates to semiconductor structures and their manufacturing processes. More specifically, this disclosure provides a sealing ring structure comprising a single type of epitaxial structure to improve processability and the stability of the sealing ring. The transistor components in the sealing ring structure do not provide electrical functionality to the chip like device regions. Instead, the transistor components in the sealing ring structure surround and protect the chip region from moisture, mechanical stress, or other defect-causing mechanisms. Therefore, the type of epitaxial structure in the sealing ring region can be controlled to prevent damage in subsequent processes.

[0093] In embodiments of this disclosure, all epitaxial structures in the sealing ring region may be of the same material and have the same conductivity type. For example, all epitaxial structures in the sealing ring region may be n-type, p-type, or undoped epitaxial structures. In one embodiment, all epitaxial structures in the sealing ring region are p-type epitaxial structures, wherein the sealing ring region does not contain n-type epitaxial structures. In another embodiment, all epitaxial structures in the sealing ring region are n-type epitaxial structures, wherein the sealing ring region does not contain p-type epitaxial structures. In some embodiments, p-type epitaxial structures provide higher stability to the sealing ring structure. The single type of epitaxial structure in the sealing ring region prevents unintentional damage caused by introducing different types of epitaxial structures, such as over-etching of existing epitaxial structures during the formation of subsequent epitaxial structures. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein.

[0094] Figure 1This is a top plan view of a semiconductor structure 100 according to the present disclosure. The semiconductor structure 100 (e.g., a fabricated wafer or a portion thereof) includes a sealing ring region 300 surrounding a circuit region (or device region, integrated circuit die, chip region) 200. In some embodiments, the semiconductor structure 100 may include other sealing ring regions(s) surrounding the sealing ring 300, or other sealing rings(s) surrounded by the sealing ring region 300. Furthermore, the sealing ring region 300 may surround other circuit regions(s). The circuit region 200 may include any circuitry, such as a memory, processor, transmitter, receiver, etc. The exact functionality of the circuit region 200 is not limited to the embodiments of the present disclosure.

[0095] In this embodiment, the sealing ring region 300 includes a sealing ring structure 302. Figure 1 and Figure 4 The sealing ring region 300 has a rectangular or substantially rectangular perimeter that completely surrounds the circuit region 200. The four corners of the rectangular perimeter are replaced by beveled corner lines connecting the adjacent edges of the rectangle. In this embodiment, each beveled corner line is substantially at 45° to the X direction. The sealing ring region 300 also includes four outer corner regions 304 disposed at the corners of the sealing ring region 300. Each outer corner region 304 is disposed outside the sealing ring structure 302 and along the corresponding beveled corner line. The sealing ring region 300 also includes four inner corner regions 306 disposed along the corresponding beveled corner lines and between the sealing ring structure 302 and the circuit region 200. The outer corner regions 304 and inner corner regions 306 provide further mechanical strength to the sealing ring region 300. The outer corner regions 304 are substantially triangular, and the inner corner regions 306 are substantially trapezoidal. In some embodiments, the sealing ring structure 302 may provide openings at selected locations and / or in selected layers to allow the circuit region 200 to interact with other areas not in the same layer. Figure 1 The interconnections between the circuit regions shown are illustrated. In some embodiments, the sealing ring region 300 may have a non-rectangular shape.

[0096] Figure 2 for Figure 1The diagram shows an enlarged top view of region A within circuit region 200. Circuit region 200 includes fins (active regions) 220 oriented longitudinally along the X direction, isolation structures 230 disposed between and separating the fins 220, gate structures 240 oriented longitudinally along the Y direction and above the fins 220, and contact structures 260 oriented longitudinally along the Y direction and above the fins 220. These elements form a matrix, and transistors are formed at the intersection between the fins 220 and the gate structures 240. The transistors can be planar metal-oxide-semiconductor field-effect transistors (MOSFETs) or multi-gate transistors. Multi-gate transistors generally refer to devices or portions thereof having gate structures disposed above more than one side of the channel region. Increasingly common examples of multi-gate devices include fin-like field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors. A fin field-effect transistor has an elevated channel covered by a gate on more than one side (for example, the gate covers the top and sidewalls of a "fin" of semiconductor material extending from the substrate). A multi-bridge channel transistor has a gate structure that extends partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a multi-bridge channel transistor can also be called a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor.

[0097] It should be noted that, although the fins 220 and the gate structure 240 are in Figure 2 As shown in the diagram, extending continuously along the X or Y direction, the fins 220 and gate structure 240 can be divided into multiple segments by multiple dielectric features according to the circuit design of the semiconductor structure 100.

[0098] Figure 3 for Figure 1 The enlarged top view of region B in the sealing ring region 300 shown is illustrated. The sealing ring region 300 includes fin-type structures 320 arranged longitudinally along the Y direction, isolation structures 330 disposed between and separating the fin-type structures 320, a gate-type structure 340 arranged longitudinally along the Y direction, and a contact structure 360 ​​arranged longitudinally above the fin-type structures 320 along the Y direction. (See also...) Figure 1Each fin structure 320, gate structure 340, contact structure 360, and isolation structure 330 forms a continuous ring that completely surrounds the circuit region 200, and is thereby referred to herein as a fin ring 320, a gate ring 340, a contact ring 360, and an isolation ring 330. Each fin ring 320, gate ring 340, contact ring 360, and isolation ring 330 concentrically surrounds (or completely surrounds) the circuit region 200 and extends substantially parallel to each other.

[0099] The sealing ring region 300 may include fin field-effect transistor components, gate-around transistor components, other types of transistors, and combinations thereof. The transistor components in the sealing ring region 300 are formed simultaneously with the transistors in the device region and are consistent with the type of the device region. For example, if the circuit region includes a fin field-effect transistor, the sealing ring region includes components similar to and corresponding to those in the fin field-effect transistor. In another example, if the circuit region includes a gate-around transistor, the sealing ring region includes components similar to and corresponding to those in the gate-around transistor. A cross-sectional view of the sealing ring region 300 including fin field-effect transistor components is shown. Figures 4 to 9 Let's discuss this together. Similarly, a cross-sectional view of the sealing ring region 300 of the gate-around-the-ring transistor, along with... Figures 10 to 16 Let's discuss it together.

[0100] Figure 4 For along Figure 1 and Figure 3 Line segment 1-1 shows a cross-sectional view of the semiconductor structure 100 in the sealing ring region 300, wherein the sealing ring region 300 includes fin field-effect transistor-type components. Fin rings 320 protrude in pairs from the semiconductor substrate 102 along the Z-direction and are parallel to each other. The gap G1 between each pair of fin rings 320 and the gap G2 between the two fin rings 320 in each pair may vary along the X-direction in the sealing ring region 300. In this embodiment, the sealing ring region 300 has a uniform gap G1 between each pair of fin rings 320 and a uniform gap G2 between the two fin rings 320 in each pair, wherein gap G1 is larger than gap G2. The fin rings 320 may comprise silicon, germanium, silicon-germanium, or other suitable semiconductor materials.

[0101] The semiconductor structure 100 also includes a gate ring 340 disposed over a fin ring 320 in the sealing ring region 300. Each gate ring 340 forms a substantially annular shape, extends parallel to the fin ring 320, and surrounds the circuit region 200. Each gate ring 340 is formed over one or more fin rings 320. In some embodiments, the gate ring 340 is formed over one or more pairs of fin rings 320. For example, in Figure 4In the illustrated embodiment, a gate ring 340 is formed above two pairs of fin rings 320. The width of each gate ring 340 is greater than the width of each fin ring 320. Accordingly, the gate ring 340 covers the fin ring 320 disposed below it, as shown below. Figure 3 and Figure 4 As shown. Figure 5 and Figure 6 As shown, each gate ring 340 includes a gate electrode 344 and a gate dielectric layer 342 disposed between the fin ring 320 and the gate electrode 344, separating the fin ring 320 and the gate electrode 344. The gate electrode 344 may include tungsten, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), titanium, tantalum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum aluminum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), manganese, zirconium, other suitable work function metals, or combinations thereof. The gate dielectric layer 242 may include a dielectric material with a high dielectric constant, such as: hafnium oxide (ZrO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (S). Hafnium trioxide (HfZrO), barium titanate (BTO), barium zirconate (BaZrO), hafnium zirconium oxide (HfZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicate (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)TiO3, BST), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0102] like Figure 5 As shown, along Figure 1 , Figure 3 and Figure 4 As shown in line segment 2-2, in the cross-sectional view of the sealing ring region 300, the gate dielectric layer 342 contacts the top surface of the fin ring 320. Figure 6 As shown, along Figure 4As shown in line segment 3-3, in the cross-sectional view of the sealing ring region 300, the gate dielectric layer 342 contacts the top surface of the isolation structure 330. In one embodiment, the gate dielectric layer 342 may include a dielectric material such as hafnium oxide (HfO2) and may be applied by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate electrode 344 may include a single-layer or multi-layer structure and may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (AlTi), or tungsten.

[0103] Refer to Figure 4 The semiconductor structure 100 also includes an epitaxial structure 350 disposed above the fin ring 320 in the sealing ring region 300. The epitaxial structure 350 and the gate ring 340 are disposed above different fin rings 320 or different groups of fin rings 320. Each epitaxial structure 350 forms a substantially ring-shaped structure surrounding the circuit region 200 and is therefore referred to hereinafter as an epitaxial ring 350. Each epitaxial ring 350 extends parallel to the fin ring 320 around the entire circuit region 200.

[0104] All epitaxial rings 350 in the sealing ring region comprise the same material. For example, all epitaxial rings 350 in the sealing ring region 300 are p-type epitaxial rings. In another example, all epitaxial rings 350 in the sealing ring region 300 are n-type epitaxial rings. In yet another example, all epitaxial rings 350 in the sealing ring region 300 are undoped epitaxial rings. The p-type epitaxial material may include epitaxial silicon germanium (epi SiGe), wherein the silicon germanium is doped with p-type dopants such as boron, gallium, indium, and / or other p-type dopants. The n-type epitaxial material may include epitaxial silicon (epi Si) or epitaxial silicon carbide (epi SiC), wherein the silicon or silicon carbide is doped with n-type dopants such as arsenic, phosphorus, and / or other n-type dopants. Undoped epitaxial rings may include silicon germanium, silicon, or silicon carbide without containing any dopants. Unlike the epitaxial structure in circuit region 200, the epitaxial ring 350 in sealing ring region 300 does not have electronic functionality as a typical active component of a transistor. Instead, the epitaxial ring 350 is part of sealing ring structure 302, used to protect circuit region 200 from dust, moisture, mechanical stress, and / or other sources of damage. All epitaxial rings 350 in sealing ring region 300 are made of the same material to prevent unintended damage that might occur if different materials were used in the epitaxial rings 350, without affecting the functionality of the epitaxial ring 350 as part of sealing ring structure 302.

[0105] Each extensional ring 350 is formed above one or more fin rings 320. For example, in Figure 4In the illustrated embodiment, an epitaxial ring 350 is formed over a pair of fin rings 320. The epitaxial rings 350 may be separate from each other, merged together, or a combination thereof. For example, an epitaxial ring 350a disposed over a first pair of fin rings 320 and an epitaxial ring 350b disposed over a second pair of fin rings 320 are merged together, wherein the second pair of fin rings 320 is adjacent to the first pair of fin rings 320. Figure 4 Two merged extensional rings 350 are also called extensional pairs 350. Adjacent extensional pairs 350 can be further merged together, such as... Figure 9 As shown.

[0106] Still refer to Figure 4 The semiconductor structure 100 also includes a silicide layer 352 disposed above the epitaxial ring 350. Each silicide layer 352 forms a substantially annular ring surrounding the circuit region 200 in the sealing ring region, and is therefore referred to hereinafter as a silicide ring 352. In at least some embodiments, the silicide ring 352 is substantially parallel to the epitaxial ring 350 and surrounds the entire circuit region 200. In some embodiments, the silicide rings 352 are disposed above individual epitaxial rings 350 and are separated from each other. In alternative embodiments, such as Figure 7 As shown, a silicide ring 352 is disposed above the merged epitaxial ring 350 to form the merged silicide ring 352. The epitaxial ring 350 may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, other suitable silicides, or combinations thereof.

[0107] The semiconductor structure 100 also includes a contact structure 360 ​​disposed above the silicide ring 352. While the epitaxial ring 350 may be a continuous ring surrounding the circuit region 200, the contact structure 360 ​​may or may not be a continuous ring surrounding the circuit region 200. Figure 7 and Figure 8 A cross-sectional view along line segment 4-4 is shown to illustrate the continuous and segmented contact structure 360. Figure 7 In some of the represented embodiments, each contact structure 360 ​​forms a substantial ring in the sealing ring region surrounding the circuit region 200, and is therefore referred to hereinafter as contact ring 360. The contact ring 360 may rest on a single epitaxial ring 350 (within which a silicide ring 352 is present, if present) (e.g. Figure 7 (as shown) or on the merged extensional ring 350 (such as Figure 9 (As shown). Contact ring 360 (via silicide ring 352, if present) connects the epitaxial ring 350 to the portion of the sealing ring structure 302 subsequently formed at the rear end of the production line. Contact ring 360 may include any suitable conductive material, such as: cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, titanium nitride, tantalum nitride, tantalum, and / or other suitable conductive materials. Figure 8In some representative embodiments, each contact structure 360 ​​is separated by multiple interlayer dielectric (ILD) features 640 and becomes segmented (discontinuous). In the illustrated embodiment, the interlayer dielectric features 640 extend into the silicide ring 352 and divide the silicide ring 352 into different segments. In other embodiments, the interlayer dielectric features 640 do not extend through the entire silicide ring 352, leaving the silicide ring 352 substantially intact.

[0108] Still refer to Figure 4 Fin rings 320, isolation rings 330, gate rings 340, epitaxial rings 350, and contact rings 360 are alternately arranged along the X direction in the sealing ring region 300. The number of epitaxial rings 350 and contact rings 360 disposed between two adjacent gate rings 340 may vary along the X direction in the sealing ring region 300. For example, in Figure 4 In the illustrated embodiment, four pairs of fin rings (eight fin rings) 320 and one contact ring 360 are disposed between two adjacent gate rings 340. This configuration improves manufacturability and the stability of the sealing rings. For example, the spacing of the gate rings 340, epitaxial rings 350, and contact rings 360 is configured to match the pattern density in the circuit region to improve topography and prevent dishing in subsequent chemical mechanical planarization processes. The multiple epitaxial rings 350 between two adjacent gate rings 340, especially when they are joined together, provide a better drop surface and stability for the contact ring 360.

[0109] Figure 10 and Figure 11 For along Figure 1 and Figure 10 The lines 1-1 and 2-2 shown are cross-sectional views of the semiconductor structure 100 in the sealing ring region 300, where the sealing ring region 300 includes a ring-gate component. The fins (active regions) of the ring-gate transistor are formed by alternately stacking a first semiconductor layer 322 and a second semiconductor layer 323. In some examples, the first semiconductor layer 322 comprises silicon and the second semiconductor layer 323 comprises silicon-germanium, such that the second semiconductor layer 323 can be selectively removed in a channel release process. However, because the gate ring 340 in the sealing ring region 300 extends parallel to the fin ring 320', the second semiconductor layer 323 in the fin ring 320' is not selectively removed. Accordingly, as Figure 10 As shown, both the first semiconductor layer 322 and the second semiconductor layer 323 remain within the fin ring 320'. Except for the explicitly stated configurations, the above references... Figures 4 to 9 The embodiments of the sealing ring region 300 discussed also apply to sealing ring regions 300 including ring gate type members. For example... Figure 10As shown, each fin ring 320' is directly disposed between two extension rings 350' along the X direction.

[0110] like Figure 10 and Figure 11 As shown, the sealing ring region 300 includes a ring gate-type member. Figure 10 In the illustrated embodiment, each gate ring 340' is disposed above one of the fin rings 320', and each fin ring 320' includes a first semiconductor layer 322 with a second semiconductor layer 323 inserted therebetween. In some embodiments, not all fin rings 320' are disposed below the gate ring 340'. In other words, some fin rings 320' may not include any gate rings 340' above them. The gate ring 340' includes a gate dielectric layer 342 and a gate electrode 344. The gate dielectric layer 342 separates the gate electrode 344 from the top surface of the first semiconductor layer 322 at the top of the fin ring 320'. The semiconductor structure 100 also includes a gate spacer 346 and an inner spacer 348 disposed on the sidewall of the gate ring 340'. The inner spacer separates the second semiconductor layer 323 from the epitaxial ring 350', but neither has an electrical function.

[0111] The sealing ring region 300 also includes dummy fin rings 332 disposed between the fin rings 320' and around the circuit region 200 to provide isolation and adjust the distance between the fin rings 320'. An extension ring 350' is also disposed between the fin rings 320' and the dummy fin rings 332. All extension rings 350' in the sealing ring region 300 are formed of the same material to prevent accidental damage from forming extension rings 350' comprising more than one material.

[0112] Figure 10 The sealing ring region 300 shown also includes contact structures 360, each contact structure 360 ​​being at least partially disposed above the outer ring 350'. Figure 10 In some representative embodiments, each contact structure 360 ​​is disposed above an epitaxial ring 350' and a dummy fin ring 332. In some specific embodiments, the silicide ring 352 may be disposed between the epitaxial ring 350' and the contact structure 360. Although the epitaxial ring 350 may be a continuous ring surrounding the circuit region 200, the contact structure 360 ​​may or may not be a continuous ring surrounding the circuit region 200. Figure 12 and Figure 13 A cross-sectional view along line segment 4-4 is shown to illustrate the continuous and segmented contact structure 360. Figure 12In some representative embodiments, each contact structure 360 ​​forms an annulus in the sealing ring region surrounding the circuit region 200, and is therefore referred to hereinafter as contact ring 360. Contact ring 360 (via silicide ring 352, if present) connects the epitaxial ring 350 to a portion of the sealing ring structure 302 subsequently formed at the rear end of the production line. Contact ring 360 may comprise any suitable conductive material, such as cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, titanium nitride, tantalum nitride, tantalum, and / or other suitable conductive materials. Figure 13 In some representative embodiments, each contact structure 360 ​​is separated by multiple interlayer dielectric (ILD) features 640 and becomes segmented (discontinuous). In the illustrated embodiment, the interlayer dielectric features 640 extend into the silicide ring 352 and divide the silicide ring 352 into distinct segments. In other embodiments, the interlayer dielectric features 640 do not extend through the entire silicide ring 352, leaving the silicide ring 352 substantially intact.

[0113] In some Figure 14 In the alternative embodiment shown, each fin ring 320' is sandwiched between a dummy fin ring 332 and a lopsided epitaxial ring 353. That is, the fin ring 320' is not sandwiched between the two epitaxial rings 350'. Because the sidewall of each fin ring 320' is pushed to the bottom to abut against the dummy fin ring 332, the inner spacer 348 is formed only at one end adjacent to each second semiconductor layer 323. In other words, along the X direction, each second semiconductor layer 323 is disposed between the dummy fin ring 332 and the inner spacer 348.

[0114] Figure 14 The sealing ring region 300 shown also includes contact structures 360, each contact structure 360 ​​being at least partially disposed above the biased outer ring 353. Figure 14 In some representative embodiments, each contact structure 360 ​​is disposed above the biased epitaxial ring 353 and the dummy fin ring 332. In some specific embodiments, the silicide ring 352 may be disposed between the epitaxial ring 350' and the contact structure 360. Although the biased epitaxial ring 353 may be a continuous ring surrounding the circuit region 200, the contact structure 360 ​​may or may not form a continuous ring surrounding the circuit region 200. Figure 15 and Figure 16 A cross-sectional view along line segment 4-4 is shown to illustrate the continuous and segmented contact structure 360. Figure 15In some representative embodiments, each contact structure 360 ​​forms a ring within a sealing ring region 300, surrounding the circuit region 200, and is therefore referred to hereinafter as contact ring 360. Contact ring 360 connects the epitaxial ring 350 (via a silicide ring 352, if present) to a portion of the sealing ring structure 302 subsequently formed at the rear end of the production line. Contact ring 360 may comprise any suitable conductive material, such as cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, titanium nitride, tantalum nitride, tantalum, and / or other suitable conductive materials. Figure 16 In some representative embodiments, each contact structure 360 ​​is separated by multiple interlayer dielectric (ILD) features 640 and becomes segmented (discontinuous). In the illustrated embodiment, the interlayer dielectric features 640 extend into the silicide ring 352 and divide the silicide ring 352 into distinct segments. In other embodiments, the interlayer dielectric features 640 do not extend through the entire silicide ring 352, leaving the silicide ring 352 substantially intact.

[0115] Figure 17 Show Figure 1 The diagram shows an enlarged top view of region C. In this disclosure, transistor-type components are selectively placed in the outer corner region 304 and inner corner region 306 of the sealing ring region 300. The transistor-type components in the sealing ring region 300 are non-electrically functional and are formed to reduce process variations, such as denting problems during subsequent chemical mechanical planarization (CMP) processes or other types of manufacturing process problems. The outer corner region 304 and inner corner region 306 may include one or more transistor-type components selected from fins 420, isolation structures 430, epitaxial structures 450, silicide layers 452, gate structures 440, contact structures 460, other suitable components, or combinations thereof. These components are arranged longitudinally in a straight line and substantially parallel to the beveled corner lines, and are therefore referred to as fins 420, isolation lines 430, epitaxial lines 450, silicide lines 452, gate lines 440, and contact lines 460. The transistor-type components in the outer corner region 304 and the inner corner region 306 are formed simultaneously with their counterparts in the circuit region 200 and the sealing ring region 300. Except for the explicitly stated differences, the outer corner region 304 and the inner corner region 306 include transistor-type components similar to those described above with reference to the circuit region 200 and the sealing ring region 300.

[0116] Figure 18 Show along Figure 17The diagram shows a cross-sectional view of the outer corner region 304, represented by line segment 5-5. Line segment 4-4 is the diagonal of the semiconductor structure 100, forming a 45° angle with the X direction. The outer corner region 304 includes a fin 420, an isolation structure 430, an epitaxial structure 450, a silicide layer 452, and a contact structure 460. The outer corner region 304 has a gap region 465, in which the fin 420 is not included in the gate structure 440, epitaxial structure 450, and contact structure 460 above it. The gap region 465 includes a silicide layer 452 directly disposed above and in contact with the fin 420. The silicide layer 452 is formed above the fin 420 simultaneously with the gate dielectric layer 242 in the circuit region 200 and the silicide ring 352 in the sealing ring region 300. The gap region 465 is longitudinally disposed, substantially perpendicular to the longitudinal direction of the fin 420. The extension line along the length of the gap region 465 intersects with the fin 420, gate structure 440, epitaxial structure 450, and silicide layer 452 in the outer corner region 304. Figure 4 ).

[0117] Figure 19 Show along Figure 17 The line segment 5-5 shown is a cross-sectional view of the inner corner region 306. The inner corner region 306 includes a fin 420, an isolation structure 430, a silicide layer 452, and a contact structure 460. Figure 19 The cross-sectional area of ​​the inner corner region 306 shown does not include the gate structure 440 and the epitaxial structure 450. Other cross-sectional areas of the inner corner region 306 may include those similar to... Figure 18 The gate structure 440 and epitaxial structure 450 are shown. A silicide layer 452 is deposited directly on and in direct contact with the fin 420. A contact structure 460 is disposed above a portion of the fin 420 (with the silicide layer 452 disposed therein, if present). The remaining portion of the fin 420 does not include the gate structure 440, epitaxial structure 450, or contact structure 460. The outer corner region 304 and inner corner region 306 are designed for various mechanical considerations, such as preventing layer peeling at the chip corners during the dicing process.

[0118] Figure 20 The flowchart above describes a method 500 for manufacturing a semiconductor structure 100 according to various forms of this disclosure, wherein the semiconductor structure 100 is referred to above. Figures 1 to 8 and Figures 10 to 19 Discussion. Additional operations may be provided before, during, and after method 500, and for some additional embodiments of method 500, some described operations may be moved, replaced, or deleted. Method 500 is described below together with Figures 21 to 54 describe, Figures 21 to 54Various cross-sectional views of the semiconductor structure 100 are shown according to some embodiments, during various steps of manufacturing according to method 500. In these figures... Figure 21 and Figure 22 for Figure 1 A three-dimensional view of region A in circuit region 200 and region B in sealing ring region 300 of semiconductor structure 100; Figure 23 , Figure 27 , Figure 31 , Figure 35 , Figure 39 , Figure 43 , Figure 47 and Figure 51 For along Figure 21 Line segment 6-6 in the diagram is a cross-sectional view of semiconductor structure 100; Figure 24 , Figure 28 , Figure 32 , Figure 36 , Figure 40 , Figure 44 , Figure 48 and Figure 52 For along Figure 22 Line segment 2-2 in the figure, cross-sectional view of semiconductor structure 100; Figure 25 , Figure 29 , Figure 33 , Figure 37 , Figure 41 , Figure 45 , Figure 49 and Figure 53 For along Figure 21 Line segment 7-7 in the diagram is a cross-sectional view of semiconductor structure 100; Figure 26 , Figure 30 , Figure 34 , Figure 38 , Figure 42 , Figure 46 , Figure 50 and Figure 54 For along Figure 22 Line segment 1-1 in the figure is a cross-sectional view of semiconductor structure 100.

[0119] The semiconductor structure 100 described in detail below shows the components of the fin field-effect transistor in circuit region 200 and sealing ring region 300, as well as... Figures 1 to 9 and Figures 17 to 19The embodiments shown are provided for simplicity and ease of understanding and are not intended to limit the embodiments to any type of device, any number of devices, any number of regions, or any configuration of region structures. For example, the same inventive concept can be applied to the manufacture of devices including gate-around-ahead (GAA) transistors. Furthermore, the semiconductor structure 100 can be an intermediate device manufactured during the processing of an integrated circuit or a portion thereof, and may include static random access memory (SRAM) and / or logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as: P-channel field-effect transistors (PFETs), N-channel field-effect transistors (NFETs), FinFETs, gate-around-ahead (GAA) field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof. Throughout this disclosure, unless otherwise specified, similar reference numerals denote similar features.

[0120] In case of error 502, refer to... Figure 20 and Figures 23 to 30 Method 500 receives a semiconductor substrate (or substrate) 102. In this embodiment, the semiconductor substrate 102 is a silicon substrate. Alternatively, the semiconductor substrate 102 may include another elemental semiconductor, such as germanium; composite semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP); or combinations thereof. In yet another alternative embodiment, the semiconductor substrate 102 is a semiconductor-on-insulator (SOI), such as an embedded dielectric layer.

[0121] The semiconductor substrate 102 also includes fins (or active regions) 220 (including fin 220a and fin 220b adjacent to fin 220a) in the circuit region 200 and fin rings 320 in the sealing ring region 300. The fins 220 are formed along parallel lines in the Y direction in the circuit region 200, and each fin ring 320 is formed circumferentially in the sealing ring region 300, surrounding the circuit region 200. In this disclosure, the fins 220 and fin rings 320 are considered as part of the semiconductor substrate 102. The fins 220 and fin rings 320 can be manufactured using suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer (photoresist) covering the semiconductor substrate 102, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a mask element including the photoresist. A mask element is then used to etch recesses into the semiconductor substrate 102, leaving the fins 220 and fin rings 320 on the semiconductor substrate 102. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. Alternatively, in this embodiment, the fins 220 and fin rings 320 are formed using a double-patterning lithography (DPL) process, wherein mandrels are used to form the fins 220 and fin rings 320. The mandrels are formed above the semiconductor substrate 102 to support thin spacers above its sidewalls. The mandrels are subsequently removed, leaving the spacers as a mask for etching the semiconductor substrate 102 alone. The portion of the semiconductor substrate 102 protected under the spacers forms the fins 220 and fin rings 320. The fins 220 and fin rings 320 may be formed in pairs, extending from the sidewalls of the mandrels. Several other method embodiments for forming the fin 220 and fin ring 320 may be suitable.

[0122] Adjacent fins 220 and adjacent fin rings 320 are separated by isolation structures 230 and isolation rings 330, respectively. Isolation structures 230 and isolation rings 330 may be made of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-dielectric-constant dielectric materials, and / or other suitable insulating materials. Isolation structures 230 and isolation rings 330 may be shallow trench isolation (STI) structures. In one embodiment, isolation structures 230 and isolation rings 330 are formed by etching trenches in the semiconductor substrate 102, for example, as part of the formation process of fins 220 and fin rings 320. The trenches may then be filled with an isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation features, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, are possible. The isolation structure 230 and the isolation ring 330 may include a multi-layer structure, for example, having one or more thermal oxide linings.

[0123] Still refer to Figure 20 and Figures 23 to 30 Method 500 further forms a dummy gate structure 241 in circuit region 200 and a dummy gate ring 341 in sealing ring region 300. The dummy gate structure 241 is longitudinally substantially perpendicular to the longitudinal direction of fin 220, while the dummy gate ring 341 is longitudinally substantially parallel to the longitudinal direction of fin ring 320. The dummy gate structure 241 and dummy gate ring 341 may include gate spacers 246 and 346 (respectively), a hard mask layer (not shown), and a capping layer (not shown). Gate spacers 246 and 346 may include a single-layer or multi-layer structure and may include a dielectric material such as silicon nitride (SiN). In one embodiment, the dummy gate structure 241 and dummy gate ring 341 comprise polysilicon. Gate spacers 246 and 346 may be formed by atomic layer deposition, thermal deposition, or other suitable methods. In some embodiments, the dummy gate structure 241 and the dummy gate ring 341 are sacrificial gate structures, i.e., placeholders for the final gate stack. In this disclosure, the fin 220 and fin ring 320, the isolation structure 230 and isolation ring 330, the dummy gate structure 241, and the dummy gate ring 341 are all considered as part of the semiconductor substrate 102. In some embodiments, as shown in reference... Figure 19 As explained, the epitaxial structure and gate structure are not formed in the inner corner region 306.

[0124] When encountering error 504, refer to... Figure 20 and Figures 27 to 30In method 500, fins 220a in the circuit region and fins 320 in the sealing ring region are etched to form recesses 222 and 324, respectively, while fins 220b in the circuit region are protected under a mask 600. The etching process can be dry (plasma) etching, wet etching, etc. In one embodiment, the etching process includes a dry etching process using a combination of hydrogen bromide / chlorine / oxygen / helium (HBr / Cl2 / O2 / He). In another embodiment, the etching process includes a dry etching process using a combination of germane / hydrochloric acid / hydrogen / nitrogen (GeH4 / HCl / H2 / N2). The mask 600 may include a photoresist mask or other suitable mask and is removed after the etching process. Afterward, a cleaning process for recesses 222 and 324 can be performed using a hydrofluoric acid (HF) solution or other suitable solution.

[0125] In operation 506, refer to Figure 20 and Figures 31 to 34 Method 500 continues by growing an epitaxial structure 250a in the recess 222 and an epitaxial ring 350 in the recess 324. The epitaxial structure 250a and the epitaxial ring 350 in the sealing ring region 300 are formed simultaneously during the epitaxial process and include elements related to the reference... Figure 2 The same materials are discussed. Epitaxial processes may utilize chemical vapor deposition (CVD) techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum chemical vapor deposition (UHV-CVD)), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. Epitaxial processes may utilize gaseous and / or liquid precursors that interact with the composition of fin 220a and fin ring 320. Epitaxial structure 250a and epitaxial ring 350 may comprise silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof. Alternatively, epitaxial structure 250a and epitaxial ring 350 may comprise silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some alternative embodiments, epitaxial ring 350 may comprise silicon-germanium, germanium, or silicon without dopants. Undoped epitaxial ring 350 and epitaxial structure 250a are formed in separate processes. In this embodiment, the epitaxial structure 250a and the epitaxial ring 350 comprise silicon-germanium doped with a p-type dopant. In some embodiments, the epitaxial structure 250a and the epitaxial ring 350 comprise more than one epitaxial semiconductor layer.

[0126] When operating 508, refer to... Figure 20 and Figures 35 to 38In method 500, a mask 620 is formed over a semiconductor structure 100. The mask 620 completely covers the sealing ring region 300 and partially covers the circuit region 200. For example, an epitaxial structure 250a is covered under the mask 620, and fins 220b in the circuit region 200 are exposed. The mask 620 prevents accidental damage to the sealing ring region (especially the epitaxial ring 350) and the device region during subsequent processes (e.g., the formation of the epitaxial structure 250b, which will be described below). The mask 620 may include references to... Figures 27 to 30 The composition of the mask 600 under discussion is the same, and it can be formed in a similar manner to the mask 600.

[0127] In operation 510, refer to Figures 39 to 42 In method 500, fin 220b is etched to form a recess 224 in the source / drain region of fin 220b, while a portion of fin 220b and the entire sealing ring region 300 are covered by a mask 620. The etching process can be dry (plasma) etching, wet etching, etc. Etching of fin 220b may inadvertently damage other components of the semiconductor structure 100. For example, in the case of misalignment, etching of fin 220b may accidentally etch a portion of the epitaxial structure 250a. If the epitaxial ring 350 in the sealing ring region 300 is inadvertently etched during the etching of the recess 224, it will affect the stability and reliability of the sealing ring structure 302. In this embodiment, the entire sealing ring region 300 is covered by a mask 620. The mask 620 prevents any inadvertent damage that may occur during the etching of the recess 224, thereby improving the stability and reliability of the sealing ring structure 302. It should be noted that the only epitaxial ring in the sealing ring region 300 is the epitaxial ring 350. Epitaxial ring 350 is of a single type, selected from n-type, p-type, or undoped epitaxial rings. In other words, all epitaxial rings in sealing ring region 300 are of the same type, selected from n-type, p-type, or undoped epitaxial rings.

[0128] In operation 512, refer to Figure 20 and Figures 43 to 46Method 500 continues by growing an epitaxial structure 250b in a recess 224 in circuit region 200. Epitaxial structure 250b comprises a material different from that of epitaxial structure 250a and epitaxial ring 350. For example, if epitaxial structure 250a and epitaxial ring 350 are p-type epitaxial structures, epitaxial structure 250b is an n-type epitaxial structure. Similarly, if epitaxial structure 250a and epitaxial ring 350 are n-type epitaxial structures, epitaxial structure 250b is a p-type epitaxial structure. During the formation of epitaxial structure 250b, sealing ring region 300 completely covers the mask 620, thereby still having a single type of epitaxial ring 350 and not including epitaxial structure 250b. In some embodiments, epitaxial structure 250a, epitaxial structure 250b, and epitaxial ring 350 are not formed in inner corner region 306. The mask 620 is subsequently removed using any suitable process, such as ashing and / or photoresist removal.

[0129] In operation 512, refer to Figure 20 and Figures 47 to 54 Method 500 performs further operations, such as replacing the dummy gate structure 241 and the dummy gate ring 341 with the gate structure 240 and the gate ring 340 respectively, and forming the contact structure 260 and the contact ring 360.

[0130] Reference Figures 47 to 50 An interlayer dielectric (ILD) layer 640 is formed over the semiconductor substrate 102 through processes such as deposition and chemical mechanical planarization. In one embodiment, the interlayer dielectric layer 640 is formed by a flowable chemical vapor deposition (FCVD) process. Then, a chemical mechanical planarization process is performed on the interlayer dielectric layer 640 to expose the dummy gate structure 241 and the dummy gate ring 341. Subsequently, the dummy gate structure 241 and the dummy gate ring 341 are removed by one or more selective etching processes, thereby forming an opening 243 in the circuit region 200 and an opening 343 in the sealing ring region 300. During the etching process, the gate spacers 246 and 346 remain intact.

[0131] Reference Figures 51 to 54One or more material layers are deposited into openings 243 and 343 to form gate structure 240 and gate ring 340, respectively. In this embodiment, each gate structure 240 and gate ring 340 includes gate dielectric layer 242 and gate dielectric layer 342, gate electrode 244 and gate electrode 344, respectively, above gate dielectric layer 242 and gate dielectric layer 342. Each gate dielectric layer 242 and gate dielectric layer 342 may include a high dielectric constant dielectric material, such as hafnium dioxide (HfO2), lanthanum oxide (La2O3), other suitable materials, or combinations thereof. Each metal gate electrode 244 and gate electrode 344 may include at least one work function metal layer and a bulk conductive layer disposed thereon. The work function metal layer may be a p-type or n-type work function metal layer. Examples of work function metals include: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), titanium, tantalum aluminide (TaAl), aluminum tantalum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum nitride carbide (TaCN), tantalum silicon nitride (TaSiN), manganese, zirconium, other suitable work function metals, or combinations thereof. The main conductive layer may include copper, tungsten, aluminum, cobalt, ruthenium, other suitable materials, or combinations thereof. The gate structure 240 and gate ring 340 may also include other material layers (not shown), such as: interface layers, capping layers, barrier layers, other suitable layers, or combinations thereof. The various layers of the gate structure 240 and gate ring 340 may be formed by various methods, including: atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, other suitable methods, or combinations thereof. After the main conductive layer is formed, one or more chemical mechanical planarization processes are performed to remove excess material formed on the top surface of the interlayer dielectric layer 640, thereby planarizing the semiconductor structure 100.

[0132] Still refer to Figure 20 and Figures 51 to 54In method 500, in operation 514, contact structures 260 and contact rings 360 are formed above epitaxial structures 250a, 250b, and / or epitaxial rings 350, respectively. Each contact structure 260 and contact ring 360 may include any suitable conductive material, such as cobalt, tungsten, ruthenium, copper, aluminum, titanium, nickel, gold, platinum, palladium, and / or other suitable conductive materials. Method 500 may form a source / drain contact opening (or trench, not shown) in the interlayer dielectric layer 640 via a series of patterning and etching processes, and continue to deposit conductive material in the source / drain contact opening using any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition (PVD), electroplating, and / or other suitable processes.

[0133] Method 500 may perform further manufacturing in operation 514, such as mid-end-of-line (MEOL) processing and end-of-line (BEOL) processing. For example, method 500 may form gate vias connected to gate structure 240 and / or gate ring 340, contact vias connected to contact structure 260 and contact ring 360, and one or more interconnect layers embedded in a dielectric layer, including wiring and vias. The one or more interconnect layers connect the gates, sources, and drains of various transistors, as well as other circuitry in circuit region 200, to form part or all of an integrated circuit. The one or more interconnect layers also form part of the sealing ring region 300. Method 500 may also form one or more passivation layers over the interconnect layers.

[0134] While not intended to be limiting, embodiments of this disclosure provide one or more of the following advantages. For example, embodiments of this disclosure provide a semiconductor structure including a sealing ring region comprising a single type of epitaxial structure. In other words, all epitaxial structures in the sealing ring region are n-type, p-type, or undoped. In one example, all epitaxial structures in the sealing ring region are p-type, and no n-type or undoped epitaxial structures are included. In another example, all epitaxial structures in the sealing ring region are n-type, and no p-type or undoped epitaxial structures are included. The single type of epitaxial ring in the sealing ring region prevents accidental damage that could occur during the formation of multiple epitaxial structures, thereby improving processability and the stability of the sealing ring.

[0135] In another example, embodiments of this disclosure provide a method for forming a sealing ring region comprising a single type of epitaxial structure. In these embodiments, a first epitaxial structure in the sealing ring region and a second epitaxial structure in the circuit region are formed simultaneously, wherein the first and second epitaxial structures comprise the same material (e.g., silicon-germanium doped with p-type dopant). Subsequently, a third epitaxial structure is formed in the circuit region but not in the sealing ring region, wherein the third epitaxial structure comprises a material different from the first material (e.g., silicon doped with n-type dopant). Embodiments of this disclosure can be readily integrated into existing semiconductor manufacturing processes.

[0136] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a circuit region disposed above a substrate and a sealing ring region disposed above the substrate and completely surrounding the circuit region. The circuit region includes a plurality of first fins, a plurality of second fins, a plurality of n-type epitaxial structures above the first fins, and a plurality of p-type epitaxial structures above the second fins. The sealing ring region includes a plurality of fin rings extending completely around the circuit region and a plurality of epitaxial rings disposed above the fin rings and extending parallel to the fin rings. All epitaxial rings above all fin rings in the sealing ring region are p-type epitaxial rings.

[0137] In some embodiments, the semiconductor structure further includes: a plurality of contact rings disposed above and extending parallel to the epitaxial rings. Each contact ring completely surrounds the circuit region. In some examples, the semiconductor structure further includes: a plurality of silicide rings disposed between the epitaxial rings and the contact rings. Each silicide ring completely surrounds the circuit region. In some specific embodiments, a first epitaxial ring of the epitaxial rings is disposed above and extends parallel to a first subset of the fin rings, and a second epitaxial ring of the epitaxial rings is disposed above and extends parallel to a second subset of the fin rings. In some examples, the first and second epitaxial rings are merged together to form a merged epitaxial ring. In some embodiments, the semiconductor structure further includes: a first gate ring disposed above a third subset of the fin rings in a sealing ring region, the third subset of the fin rings being adjacent to the first subset of the fin rings; and a second gate ring disposed above a fourth subset of the fin rings in a sealing ring region, the fourth subset of the fin rings being adjacent to the second subset of the fin rings. In some embodiments, the first epitaxial ring and the second epitaxial ring are disposed between the first gate ring and the second gate ring. In some examples, the semiconductor structure further includes: an outer corner region disposed outside a corner of the sealing ring region, wherein the outer corner region includes a plurality of first straight fin lines; and an inner corner region disposed between a corner of the sealing ring region and a corner of the circuit region. The inner corner region includes a plurality of second straight fin lines. The first straight fin lines and the second straight fin lines are arranged longitudinally in the same direction.

[0138] In another exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate, a circuit region above the substrate, and a sealing ring region above the substrate and completely surrounding the circuit region. The sealing ring region includes: a plurality of first fin rings and a plurality of second fin rings disposed on the substrate and completely surrounding the circuit region, and a plurality of epitaxial rings disposed above the first fin rings. Each epitaxial ring extends the entire length of the first fin rings and completely surrounds the circuit region. All epitaxial rings in the sealing ring region comprise the same material, and the second fin rings do not contain epitaxial rings.

[0139] In some embodiments, each epitaxial ring is formed over at least two fin rings in the first fin ring. In some specific embodiments, the semiconductor structure further includes a plurality of gate rings disposed over the second fin rings. Each gate ring extends the full length of one of the second fin rings and completely surrounds the circuit region. In some embodiments, each gate ring is disposed over at least two of the second fin rings. In some examples, the epitaxial ring and the gate ring are alternately disposed in the sealing ring region. In some examples, the epitaxial ring comprises silicon germanium doped with a p-type dopant.

[0140] In yet another exemplary embodiment, this disclosure relates to a method of forming a semiconductor structure. The method includes: providing a semiconductor substrate including a sealing ring region surrounding a device region; forming a plurality of fins protruding from the semiconductor substrate in the device region and forming a plurality of fin rings in the sealing ring region, wherein each fin ring completely surrounds the device region; recessing the top portions of the fins and fin rings; simultaneously growing a plurality of first epitaxial structures over the recessed fins and growing a plurality of epitaxial rings over the recessed fin rings, wherein the first epitaxial structures and epitaxial rings include a first material; subsequently forming a mask covering the entire sealing ring region and exposing a plurality of portions of the device region; etching the exposed portions of the device region to form a plurality of recesses; and growing a plurality of second epitaxial structures in the recesses, wherein the second epitaxial structures include a second material different from the first material.

[0141] In some embodiments, the semiconductor substrate further includes an outer corner region adjacent to a corner of the sealing ring region and spaced apart from the device region by the sealing ring region. The semiconductor substrate also includes an inner corner region adjacent to a corner of the sealing ring region and spaced apart from the outer corner region by the sealing ring region. The method further includes: simultaneously forming a plurality of straight fin lines in the outer corner region and the inner corner region during the formation of the fins and the fin ring; and simultaneously forming a plurality of straight epitaxial lines over a portion of the straight fin lines in the outer corner region during the formation of the first epitaxial structure and the epitaxial ring, while the inner corner region is covered by a mask layer. In some specific embodiments, the straight epitaxial lines comprise a material identical to the first material. In some examples, the method further includes: simultaneously forming a plurality of contact structures over the straight epitaxial lines in the outer corner region and over the straight fin lines in the inner corner region. In some embodiments, a remaining portion of the straight fin lines in the outer corner region is excluded from forming the straight epitaxial lines, and the method further includes: forming a silicide layer over the straight epitaxial lines in the outer corner region and the remaining portion of the straight fin lines in the outer corner region. In some embodiments, the method further includes forming a plurality of contact structures over a silicide layer in the outer corner region and the inner corner region.

[0142] The foregoing outlines features of numerous embodiments to enable those skilled in the art to better understand this disclosure from various perspectives. Those skilled in the art will understand that other processes and structures can be readily designed or modified based on this disclosure to achieve the same objectives and / or the same advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive concept and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from the inventive concept and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: a circuit region disposed above a substrate, wherein the circuit region comprises a plurality of first fins, a plurality of second fins, a plurality of n-type epitaxial structures above the first fins, and a plurality of p-type epitaxial structures above the second fins; and a seal ring region disposed above the substrate and completely surrounding the circuit region, wherein the seal ring region comprises a plurality of fin rings extending completely around the circuit region, a plurality of epitaxial rings disposed above and extending parallel to the fin rings, wherein all of the epitaxial rings above all of the fin rings in the seal ring region are p-type epitaxial rings.

2. The semiconductor structure of claim 1, further comprising: a plurality of contact rings disposed above and extending parallel to the epitaxial rings, wherein each of the contact rings completely surrounds the circuit region.

3. The semiconductor structure of claim 2, further comprising: a plurality of silicide rings disposed between the epitaxial rings and the contact rings, wherein each of the silicide rings extends completely around the circuit region.

4. The semiconductor structure of claim 1, wherein: a first one of the epitaxial rings is disposed above and extends parallel to a first subset of the fin rings; and a second one of the epitaxial rings is disposed above and extends parallel to a second subset of the fin rings.

5. The semiconductor structure of claim 4, wherein the first epitaxial ring and the second epitaxial ring merge together to form a merged epitaxial ring.

6. The semiconductor structure of claim 4, further comprising: a first gate ring disposed above a third subset of the fin rings in the seal ring region, the third subset of the fin rings being adjacent to the first subset of the fin rings; and a second gate ring disposed above a fourth subset of the fin rings in the seal ring region, the fourth subset of the fin rings being adjacent to the second subset of the fin rings.

7. The semiconductor structure of claim 6, wherein the first epitaxial ring and the second epitaxial ring are disposed between the first gate ring and the second gate ring.

8. The semiconductor structure of claim 1, further comprising: an outer corner region disposed outside a corner of the seal ring region, wherein the outer corner region comprises a plurality of first straight fin lines; and an inner corner region disposed between the corner of the seal ring region and a corner of the circuit region, wherein the inner corner region comprises a plurality of second straight fin lines, and wherein the first straight fin lines and the second straight fin lines are disposed longitudinally in the same direction.

9. A semiconductor structure, comprising: a substrate; a circuit region above the substrate; and a seal ring region above the substrate and completely surrounding the circuit region, wherein the seal ring region comprises: a plurality of first fin rings and a plurality of second fin rings disposed on the substrate and completely surrounding the circuit region; and a plurality of epitaxial rings disposed above and extending parallel to the fin rings, wherein all of the epitaxial rings above all of the fin rings in the seal ring region are p-type epitaxial rings. ​ a plurality of epitaxial rings disposed over the first fin rings, wherein each of the epitaxial rings extends a full length of one of the first fin rings and completely surrounds the circuit region, and wherein all of the epitaxial rings in the seal ring region comprise a same material, wherein the second fin rings do not include epitaxial rings.

10. The semiconductor structure of claim 9, wherein each of the epitaxial rings is formed over at least two of the first fin rings.

11. The semiconductor structure of claim 9, further comprising a plurality of gate rings disposed over the second fin rings, wherein each of the gate rings extends a full length of one of the second fin rings and completely surrounds the circuit region.

12. The semiconductor structure of claim 11, wherein each of the gate rings is disposed over at least two of the second fin rings.

13. The semiconductor structure of claim 11, wherein the epitaxial rings and the gate rings are alternately disposed in the seal ring region.

14. The semiconductor structure of claim 9, wherein the epitaxial rings comprise silicon germanium doped with p-type dopants.

15. A method of forming a semiconductor structure, comprising: providing a semiconductor substrate including a seal ring region surrounding a device region; forming a plurality of fins protruding from the semiconductor substrate in the device region and a plurality of fin rings in the seal ring region, wherein each of the fin rings completely surrounds the device region; recessing top portions of the fins and the fin rings; simultaneously growing a plurality of first epitaxial structures over the recessed fins and a plurality of epitaxial rings over the recessed fin rings, wherein the first epitaxial structures and the epitaxial rings comprise a first material; thereafter, forming a mask covering an entirety of the seal ring region and exposing portions of the device region; etching the exposed portions of the device region to form a plurality of recesses; and growing a plurality of second epitaxial structures in the recesses, wherein the second epitaxial structures comprise a second material different from the first material.

16. The method of claim 15, wherein the semiconductor substrate further comprises an outer corner region adjacent a corner of the seal ring region and spaced apart from the device region by the seal ring region, wherein the semiconductor substrate further comprises an inner corner region adjacent the corner of the seal ring region and spaced apart from the outer corner region by the seal ring region, wherein the method further comprises: simultaneously forming a plurality of straight fin lines in the outer corner region and the inner corner region during forming the fins and the fin rings; and simultaneously forming a plurality of straight epitaxial lines over a portion of the straight fin lines in the outer corner region during forming the first epitaxial structures and the epitaxial rings, while the inner corner region is covered by a mask layer.

17. The method of claim 16, wherein the straight epitaxial lines comprise a same material as the first material.

18. The method of claim 16, further comprising: simultaneously forming a plurality of contact structures over the straight epitaxial lines in the outer corner region and over the straight fin lines in the inner corner region.

19. The method of claim 16, wherein a remaining portion of the straight fin lines in the outer corner region are excluded from forming the straight extension lines; wherein the method further comprises: forming a silicide layer over the straight extension lines in the outer corner region and the remaining portion of the straight fin lines in the outer corner region.

20. The method of claim 19, further comprising: forming contact structures over the silicide layer in the outer corner region and the inner corner region.

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