A multi-layer high-bandwidth memory and a manufacturing method thereof

Abstract

The present invention provides a multi-layer high-bandwidth memory. By adopting a fan-out embedded component packaging method, the high-bandwidth memory and a logic chip are integrated on a single wafer, improving the storage capacity, and the packaging efficiency is improved through a wafer-level bump process. It includes: at least one high-bandwidth memory chip module, each high-bandwidth memory chip module includes N vertically stacked high-bandwidth memory wafers, and a first metal connection layer electrically connected thereto is disposed on the surface; a logic chip, and a second metal connection layer electrically connected thereto is disposed on the surface; a plastic encapsulation layer covering the high-bandwidth memory chip module, the logic chip, the first metal connection layer, and the second metal connection layer, a redistribution layer and a surface passivation layer electrically connected to the first and second metal connection layers are disposed on the first surface thereof, and a carrier layer is disposed on the second surface; and bumps electrically connected to the redistribution layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a multi-layer high-bandwidth memory and a manufacturing method thereof. Background Art

[0002] A high-bandwidth memory (HBM) is a CPU / GPU memory chip, i.e., RAM. The HBM includes a plurality of vertically stacked DDR chips, and the DDR chips are connected to a CPU or GPU or directly to a substrate through a super-fast interconnection method called an interposer, thereby realizing a large-capacity and high-bit-width DDR combined array.

[0003] Generally, the HBM is packaged and assembled with a CPU and a GPU into a specific module and then connected to a circuit board. In practical applications, a logic chip is usually required to be configured in each HBM to execute DDR memory management tasks. In traditional HBM packaging, the stacked DDR chips and the logic chip are usually separately packaged and then attached to the substrate, and the overall packaging efficiency is relatively low. Summary of the Invention

[0004] In view of some or all of the problems in the prior art, in order to improve the packaging efficiency while ensuring the function, on the one hand, the present invention provides a multi-layer high-bandwidth memory, which integrates a high-bandwidth memory and a logic chip on a single wafer. The multi-layer high-bandwidth memory includes:

[0005] At least one high-bandwidth memory chip module, including N vertically stacked high-bandwidth memory wafers;

[0006] A logic chip;

[0007] A first metal connection layer, disposed on the surface of the high-bandwidth memory chip module and electrically connected to the high-bandwidth memory chip module;

[0008] A second metal connection layer, disposed on the surface of the logic chip and electrically connected to the logic chip;

[0009] A first dielectric layer, covering the surfaces and gaps of the first metal connection layer and the second metal connection layer, but exposing at least one external pad of the first metal connection layer and the second metal connection layer;

[0010] A second dielectric layer, disposed below the first metal connection layer and the second metal connection layer;

[0011] A plastic encapsulation layer, covering the high-bandwidth memory chip module, the logic chip, the first metal connection layer, the first dielectric layer, the second metal connection layer, and the second dielectric layer;

[0012] A surface passivation layer is disposed on the first surface of the encapsulation layer, but at least one external pad of the first metal connection layer and the second metal connection layer is exposed;

[0013] A redistribution layer is disposed on the surface of the surface passivation layer and is electrically connected to the first metal connection layer and the second metal connection layer;

[0014] A bump is electrically connected to the redistribution layer; and

[0015] A carrier layer is disposed on the second surface of the encapsulation layer.

[0016] Further, the high-bandwidth memory wafers in each high-bandwidth memory chip module are connected by micro-bumps.

[0017] Further, the number of high-bandwidth memory wafers in each high-bandwidth memory chip module is the same or different.

[0018] Further, the number of high-bandwidth memory wafers in each high-bandwidth memory chip module is 1 to 4.

[0019] Further, the multi-layer high-bandwidth memory structure includes a plurality of the logic chips.

[0020] Further, the high-bandwidth memory chip module and the logic chips are arranged in an interleaved manner.

[0021] Further, the first metal connection layer realizes the fan-out function for the pins of the high-bandwidth memory chip module.

[0022] Further, the second metal connection layer realizes the fan-out function for the pins of the logic chips.

[0023] On the other hand, the present invention provides a manufacturing method of a multi-layer high-bandwidth memory as described above, including:

[0024] Forming a high-bandwidth memory chip module;

[0025] Covering a temporary bonding layer on a carrier wafer, and forming a first metal connection layer, a first dielectric layer, a second metal connection layer and a second dielectric layer thereon;

[0026] Mounting the high-bandwidth memory chip module and the logic chips to the first metal connection layer and the second metal connection layer respectively;

[0027] Using an encapsulation material to cover the high-bandwidth memory chip module, the logic chips, the first metal connection layer, the first dielectric layer, the second metal connection layer and the second dielectric layer to form an encapsulation layer;

[0028] Forming a carrier wafer on the surface of the encapsulation layer;

[0029] Remove the temporary bonding layer and the carrier wafer;

[0030] Form a surface passivation layer on the second surface of the encapsulation layer, and remove a part of the surface passivation layer to expose at least one external pad of the first metal connection layer and the second metal connection layer;

[0031] Form a redistribution layer on the surface passivation layer to electrically connect it to the first metal connection layer and the second metal connection layer;

[0032] Fabricate bumps on the external pads of one or more of the redistribution layers; and

[0033] Thin the carrier wafer.

[0034] Further, the manufacturing method further includes power-on testing of the multi-layer high-bandwidth memory.

[0035] A multi-layer high-bandwidth memory and a manufacturing method thereof provided by the present invention innovatively adopt a fan-out embedded component packaging method (Fan-out ECP) to integrate a high-bandwidth memory (HBM) and a logic chip on a single wafer, effectively improving the storage capacity of the HBM. In addition, its use of the wafer-level bumping process has greatly improved the packaging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To further clarify the above and other advantages and features of the embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0037] Figure 1 A cross-sectional schematic diagram of a multi-layer high-bandwidth memory showing an embodiment of the present invention;

[0038] Figure 2 A top-view schematic diagram of a multi-layer high-bandwidth memory showing an embodiment of the present invention;

[0039] Figures 3A to 3G A cross-sectional schematic diagram showing the process of forming a multi-layer high-bandwidth memory according to an embodiment of the present invention; and

[0040] Figure 4 A flowchart showing the process of forming a three-dimensional stacked package structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] In the following description, the present invention is described with reference to the embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in conjunction with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for purposes of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0042] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment.

[0043] It should be noted that the embodiments of the present invention describe the process steps in a specific order. However, this is only for the purpose of explaining the specific embodiment and does not limit the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.

[0044] Conventional High Bandwidth Memory (HBM) typically involves individually packaging HBM chips and logic chips and then attaching them to a substrate. When a large number of HBM chips are required, this packaging form has low efficiency. To improve packaging efficiency while ensuring or even increasing the number of memory chips to achieve higher unit storage capacity, the present invention provides a multi-layer high bandwidth memory and its manufacturing method. Using the form of Fan-out Embedded Component Packaging (Fan-out ECP), the HBM chip and the logic chip can be integrated together simultaneously. On the one hand, it improves packaging efficiency while achieving the same function, and on the other hand, it enables the mass production of the multi-layer high bandwidth memory.

[0045] The solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0046] Figure 1 A cross-sectional schematic diagram of a multi-layer high bandwidth memory showing an embodiment of the present invention is as follows Figure 1As shown, a multi-layer high-bandwidth memory includes a high-bandwidth memory chip module 101 and a logic chip 102, and the high-bandwidth memory chip module 101 and the logic chip 102 are integrated on a single wafer. In an embodiment of the present invention, the multi-layer high-bandwidth memory includes K high-bandwidth memory chip modules and L logic chips, where both K and L are natural numbers. Figure 2 The top view schematic diagram of the multi-layer high-bandwidth memory showing an embodiment of the present invention is as Figure 2 shown, the K high-bandwidth memory chip modules and the L logic chips are staggered and distributed on the wafer, that is, on the carrier layer 105.

[0047] As Figure 1 shown, the high-bandwidth memory chip module 101 and the logic chip 102 first respectively implement the fan-out function for the pins through the first metal connection layer 111 and the second metal connection layer 121, and then further implement electrical and / or signal interconnection through the redistribution layer 131, and finally implement electrical connection with external components or structures through the bumps 132.

[0048] In an embodiment of the present invention, any one of the high-bandwidth memory chip modules 101 includes N vertically stacked high-bandwidth memory wafers, where N is a natural number. In an embodiment of the present invention, the N high-bandwidth memory wafers are stacked by a vertical 3D TSV stacking process. A high-bandwidth memory wafer can be regarded as a storage area, and each storage area is connected by micro-bumps (uBump). In an embodiment of the present invention, the number of high-bandwidth memory wafers included in different high-bandwidth memory chip modules may be the same or different, but preferably, the number of high-bandwidth memory wafers included in each high-bandwidth memory chip module is 1 to 4, and the value range of N is 1 to 4.

[0049] As Figure 1 shown, the surface of the high-bandwidth memory chip module 101 is provided with a first metal connection layer 111, which is electrically connected to the high-bandwidth memory chip module 101 to implement the fan-out function for the pins of the high-bandwidth memory chip module 101. In an embodiment of the present invention, the material of the first metal connection layer 111 may be copper metal, aluminum metal, tungsten metal, etc. The first metal connection layer 111 is formed on the surface of the second dielectric layer 162. The surface of the first metal connection layer 111 is also covered with a first dielectric layer 161, and the first dielectric layer 161 covers the surface and gaps of the first metal connection layer 111, but exposes at least one external pad of the first metal connection layer, playing an insulating and protective role. In an embodiment of the present invention, the materials of the first dielectric layer 161 and the second dielectric layer 162 may be organic materials such as resin and PI, or inorganic insulating materials such as silicon oxide and silicon nitride.

[0050] The logic chip 102 is mainly used to implement control functions such as logical operations on the high - bandwidth memory chip module. A second metal connection layer 121 is provided on the surface of the logic chip 102, which is electrically connected to the logic chip 102 to achieve the fan - out function of the pins of the logic chip 102. In an embodiment of the present invention, the material of the second metal connection layer 121 can be copper metal, aluminum metal, tungsten metal, etc. The second metal connection layer 121 is formed on the surface of the second dielectric layer 162. The surface of the second metal connection layer 121 is also covered with a first dielectric layer 161, which covers the surface and gaps of the second metal connection layer 121, but exposes at least one external pad of the second metal connection layer, playing an insulating and protective role.

[0051] As Figure 1 shown, the high - bandwidth memory chip module 101, the logic chip 102, the first metal connection layer 111, the first dielectric layer 161, the second metal connection layer 121, and the second dielectric layer 162 are encapsulated in the plastic package layer 104. In an embodiment of the present invention, the plastic package layer 104 is made of resin material.

[0052] The redistribution layer 131 is formed on the first surface of the plastic package layer 104, and is electrically connected to the first metal connection layer 111 and the second metal connection layer 121. The material of the redistribution layer 131 can be copper metal, aluminum metal, tungsten metal, etc. In an embodiment of the present invention, the redistribution layer 131 can have one or more layers, and the outermost layer can also be provided with pads for connecting to external chips, chip sets, or circuits.

[0053] As Figure 1 shown, a surface passivation layer 133 is also provided on the first surface of the plastic package layer 104, which covers the first surface of the plastic package layer 104, but exposes at least one external pad of the first metal connection layer 111 and the second metal connection layer 121, so that the redistribution layer 131 can be electrically connected to the first metal connection layer and the second metal connection layer.

[0054] As Figure 1 shown, a carrier layer 105 is provided on the second surface of the plastic package layer 104, and the thickness of the carrier layer 105 can be set according to actual requirements. In an embodiment of the present invention, the carrier layer 105 is obtained by thinning the wafer.

[0055] The bumps 132 are formed on the external pads of the redistribution layer 131.

[0056] It should be understood that, in order to achieve the synchronous integration of multiple functions, other types of chips may also be added according to actual requirements, and the packaging of the other types of chips is the same as that of the logic chip.

[0057] Next, in conjunction with Figures 3A to 3G and Figure 4 to describe in detail the process of forming such a multi-layer high-bandwidth memory. Figures 3A to 3G FIG. shows a process cross-sectional schematic diagram of forming a multi-layer high-bandwidth memory according to an embodiment of the present invention; Figure 4 FIG. shows a flowchart of forming a multi-layer high-bandwidth memory according to an embodiment of the present invention. As shown in the figure, a manufacturing method of a multi-layer high-bandwidth memory as described above includes:

[0058] First, in step 401, as Figure 3A shown, a high-bandwidth memory chip module 101 is formed. In an embodiment of the present invention, a plurality of HBM wafers 1011 are vertically stacked by 3D TSV, and each HBM wafer is connected by uBump 1012;

[0059] Next, in step 402, as Figure 3B shown, a fan-out structure is formed. A temporary bonding layer 002 is covered on a carrier wafer 001, where the carrier wafer 001 can be a wafer, glass or other carrier wafer materials; the temporary bonding layer 002 is a detachable bonding material such as heating and light irradiation. According to the preset positions of the high-bandwidth memory chip module and the logic chip on the temporary bonding layer, a second dielectric layer 162 is formed. The material of the second dielectric layer 162 can be an organic material such as resin and PI, or an inorganic insulating material such as silicon oxide and silicon nitride. One or more layers of conductive materials are respectively formed on the second dielectric layer 162, and the non-conductive regions are removed by photolithography and etching techniques to form a first metal connection layer 111 and a second metal connection layer 121. A first dielectric layer 161 is formed on the first metal connection layer 111 and the second metal connection layer 121. Part of the first dielectric layer 161 is removed by photolithography and etching techniques to expose the external pads of at least one of the first metal connection layer 111 and the second metal connection layer 121. The high-bandwidth memory chip module 101 and the logic chip 102 are respectively mounted on the preset external pads of the first metal connection layer 111 and the second metal connection layer 121;

[0060] Next, in step 403, as Figure 3C shown, a molding layer is formed. The molding layer 104 covers the high-bandwidth memory chip module 101, the logic chip 102, the first metal connection layer 111, the first dielectric layer 161, the second metal connection layer 121, and the second dielectric layer 162;

[0061] Next, in step 404, asFigure 3D As shown, a carrier layer is formed. On the second surface of the encapsulation layer 104, that is, on the side surface away from the temporary bonding layer 002, a carrier wafer 105 is loaded. The carrier wafer 105 can be a wafer, glass, or other wafer materials;

[0062] Next, in step 405, as Figure 3E shown, the wafer and the temporary bonding layer are removed. In a specific embodiment of the present invention, according to the characteristics of the temporary bonding layer 002, methods such as thermal debonding and laser irradiation debonding can be used to achieve this, and a cleaning process can be further used to completely remove the temporary bonding layer 002;

[0063] Next, in step 406, as Figure 3F shown, a redistribution structure is formed. A surface passivation layer 133 is formed on the second surface of the encapsulation layer 104. Part of the surface passivation layer 133 is removed to expose at least one external pad of the first metal connection layer 111 and the second metal connection layer 121. A redistribution layer 131 is formed on the surface passivation layer 133 to be electrically connected to the first metal connection layer 111 and the second metal connection layer 121. Bumps 132 are fabricated on the external pads of one or more of the redistribution layers; In an embodiment of the present invention, after the redistribution structure is completed, a connection structure power-on test can also be performed; and

[0064] Finally, in step 407, as Figure 3G shown, back thinning is performed. According to requirements, the carrier wafer 105 is thinned to a certain thickness to form the final product.

[0065] A multi-layer high-bandwidth memory and its manufacturing method provided by the present invention innovatively adopt a fan-out embedded component packaging method (Fan-out ECP) to integrate a high-bandwidth memory (HBM) and a logic chip on a single wafer, effectively improving the storage capacity of the HBM. In addition, its use of the wafer-level bumping process has greatly improved the packaging efficiency.

[0066] Although the above describes the embodiments of the present invention, it should be understood that they are presented only as examples and not as limitations. It will be obvious to those skilled in the relevant art that various combinations, variations, and changes can be made to them without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-disclosed exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A multi-layer high-bandwidth memory, characterized in that, it includes: at least one high-bandwidth memory chip module, each of the high-bandwidth memory chip modules includes N vertically stacked high-bandwidth memory wafers, where N is a natural number; at least one logic chip, which is configured to control the high-bandwidth memory chip module, and the high-bandwidth memory chip module and the logic chip are arranged in an interleaved manner; a first metal connection layer, disposed on the surface of the high-bandwidth memory chip module and electrically connected to the high-bandwidth memory chip module; a second metal connection layer, disposed on the surface of the logic chip and electrically connected to the logic chip; a first dielectric layer, covering the surfaces and gaps of the first metal connection layer and the second metal connection layer, but exposing at least one external pad of the first metal connection layer and the second metal connection layer; a second dielectric layer, disposed below the first metal connection layer and the second metal connection layer; a plastic encapsulation layer, encapsulating the high-bandwidth memory chip module, the logic chip, the first metal connection layer, the first dielectric layer, the second metal connection layer, and the second dielectric layer; a surface passivation layer, disposed on the first surface of the plastic encapsulation layer, but exposing at least one external pad of the first metal connection layer and the second metal connection layer; a redistribution layer, disposed on the surface of the surface passivation layer and electrically connected to the first metal connection layer and the second metal connection layer; bumps, electrically connected to the redistribution layer; and a carrier layer, disposed on the second surface of the plastic encapsulation layer.

2. The multi-layer high-bandwidth memory according to claim 1, characterized in that, the high-bandwidth memory wafers in each of the high-bandwidth memory chip modules are connected by micro-bumps.

3. The multi-layer high-bandwidth memory according to claim 1, characterized in that, the number of high-bandwidth memory wafers in each of the high-bandwidth memory chip modules is the same or different.

4. The multi-layer high-bandwidth memory according to claim 1, characterized in that, the number of high-bandwidth memory wafers in each of the high-bandwidth memory chip modules is 1 to 4.

5. The multi-layer high-bandwidth memory according to claim 1, characterized in that, the first metal connection layer realizes the fan-out function for the pins of the high-bandwidth memory chip module.

6. The multi-layer high-bandwidth memory according to claim 1, characterized in that, the second metal connection layer realizes the fan-out function for the pins of the logic chip.

7. A manufacturing method of the multi-layer high-bandwidth memory according to any one of claims 1 to 6, characterized in that, it includes the steps of: forming a high-bandwidth memory chip module; covering a temporary bonding layer on a carrier wafer, and forming a first metal connection layer, a first dielectric layer, a second metal connection layer, and a second dielectric layer thereon; mounting the high-bandwidth memory chip module and the logic chip to the first metal connection layer and the second metal connection layer respectively; using a plastic encapsulation material to encapsulate the high-bandwidth memory chip module, the logic chip, the first metal connection layer, the first dielectric layer, the second metal connection layer, and the second dielectric layer to form a plastic encapsulation layer; forming a carrier wafer for carrying on the second surface of the plastic encapsulation layer; removing the temporary bonding layer and the carrier wafer; Form a surface passivation layer on the first surface of the encapsulation layer, and remove a part of the surface passivation layer to expose at least one external pad of the first metal connection layer and the second metal connection layer; Form a redistribution layer on the surface passivation layer to electrically connect it to the first metal connection layer and the second metal connection layer; Fabricate bumps on the external pads of one or more of the redistribution layers; and Thin the carrier wafer.

8. The manufacturing method according to claim 7, wherein, it further includes the step of: performing a power-on test on the multi-layer high-bandwidth memory.

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