Method of forming a semiconductor structure

Abstract

A semiconductor structure includes a substrate having an isolation region and an active region, and a word line structure. The word line structure includes a first portion and a second portion. The first portion is formed within the isolation region of the substrate, wherein the isolation region surrounds the first portion. The second portion is formed within the active region of the substrate, wherein the width of the second portion is greater than the width of the first portion. Each portion of the word line structure has a different width depending on its location. The portion of the word line structure located in the isolation region has a smaller width, thereby increasing the distance between the word line structure and adjacent elements, such that the isolation region provides better electrical isolation and reduces the occurrence of leakage in the semiconductor structure. Meanwhile, the portion of the word line structure located in the active region retains a larger width to provide sufficient channel area to maintain the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor structure and a method of forming the same, and more particularly to a word line structure of a dynamic random access memory (DRAM). BACKGROUND

[0002] With the advancement of technology, dynamic random access memory (DRAM) has become more highly integrated, and the performance of DRAM has been improved by the reduction of the pitch of semiconductor structures within the DRAM. Due to the reduction in size, in addition to increasing the difficulty of the process, each element within the semiconductor structure is prone to leakage due to being too close in proximity.

[0003] Therefore, how to reduce the leakage phenomenon to improve the process yield of the semiconductor structure becomes an important issue. SUMMARY

[0004] According to some embodiments of the present disclosure, a semiconductor structure includes a substrate having an isolation region and an active region, and a word line structure. The word line structure includes a first portion and a second portion. The first portion is formed within the isolation region of the substrate, wherein the isolation region surrounds the first portion. The second portion is formed within the active region of the substrate, wherein a width of the second portion is greater than a width of the first portion.

[0005] In some embodiments, the width of the second portion of the semiconductor structure is about 1 nm to about 3 nm greater than the width of the first portion.

[0006] According to some embodiments of the present disclosure, a semiconductor structure includes a substrate having an isolation region and an active region, and a plurality of word line structures, wherein each word line structure extends through the isolation region and the active region. A lateral distance between adjacent word line structures located within the isolation region is a first length, and a lateral distance between adjacent word line structures located within the active region is a second length, wherein the first length is greater than the second length.

[0007] In some embodiments, the first length of the semiconductor structure is about 1 nm to about 3 nm greater than the second length.

[0008] According to some embodiments of the present invention, a method of forming a semiconductor structure includes receiving a substrate, forming an isolation region and an active region within the substrate, and forming a trench within the substrate, wherein the trench is linear in shape and extends through the isolation region and the active region of the substrate. The trench includes a first portion of the trench located within the isolation region and a second portion of the trench located within the active region. The method of forming the semiconductor structure also includes increasing the width of the second portion of the trench after forming the trench. The method of forming the semiconductor structure also includes forming a dielectric layer on the inner surface of the trench, forming a conductive layer within the trench and having the dielectric layer cover the conductive layer, and forming a capping layer within the trench and stacking it on the conductive layer.

[0009] In some embodiments, the increase in the width of the second portion of the trench in the method of forming the semiconductor structure is from about 1 nanometer to about 3 nanometers.

[0010] In some embodiments, increasing the width of the second portion of the trench includes using an etching process, wherein the etch selectivity ratio of the material in the active region to the material in the isolation region is at least greater than about 5.

[0011] In some embodiments, the etching process includes the use of ammonia.

[0012] In some embodiments, the etching process includes the use of nitrogen trifluoride.

[0013] In some embodiments, the etching process includes using plasma to generate an etchant in a free radical state.

[0014] This invention relates to a semiconductor structure and a method for forming it. Each portion of the word line structure has a different width depending on its location. The portion of the word line structure located in the isolation region has a smaller width, thereby increasing the distance between the word line structure and adjacent components. This allows the isolation region to provide better electrical barrier, reducing leakage current in the semiconductor structure. Simultaneously, the portion of the word line structure located in the active region maintains a larger width to provide sufficient channel area and maintain the performance of the semiconductor structure. Attached Figure Description

[0015] The following embodiments are read in conjunction with the accompanying drawings for a clear understanding of the present invention. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0016] Figure 1 The semiconductor structure configuration is illustrated in some embodiments of the present invention.

[0017] Figure 2 Semiconductor structures are illustrated along some embodiments of the present invention. Figure 1 Cross-sectional view of section AA.

[0018] Figure 3 A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0019] Figure 4A A configuration view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0020] Figure 4B A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application. Figure 4A A cross-sectional view along section line A-A.

[0021] Figure 5 A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0022] Figure 6A A configuration view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0023] Figure 6B A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application. Figure 6A A cross-sectional view along section line A-A.

[0024] Figure 7A A configuration view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0025] Figure 7B A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application. Figure 7A A cross-sectional view along section line A-A.

[0026] Figure 8 A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0027] Figure 9 A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0028] Figure 10 A cross-sectional view of one of the process stages of forming a semiconductor structure is depicted in accordance with some embodiments of the present application.

[0029]

SYMBOL DESCRIPTION

[0030] 100: semiconductor structure

[0031] 110: word line structure

[0032] 110A: first portion

[0033] 110B: second portion

[0034] 112: dielectric layer

[0035] 114: conductive layer

[0036] 116: capping layer

[0037] 120: bit line structure

[0038] 130: active region

[0039] 132: source / drain region

[0040] 140: isolation region

[0041] 150: direct contact

[0042] 160: contact

[0043] 162: first contact plug

[0044] 164: second contact plug

[0045] 200: substrate

[0046] 220: first interlayer dielectric layer

[0047] 240: second interlayer dielectric layer

[0048] 600: trench

[0049] 600A: first portion trench

[0050] 600B: second portion trench

[0051] 600S: inner surface

[0052] 620: patterned mask

[0053] 700: portion

[0054] 700L: length

[0055] A-A: line

[0056] D1: first direction

[0057] D2: second direction

[0058] D3: third direction

[0059] L1: first length

[0060] L2: second length

[0061] L3: third length

[0062] L4: fourth length

[0063] W1: first width

[0064] W2: second width

[0065] W3: third width

[0066] W4: fourth width

[0067] S: distance

[0068] θ: angle DETAILED DESCRIPTION

[0069] When an element as a "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0070] In this disclosure, the words "first", "second", "third", etc. are used to describe various elements, components, regions, layers and / or sections. However, these elements, components, regions, layers and / or sections should not be limited by these terms. These words are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section can also be referred to as a second element, component, region, layer and / or section without departing from the spirit of the present disclosure.

[0071] As used herein, the term "about" is used to indicate that a value or range is approximately that which is recited. Generally, the term "about" is used herein to modify that term it precedes, such that the term "about" includes a range of values that are near to the recited value or range, for example, within 20 percent, more preferably within 10 percent, and even more preferably within 5 percent of the recited value or range. Unless otherwise specified, all values recited herein are approximate, i.e., they are subject to the error or range of error that would be expected by one of ordinary skill in the art in the relevant field.

[0072] Referring now to Figure 1 , Figure 1 A configuration of a semiconductor structure 100 is depicted according to some embodiments of the present disclosure. The semiconductor structure 100 can include a plurality of word line structures 110 extending along a first direction D1, and adjacent word line structures 110 are spaced apart at equal distances along a second direction D2. A plurality of bit line structures 120 extend along the second direction D2 and are arranged above the word line structures 110 in a staggered manner. Similarly, adjacent bit line structures 120 are spaced apart at equal distances along the first direction D1 and are parallel to each other.

[0073] The semiconductor structure 100 includes active regions 130 and isolation regions 140, where the active regions 130 have a short axis and a long axis. In some embodiments, the long axis of the active regions 130 extends along the third direction D3, where the third direction D3 is at an angle Θ with respect to the second direction D2. The regions outside of the active regions 130 are the isolation regions 140.

[0074] The bit line structure 120 can be connected to the active regions 130 by direct contacts 150. Each active region 130 can be electrically connected to one direct contact 150. In addition, a plurality of contacts 160 can be formed at the ends of the long axis of the active regions 130 and between each pair of adjacent word line structures 110. In some embodiments, the contacts 160 are spaced apart from each other along the first direction Dl. The contacts 160 can electrically connect the lower electrodes of storage nodes / capacitors (not shown) to the corresponding active regions 130. In the embodiment shown, a single active region 130 can be electrically connected to two contacts 160. Figure 1

[0075] According to some embodiments of the present disclosure, each word line structure 110 of the semiconductor structure 100 is linear in shape and extends along the first direction Dl through the isolation regions 140 and the active regions 130. Thus, each word line structure 110 can include two portions, a first portion 110A of the word line structure 110 formed within the isolation regions 140 and a second portion 110B of the word line structure 110 formed within the active regions 130. In the embodiment shown, the first portion 110A and the second portion 110B of each word line structure 110 can have different widths, where the width of each portion of the word line structure 110 depends on the region in which the portion of the word line structure 110 is formed. Figure 1

[0076] In detail, the word line structure 110 formed within the isolation regions 140 (i.e., the first portion 110A of the word line structure 110) has a first width Wl and the word line structure 110 formed within the active regions 130 (i.e., the second portion 110B of the word line structure 110) has a second width W2, where the first width Wl is different from the second width W2. In some embodiments, the second width W2 is greater than the first width Wl and the second width W2 is about 1.0 nm to about 3.0 nm wider than the first width Wl, such as 1.0, 1.5, 2.0, 2.5, or 3.0 nm. In some embodiments, the second width W2 can be about 2.0 nm wider than the first width Wl.

[0077] ​​From another perspective, when the various portions of each character line structure 110 have different widths, the distances of each portion of the character line structure 110 from adjacent elements (e.g., another character line structure 110) also differ. Figure 1 As shown, the lateral distance (e.g., the distance along the second direction D2) between adjacent first portions 110A (i.e., two adjacent character line structures 110 located in the isolation region 140) is a first length L1, and the lateral distance between adjacent second portions 110B (i.e., two adjacent character line structures 110 located in the same active region 130) within the same active region 130 is a second length L2. The first length L1 differs from the second length L2 because the portions in each character line structure 110 have different widths. In some embodiments, the first length L1 is greater than the second length L2, and the first length L1 is greater than the second length L2 by about 1.0 nanometers to about 3.0 nanometers, for example, 1.0, 1.5, 2.0, 2.5, or 3.0 nanometers. In some embodiments, the first length L1 may be greater than the second length L2 by about 2.0 nanometers.

[0078] Similarly, as Figure 1 As shown, the lateral distance (e.g., the distance along the second direction D2) between the first portion 110A (i.e., the character line structure 110 located in the isolation region 140) and the second portion 110B (i.e., the character line structure 110 located in the active region 130) is a third length L3, and the lateral distance between adjacent second portions 110B (i.e., two adjacent character line structures 110 located in different active regions 130) within different active regions 130 is a fourth length L4, wherein the fourth length L4 is substantially equal to the second length L2. The third length L3 is greater than the fourth length L4 because the portions in each character line structure 110 have different widths, and the third length L3 is greater than the fourth length L4 by approximately 0.5 nanometers to approximately 1.5 nanometers. In some embodiments, the third length L3 may be greater than the fourth length L4 by approximately 1.0 nanometer. In summary, in the embodiment shown in the first figure, the first length L1 > the third length L3 > the second length L2 = the fourth length L4.

[0079] The first portion 110A and the second portion 110B of the character line structure 110 may have different widths, resulting in differences in the distance between the first portion 110A and the second portion 110B from the surrounding components. This may further affect the electrical barrier effect between the character line structure 110 and the surrounding components. This is because when the isolation region 140 includes a dielectric material, the spacing length between the character line structure 110 and the surrounding components may be positively correlated with the thickness of the isolation region 140 between the character line structure 110 and the surrounding components, thereby affecting the electrical barrier effect between the character line structure 110 and the surrounding components. Therefore, for the first portion 110A (i.e., the character line structure 110 located in the isolation region 140), the smaller width of the first portion 110A results in a larger spacing length with the surrounding components and increases the thickness of the isolation region 140 between the first portion 110A and the surrounding components, thereby improving the electrical barrier effect of the isolation region.

[0080] Please see Figure 2 , Figure 2 Semiconductor structure 100 is illustrated according to some embodiments of the present invention. Figure 1 A cross-sectional view of section AA. Specifically, section AA is parallel to the third direction D3. Semiconductor structure 100 includes a substrate 200, wherein the substrate 200 has an active region 130 and a plurality of isolation regions 140 separating the active region 130. The substrate 200 may be further subjected to an ion implantation process to dope N-type or P-type dopants into the substrate 200. In some embodiments, source / drain regions 132 can be formed in the active region 130 of the substrate 200 by doping with N-type or P-type dopants.

[0081] like Figure 2 As shown, a plurality of word line structures 110 of semiconductor structure 100 are formed in substrate 200, wherein word line structures 110 have dielectric layer 112, conductive layer 114 and capping layer 116.

[0082] exist Figure 2 The cross-sectional view shown depicts three character line structures 110, one of which is located in the first portion 110A of the isolation region 140, and the other two character line structures 110 are located in the second portion 110B of the active region 130. Figure 2As shown, the first portion 110A has a third width W3 and the second portion 110B has a fourth width W4, where the third width W3 is substantially similar to the first width W1 and the fourth width W4 is substantially similar to the second width W2. Further, the first width W1 / second width W2 (along the second direction D2) is multiplied by cos θ to the third width W3 / fourth width W4 (along the third direction D3). Thus, the relationship of the first width W1 and the second width W2 can be applied to the third width W3 and the fourth width W4. For example, in embodiments where the second width W2 is greater than the first width W1, the third width W3 can maintain a relationship of being greater than the fourth width W4, and the amount of width increase can be scaled by the aforementioned cos θ.

[0083] It should be understood that, Figure 2 The number of word line structures 110 (three) is drawn as an example and is not intended to be limiting. In practice, the number of word line structures 110 can be adjusted based on product design and process conditions.

[0084] Continuing to refer to Figure 2 The first ILD 220 and the second ILD 240 can be sequentially disposed above the substrate 200. In some embodiments, the bit line structure 120 is disposed in the second ILD 240, and the direct contact 150 is disposed in the first ILD 220, and the bit line structure 120 is electrically connected to the direct contact 150. Thus, the bit line structure 120 can be electrically connected to the active region 130 of the substrate 200 through the direct contact 150.

[0085] The contact 160 of the semiconductor structure 100 can include a first contact plug 162 and a second contact plug 164, where the second contact plug 164 is disposed above the first contact plug 162 and is electrically connected to each other. The second contact plug 164 can electrically connect a lower electrode of a storage node / capacitor (not shown) to a corresponding active region 130 through the first contact plug 162. In some embodiments, the first contact plug 162 is a buried contact. In some embodiments, the second contact plug 164 is a landing pad.

[0086] In Figure 2In this configuration, the first portion 110A and the first contact plug 162 are separated by a distance S. Because the first portion 110A has a relatively small third width W3, the thickness of the material in the isolation region 140 between the first portion 110A and the first contact plug 162 (essentially equal to the distance S) provides sufficient electrical barrier to prevent leakage between the first portion 110A and the first contact plug 162. Furthermore, the relatively small third width W3 of the first portion 110A also provides greater tolerance in subsequent processes, such as for alignment errors in the first contact plug 162. In some embodiments, the distance S between the first portion 110A and the first contact plug 162 is at least greater than about 2 nanometers.

[0087] Figure 1 and Figure 2 The structures, shapes, or configurations shown in the icons are for illustrative purposes only and should not be construed as limiting the invention.

[0088] Figure 3 , Figure 4B , Figure 5 , Figure 6B , Figure 7B ,and Figure 8 to Figure 10 Cross-sectional views of various process stages in forming the semiconductor structure 100 are illustrated according to some embodiments of the present invention, and Figure 4A , Figure 6A ,and Figure 7A The present invention illustrates the configuration of various process stages for forming the semiconductor structure 100 according to some embodiments thereof.

[0089] It should be noted that when Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B ,and Figure 8 to Figure 10 When illustrated or described as a series of operations or events, the order in which these operations or events are described should not be limited. For example, some operations or events may be performed in a different order than in this invention, some operations or events may occur simultaneously, some operations or events may be unnecessary, and / or some operations or events may be repeated. Furthermore, the actual process may require additional operational steps before, during, or after the formation of the semiconductor structure 100 to fully form the semiconductor structure 100. Therefore, this invention may briefly describe some of these additional operational steps. Moreover, unless otherwise stated, Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B , Figure 7A ,Figure 7B , and Figure 8 to Figure 10 The same description applies directly to the other figures.

[0090] See Figure 3 , Figure 3 A cross-sectional view of one of the process stages of forming a semiconductor structure 100 is depicted in accordance with some embodiments of the present application. First, a substrate 200 is received. The substrate 200 is of a semiconductor material, which can include silicon, such as crystalline silicon, polysilicon, or amorphous silicon. The substrate 200 can include elemental semiconductors, such as germanium (Ge). The substrate 200 can include alloy semiconductors, such as silicon germanium (SiGe), silicon phosphorus carbide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or other suitable materials. The substrate 200 can include compound semiconductors, such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), or other suitable materials.

[0091] In addition, the substrate 200 can be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The semiconductor-on-insulator substrate can be fabricated by separation by implantation of oxygen (SIMOX) techniques, wafer bonding techniques, other suitable techniques, or a combination thereof.

[0092] See Figure 4A and Figure 4B , Figure 4A A configuration view of one of the process stages of forming a semiconductor structure 100 is depicted in accordance with some embodiments of the present application, Figure 4B A cross-sectional view of one of the process stages of forming a semiconductor structure 100 is depicted in accordance with some embodiments of the present application, Figure 4A along section line A-A. As Figure 4A and Figure 4BAs shown, isolation regions 140 are formed within substrate 200. The material of isolation regions 140 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. Isolation regions 140 can be a single layer or a multi-layer structure. For example, isolation regions 140 can include silicon oxide and silicon nitride. In some embodiments, isolation regions 140 can be formed by a shallow trench isolation (STI) process. After isolation regions 140 are formed, the semiconductor material located around isolation regions 140 and extending out of substrate 200 can be active regions 130, where isolation regions 140 separate active regions 130.

[0093] Referring to Figure 5 , Figure 5 According to some embodiments of the present disclosure, a cross-sectional view of one of the process stages of forming semiconductor structure 100 is shown. An ion implantation process can be further performed on substrate 200 to dope N-type or P-type dopants into substrate 200. In some embodiments, source / drain regions 132 can be formed in active regions 130 by doping N-type or P-type dopants into substrate 200. N-type dopants can include phosphorus or arsenic. P-type dopants can include boron, or boron fluoride.

[0094] Referring to Figure 6A and Figure 6B , Figure 6A According to some embodiments of the present disclosure, a configuration view of one of the process stages of forming semiconductor structure 100 is shown, Figure 6B According to some embodiments of the present disclosure, a cross-sectional view of one of the process stages of forming semiconductor structure 100 is shown, Figure 6A along section line A-A. As shown, Figure 6A and Figure 6B Trenches 600 are formed within substrate 200. Trenches 600 are linear in shape and extend through isolation regions 140 and active regions 130. Thus, each trench 600 can include a first portion trench 600A and a second portion trench 600B: the first portion trench 600A is a trench 600 located at isolation regions 140, and the second portion trench 600B is a trench 600 located at active regions 130.

[0095] In some embodiments, the first trench 600A and the second trench 600B are substantially the same, differing only in the regions they occupy (isolation region 140 and active region 130). Therefore, the first trench 600A and the second trench 600B may have the same width, for example, a first width W1. In other words, Figure 6A and Figure 6B The groove 600 shown may have a uniform first width W1.

[0096] exist Figure 6B In the illustrated embodiment, the formation of the trench 600 includes forming a patterned mask 620 (not shown) on the substrate 200. Figure 6A Then, using a suitable etching process, such as a dry etching process or a wet etching process, the substrate 200 is etched to form a trench 600, wherein the formed trench 600 has a first width W1. In some embodiments, the patterned mask 620 may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof.

[0097] The trench 600, having a first width W1, can define the width of the character line structure 110 (i.e., the first portion 110A) located in the isolation region 140 in subsequent processes. As mentioned above, when the first portion 110A has a smaller width, the distance between the character line structure 110 and adjacent components can be increased, thereby enabling the isolation region 140 to provide better electrical isolation. Therefore, the first width W1 can be determined according to product design and process conditions.

[0098] Figure 6B And the following text Figure 7B and Figure 8 to Figure 10 Three trenches 600 are shown, one of which is the first part of the isolation region 140, trench 600A, and the other two trenches 600 are the second part of the active region 130, trench 600B. Because the cross-sectional view is a single section, it is difficult to read... Figure 6B , Figure 7B and Figure 8 to Figure 10 When drawing the cross-sectional diagram, it should be noted that each groove 600 can actually have both a first part 600A and a second part 600B, such as... Figure 6A and Figure 7A As shown.

[0099] Please see Figure 7A and Figure 7B , Figure 7A The present invention illustrates a configuration diagram of one process stage for forming a semiconductor structure 100 according to some embodiments thereof. Figure 7B The invention illustrates one of the process stages for forming a semiconductor structure 100 according to some embodiments of the invention. Figure 7A Cross-sectional view with section AA. (See diagram below.) Figure 7A andFigure 7B As shown, after the trenches 600 are formed, the width of the second portion of the trenches 600B (i.e., the trenches 600 located within the active region 130) is increased. In some embodiments, the first portion of the trenches 600A can remain at the first width Wi, and the second portion of the trenches 600B can have a second width W2.

[0100] In some embodiments, the second portion of the trenches 600B is increased from the first width Wi to the second width W2, where the second width W2 is about 1.0 nanometer to about 3.0 nanometers wider than the first width Wi, such as 1.0, 1.5, 2.0, 2.5, or 3.0 nanometers. In other words, the increase in width of the second portion of the trenches 600B is about 1.0 nanometer to about 3.0 nanometers, such as 1.0, 1.5, 2.0, 2.5, or 3.0 nanometers. In some embodiments, the increase in width of the second portion of the trenches 600B is about 2.0 nanometers.

[0101] By selectively increasing the width of the second portion of the trenches 600B, the word line structures 110 located within the active region 130 can have a greater width. The second portion of the trenches 600B having the second width W2 can define the word line structures 110 (i.e., the second portion 110B) located within the active region 130 in subsequent processes without affecting the first width Wi of the word line structures 110 (i.e., the first portion 110A) located within the isolation region 140. In this manner, the semiconductor structure 100 can still provide sufficient channel area to maintain the performance of the semiconductor structure 100.

[0102] Increasing the width of the second portion of the trenches 600B includes using an etching process. In embodiments where the etching process is used, the etching process can be performed such that the removal rate of the material of the active region 130 is greater than the removal rate of the material of the isolation region 140. In some embodiments, the etch selectivity of the material of the active region 130 to the material of the isolation region 140 is at least about 5 in the selective etching process. In one embodiment, the etching process is an isotropic etch.

[0103] When the material of the active region 130 includes silicon and the material of the isolation region 140 includes silicon oxide, the etching process can use a gas, where the gas can include a nitrogen-containing gas, a fluorine-containing gas, other suitable gases, and combinations thereof. The nitrogen-containing gas can include ammonia or nitrogen trifluoride, but the present application is not limited thereto. The fluorine-containing gas can include hydrogen fluoride or nitrogen trifluoride, but the present application is not limited thereto.

[0104] The etching process can be performed in conjunction with a plasma. By adjusting the operating parameters of the plasma, the plasma interacts with the gases used in the etching process to produce radicals as etching agents. In some embodiments, the plasma produces radicals of hydrogen as etching agents. In some embodiments, the plasma produces radicals of fluorine as etching agents. The plasma is then separated from the radicals as etching agents. In some embodiments, the radicals as etching agents can be separated from the plasma by a charged grid (not shown) that blocks the movement of charged ions from the plasma and allows uncharged particles (e.g., radicals as etching agents) to pass through the charged grid. For example, the charged grid can prevent charged ions (e.g., positively charged ions or negatively charged ions) from passing through by repelling or attracting the charged ions. Any element that can separate the plasma and the radicals as etching agents can be used in the present application.

[0105] Next, the radicals as etching agents can diffuse into the second portion of the trench 600B and react with the material of the active region 130. By using radicals as etching agents, the etching selectivity of the material of the active region 130 to the material of the isolation region 140 in the etching process can be improved to reduce the loss of the material of the isolation region 140 during the etching process. In some embodiments, the thickness of the material of the isolation region 140 is reduced by less than about 0.2 nm during the etching process. In addition, the etching process using radicals as etching agents is an isotropic etching process.

[0106] In some embodiments, after the width of the second portion of the trench 600B is increased, a portion 700 of the patterned mask 620 can overhang the opening of the second portion of the trench 600B, as shown in FIG. 6B. The length 700L of the portion 700 of the patterned mask 620 overhanging the opening of the second portion of the trench 600B can depend on the amount of increase in the width of the second portion of the trench 600B. In some embodiments, the length 700L can be in the range of about 0.5 nm and about 1.5 nm. In some embodiments, the length 700L can be about 1.0 nm. In other embodiments, the patterned mask 620 can be removed from the substrate 200 before the width of the second portion of the trench 600B is increased. Figure 7B

[0107] Referring to Figure 8 , Figure 8 A cross-sectional view of one of the process stages of forming a semiconductor structure 100 according to some embodiments of the present application is shown in FIG. 6A. As shown in FIG. 6A, the substrate 200 is provided with a first portion of the trench 600A and a second portion of the trench 600B. The first portion of the trench 600A has a first width Wl and the second portion of the trench 600B has a second width W2. The second width W2 is greater than the first width Wl. The patterned mask 620 is disposed on the substrate 200 and covers the first portion of the trench 600A. The patterned mask 620 does not cover the second portion of the trench 600B. Figure 2 Figure 8 ​​As shown, a dielectric layer 112 is formed on the inner surfaces 600S of the trenches 600 (including the first portion trenches 600A and the second portion trenches 600B). In some embodiments, the dielectric layer 112 conformally covers the inner surfaces 600S of the trenches 600. The dielectric layer 112 is formed of any suitable dielectric material, which can include at least one of silicon oxide, silicon nitride, silicon oxynitride, high-k material (e.g., hafnium oxide (Hf02), zirconium oxide (Zr02), or tantalum pentoxide (Ta205)). The dielectric layer 112 can be a single layer or a multi-layer structure. For example, the dielectric layer 112 with a bi-layer structure can include silicon oxide and silicon nitride, but the present disclosure is not limited thereto. The method of forming the dielectric layer 112 on the inner surfaces 600S of the trenches 600 can include using a CVD process, an ALD process, an oxygen plasma oxidation process, a thermal oxidation process, other suitable techniques, or a combination thereof.

[0108] Referring to Figure 9 , Figure 9 A cross-sectional view of one of the process stages of forming the semiconductor structure 100 is depicted in accordance with some embodiments of the present disclosure. As shown, Figure 9 a conductive layer 114 is formed within the trenches 600, where the dielectric layer 112 covers the conductive layer 114. The conductive layer 114 is located at least partially overlapping the source / drain regions 132. In other words, the source / drain regions 132 are disposed on opposite sides of the conductive layer 114. The conductive layer 114 can be a semiconductor, a metal, a metal nitride, a metal silicide, other suitable conductive material, or a combination thereof. For example, the conductive layer 114 can include doped polysilicon, titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), other suitable conductive material, or a combination thereof.

[0109] Referring to Figure 10 , Figure 10 A cross-sectional view of one of the process stages of forming the semiconductor structure 100 is depicted in accordance with some embodiments of the present disclosure. As shown, Figure 10 a cap layer 116 is formed within the trenches 600 and stacked on the conductive layer 114. The material of the cap layer 116 can include silicon oxide, silicon nitride, silicon oxynitride. In some embodiments, the material of the cap layer 116 includes silicon nitride.

[0110] In Figure 10 ​Afterwards, the word line structure 110 of the semiconductor structure 100 is completed, and the word line structure 110 includes a first portion 110A located in the isolation region 140 and a second portion 110B located in the active region 130. Subsequently, the conventional process techniques can be performed to form the semiconductor structure 100 as shown in FIG. 1C. Figure 2

[0111] The present application relates to semiconductor structures and methods of forming the same. Each word line structure has portions with different widths depending on the location of the portions. The different widths of the portions of the word line structure provide different functions, thereby improving the process yield of the semiconductor structure. The portions of the word line structure located in the isolation region have smaller widths, thereby increasing the distance between the word line structure and adjacent elements, so that the isolation region can provide better electrical isolation and reduce the concern of current leakage of the semiconductor structure. Meanwhile, the portions of the word line structure located in the active region have larger widths, thereby providing sufficient channel area and maintaining the performance of the semiconductor structure.

[0112] The above outlines the features of the embodiments of the present application, so that those skilled in the art can more easily understand the present application. Any person skilled in the art should understand that the present application can be easily used as a basis for modification or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present application. Any person skilled in the art can also understand that the structures equivalent to the above do not depart from the spirit and scope of the present application, and can be modified, replaced and changed without departing from the spirit and scope of the present application.​

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Receive substrate; An isolation zone and an active zone are formed within the substrate; A trench is formed within the substrate. The trench is linear in shape and extends through the isolation region and the active region of the substrate. The trench includes a first portion trench and a second portion trench, wherein the first portion trench is located in the isolation region and the second portion trench is located in the active region. After the trench is formed, the width of the second trench is increased by a dry etching process, wherein the dry etching process includes using gas and plasma, the gas and plasma interacting to generate an etchant in a free radical state, and separating the plasma from the etchant in a free radical state so that the etchant in a free radical state diffuses into the second trench. A dielectric layer is formed on the inner surface of the trench; A conductive layer is formed in the trench, wherein the dielectric layer covers the conductive layer; as well as A capping layer is formed within the trench and stacked on the conductive layer.

2. The method for forming a semiconductor structure according to claim 1, wherein the increase in the width of the second portion of the trench is from 1 nanometer to 3 nanometers.

3. The method for forming a semiconductor structure according to claim 1, wherein the etch selectivity ratio of the material of the active region to the material of the isolation region is at least greater than 5.

4. The method for forming a semiconductor structure according to claim 1, wherein the gas comprises ammonia.

5. The method for forming a semiconductor structure according to claim 1, wherein the gas comprises nitrogen trifluoride.

6. The method for forming a semiconductor structure according to claim 1, wherein the etchant in the radical state comprises a hydrogen radical or a fluorine radical.

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