Array substrate and preparation method thereof, and display device

Abstract

The present application discloses an array substrate and a preparation method thereof, and a display device, wherein the array substrate comprises: a transistor structure layer, the transistor structure layer comprises a transistor region and a non-transistor region; the transistor region comprises a transistor; the transistor region also comprises a light blocking pattern, and the orthographic projection of the light blocking pattern on the array substrate overlaps at least partially with the orthographic projection of the active pattern of the transistor on the array substrate. In the above scheme, since the light blocking pattern is formed in the transistor region, the light blocking pattern can block light for the transistor, that is, the light blocking pattern can prevent or reduce the light intensity of the light entering the transistor, so that the active layer of the transistor does not have a photoelectric effect, which solves the problem that the active layer of the transistor has a photoelectric effect due to the light entering the transistor, causing the carrier concentration in the active layer to rise rapidly, the channel current to increase, and the transistor cannot be completely turned off.

Description

Technical Field

[0001] The present invention generally relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display device. Background Art

[0002] Transistors are important switching elements in the field of display technology. For example, but not limited to, a liquid crystal display includes a backlight, an array substrate, a liquid crystal layer, and a color film substrate stacked in sequence. When displaying a picture, the backlight is always on, and the deflection of the liquid crystal in the liquid crystal layer is controlled by controlling the switching state of the transistor in the array substrate, thereby achieving a display effect of corresponding brightness of the corresponding pixel.

[0003] However, transistors have a photoelectric effect. When light shines on the active layer of the transistor, the carrier concentration in the active layer rises rapidly and the channel current increases. This effect can cause the transistor to be unable to be completely turned off, thus affecting the display effect. Summary of the invention

[0004] The present application hopes to provide an array substrate and a preparation method thereof, and a display device, so as to solve the problem that light irradiates the active layer of the transistor, causing the channel current of the transistor to increase, resulting in the transistor being unable to be completely turned off.

[0005] In a first aspect, the present invention provides an array substrate, comprising: a transistor structure layer, the transistor structure layer comprising a transistor region and a non-transistor region;

[0006] The transistor region includes a transistor;

[0007] The transistor region further includes a light blocking pattern, and an orthographic projection of the light blocking pattern on the array substrate at least partially overlaps with an orthographic projection of an active pattern of the transistor on the array substrate.

[0008] As an implementable manner, the non-transistor region includes a first transparent electrode pattern, the light blocking pattern and the first transparent electrode pattern are arranged in the same layer, and the light transmittance of the light blocking pattern is lower than the light transmittance of the first transparent electrode pattern.

[0009] As an implementable manner, at least part of the orthographic projection of the active pattern of the transistor on the array substrate is located within the orthographic projection range of the light blocking pattern on the array substrate.

[0010] As an implementable manner, the transistor further includes a first gate pattern, and the light blocking pattern and the first gate pattern are disposed on both sides of the active pattern.

[0011] As an implementable manner, it further includes a second gate pattern disposed in the same layer as the first gate pattern, a first transparent electrode layer is disposed on a side of the first gate pattern away from the active pattern, and the first transparent electrode layer includes a second transparent electrode pattern and a third transparent electrode pattern;

[0012] The transistor structure layer further comprises a via hole, a conductive member is disposed in the via hole, and the light blocking pattern is electrically connected to the second gate pattern through the conductive member;

[0013] The third transparent electrode pattern is electrically connected to the first gate pattern, and the second transparent electrode pattern is electrically connected to the second gate pattern.

[0014] In a second aspect, the present invention provides a method for preparing an array substrate, comprising the following steps:

[0015] forming a transistor structure layer, wherein the transistor structure layer includes a transistor region and a non-transistor region, and a transistor is formed in the transistor region;

[0016] A light blocking pattern is formed on the transistor structure layer, the light blocking pattern is located in the transistor region, and the light blocking pattern is at least used to perform light blocking protection on the transistor.

[0017] As an implementable manner, the light blocking pattern is formed on the transistor structure layer, specifically:

[0018] forming a transparent conductive oxide film on the transistor structure layer;

[0019] forming a photoresist layer on the transparent conductive oxide film;

[0020] Expose and develop the photoresist layer using a mask including a halftone area and a fulltone area, wherein the halftone area corresponds to the transistor area, and the fulltone area corresponds to the non-transistor area;

[0021] etching the transparent conductive oxide film exposed to the developed photoresist layer to form a first transparent electrode pattern at least in the non-transistor region;

[0022] Thinning the developed photoresist layer until the transparent conductive oxide film in the transistor region is exposed;

[0023] Performing a light transmittance reduction treatment on the transparent conductive oxide film in the transistor region to obtain the light blocking pattern;

[0024] The remaining photoresist is stripped off.

[0025] As an achievable manner, the transparent conductive oxide film in the transistor region is subjected to a light transmittance reduction treatment, specifically:

[0026] A hydrogen reduction treatment is performed on at least a portion of the transparent conductive oxide in the transparent conductive oxide film in the transistor region.

[0027] As an achievable manner, the forming of the transistor structure layer is specifically as follows:

[0028] forming a gate layer, the gate layer comprising a first gate pattern and a second gate pattern;

[0029] forming a gate insulating layer on the gate layer;

[0030] forming an active layer on the gate insulating layer, wherein the active layer includes an active pattern;

[0031] forming a data wiring layer on the active layer;

[0032] forming a passivation layer on the data wiring layer;

[0033] A via hole is formed from the passivation layer to the second gate pattern at a position corresponding to the second gate pattern.

[0034] In a third aspect, the present invention provides a display device, comprising the above-mentioned array substrate.

[0035] In the above scheme, since a light blocking pattern is formed in the transistor region, and the orthographic projection of the light blocking pattern on the array substrate overlaps at least partially with the orthographic projection of the active pattern of the transistor on the array substrate, the light blocking pattern can at least block the active pattern of the transistor for light protection, that is, the light blocking pattern can prevent or reduce the light intensity of the light entering the active pattern in the transistor, so that the active layer of the transistor does not have a photoelectric effect, and solves the problem that the active layer of the transistor cannot be completely turned off due to the photoelectric effect caused by the light entering the transistor, causing the carrier concentration in the active layer to rise rapidly, the channel current to increase, and the transistor cannot be completely turned off. Furthermore, as the transistor can be completely turned off, a normal display effect can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1-Figure 6 A schematic diagram of the manufacturing process of the array substrate provided in Example 1 of the present invention;

[0038] Figure 7 A schematic diagram of the structure of an array substrate provided for Example 2 of the present invention;

[0039] Figure 8 A schematic diagram of the structure of an array substrate provided in Example 3 of the present invention;

[0040] Fig. 9 This is a graph showing the relationship between the light transmittance reduction treatment time and transmittance;

[0041] Figure 10-15 A schematic diagram of the manufacturing process of an array substrate provided in Example 4 of the present invention;

[0042] Fig.16 A schematic diagram of the structure of an array substrate provided in Example 5 of the present invention;

[0043] Fig.17 This is a schematic diagram of the structure of the array substrate provided in Example 6 of the present invention. DETAILED DESCRIPTION

[0044] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] like Figure 1-Figure 6 As shown, an array substrate shown in an embodiment of the present invention includes: a transistor structure layer T, wherein the transistor structure layer T includes a transistor region A and a non-transistor region B;

[0047] The transistor area A includes transistors; wherein the transistors may be thin film transistors, field effect transistors, triodes or other devices with the same characteristics, and may be N-type transistors or P-type transistors. Different types of transistors are used mainly considering their conduction forms, and N-type transistors are conducted at a high level, and P-type transistors are conducted at a low level. The transistors in the following text take thin film transistors as an example.

[0048] The transistor region A also includes a light blocking pattern 24, the orthographic projection of the light blocking pattern 24 on the array substrate at least partially overlaps with the orthographic projection of the transistor active pattern 7 on the array substrate, so that the light blocking pattern 24 can at least block the light of the transistor active pattern 7. The light blocking pattern 24 can be formed by forming a film layer on the transistor structure layer T and patterning it through a composition process.

[0049] The specific material and structure of the light blocking pattern 24 are not uniquely limited here, as long as it can prevent light from entering the transistor and prevent the active layer of the transistor from experiencing a photoelectric effect due to the light.

[0050] The "patterning process" mentioned in the embodiment of the present invention includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, etching can adopt known methods, and epitaxial growth also adopts known methods, which are not specifically limited here.

[0051] In the description of the embodiments of the present invention, it is necessary to understand that "film" refers to a thin film made by depositing, coating or growing a certain material on a substrate (or a certain layer). If the "film" does not require a composition process or a photolithography process during the entire production process, the "film" can also be called a "layer". If the "film" still requires a composition process or a photolithography process during the entire production process, it is called a "film" before the composition process and a "layer" after the composition process. The "layer" after the composition process or the photolithography process contains at least one "pattern". For example, but not limited to, the thickness of the film referred to in this article may be less than 100μm.

[0052] In the above scheme, since a light blocking pattern 24 is formed in the transistor area A, and the orthographic projection of the light blocking pattern on the array substrate at least partially overlaps with the orthographic projection of the active pattern of the transistor on the array substrate, the light blocking pattern 24 can at least perform light blocking protection on the active pattern of the transistor, that is, the light blocking pattern 24 can prevent or reduce the intensity of light entering the active pattern in the transistor, so that the active layer of the transistor does not undergo a photoelectric effect, thereby solving the problem that the photoelectric effect occurs in the active layer of the transistor due to light entering the transistor, causing the carrier concentration in the active layer to rise rapidly, the channel current to increase, and the transistor cannot be completely turned off.

[0053] As an achievable manner, in order to simplify the preparation process, reduce production costs and improve production efficiency, the non-transistor region B is formed with a first transparent electrode pattern 21, the light blocking pattern 24 and the first transparent electrode pattern 21 are arranged in the same layer, and the light transmittance of the light blocking pattern 24 is less than the light transmittance of the first transparent electrode pattern 21. For example but not limited to, the light blocking pattern 24 and the first transparent electrode pattern 21 are prepared by patterning the same transparent conductive oxide film 2, and the region of the transparent conductive oxide film 2 corresponding to the light blocking pattern 24 is subjected to a light transmittance reduction treatment to obtain the light blocking pattern 24.

[0054] For example, a transparent conductive oxide film 2 is formed on the transistor structure layer T, and then the transparent conductive oxide film 2 is patterned by a composition process, and after patterning, the area 22 corresponding to the light blocking pattern 24 is subjected to a light transmittance reduction treatment to obtain the light blocking pattern 24, and the remaining patterned area is the first transparent electrode pattern 21.

[0055] The material forming the transparent conductive oxide film 2 may be, but is not limited to, ITO (Indium Tin Oxide), FTO (SnO2: F; fluorine-doped tin oxide), ATO (Sn2O: Sb; antimony-doped tin oxide), etc. The present invention takes ITO as an example, and the light transmittance reduction treatment thereof can also be called blackening treatment, which is generally carried out by hydrogen reduction of ITO to generate opaque (black) InO / SnO, and the amount of InO / SnO generated can be controlled by controlling the reaction conditions, such as reaction time, temperature, amount of hydrogen, etc., so as to achieve the purpose of reducing light transmittance or even completely blocking the passage of light.

[0056] As an achievable method, at least part of the orthographic projection of the active pattern 7 of the transistor on the array substrate is located within the orthographic projection range of the light blocking pattern 24 on the array substrate. For example, the orthographic projection of the active pattern 7 of the transistor on the array substrate is completely located within the orthographic projection range of the light blocking pattern 24 on the array substrate, so as to better block the light from entering the active pattern 7 to prevent light leakage; of course, in other examples, depending on the structure or type of the transistor, only part of the orthographic projection of the active pattern 7 on the array substrate needs to be located within the orthographic projection range of the light blocking pattern 24 on the array substrate, so that while preventing light leakage, it can also save materials and increase the distance between the light blocking pattern 24 and the first transparent electrode pattern 21, avoiding defects caused by process errors, which will be explained in detail in different examples later. The orthographic projection range mentioned here means that the boundaries of the two orthographic projections completely overlap, or the boundary of one of the orthographic projections is located within the boundary of the other orthographic projection.

[0057] As an implementable manner, the transistor further includes a first gate pattern 8 , and the light blocking pattern 24 and the first gate pattern 8 are disposed on both sides of the active pattern 7 .

[0058] Generally, the first gate pattern 8 can be made of one of the metals such as silver, copper, aluminum, molybdenum and their alloys, that is, the first gate pattern 8 can also have a light-shielding effect. In addition, since the light blocking pattern 24 and the first gate pattern 8 are arranged on both sides of the active pattern 7, the active pattern 7 can be protected from light shading from both sides of the active pattern 7.

[0059] As an achievable method, see at least Fig.13 As shown, it also includes a second gate pattern 10 arranged in the same layer as the first gate pattern 8, and a first transparent electrode layer is arranged on a side of the first gate pattern 8 away from the active pattern 7, and the first transparent electrode layer includes a second transparent electrode pattern 11 and a third transparent electrode pattern 9;

[0060] The transistor structure layer T further includes a via hole, in which a conductive member 23 is disposed, and the light blocking pattern 24 is electrically connected to the second gate pattern 10 through the conductive member 23;

[0061] The third transparent electrode pattern 9 is electrically connected to the first gate pattern 8 , and the second transparent electrode pattern 11 is electrically connected to the second gate pattern 10 .

[0062] By providing the conductive member 23 , the light blocking pattern 24 and the second gate pattern 10 are electrically connected via the conductive member 23 , thereby forming a double-gate structure, which can enhance the switching control effect of the transistor.

[0063] The array substrate provided by the present invention is exemplified below with specific examples, which should not be construed as the sole limitation of the present invention.

[0064] Example 1

[0065] like Figure 1-Figure 6 As shown, the array substrate includes: a first transparent electrode layer, and a transistor structure layer T disposed on the first transparent electrode layer, wherein the transistor structure layer T includes a gate layer, a gate insulating layer, an active layer, a data wiring layer 6, and a passivation layer 3 stacked in sequence; wherein the transistor structure layer T includes a transistor region A and a non-transistor region B, and a transistor is formed in the transistor region A; that is, at least the first gate pattern 8 of the gate layer and the active pattern 7 of the active layer are located in the transistor region A. Furthermore, the first transparent electrode layer includes a third transparent electrode pattern 9, and the third transparent electrode pattern 9 is electrically connected to the first gate pattern 8.

[0066] On the transistor structure layer T, the light blocking pattern 24 and the first transparent electrode pattern 21 are patterned from the same transparent conductive oxide film 2 , and the region 22 of the transparent conductive oxide film 2 corresponding to the light blocking pattern 24 is subjected to a light transmittance reduction treatment to obtain the light blocking pattern 24 .

[0067] In this example, the orthographic projection of the active pattern 7 on the array substrate is within the orthographic projection range of the light blocking pattern 24 on the array substrate, and the light blocking pattern 24 is larger than the active pattern 7, so as to better shield the active pattern 7 and prevent light from irradiating the active pattern 7 and generating a photoelectric effect.

[0068] Example 2

[0069] like Figure 7 As shown, for a conventional thin film transistor, such as an amorphous silicon thin film transistor, the data wiring layer 6 overlaps on both sides of the active pattern 7, and the positive projection of the active pattern 7 not covered by the data wiring layer 6 on the array substrate is located within the positive projection range of the light blocking pattern 24 on the array substrate, that is, as long as the size of the light blocking pattern 24 can block the part of the active pattern 7 not covered by the data wiring layer 6, it can prevent light from irradiating the active pattern 7, and at the same time save the material for making the light blocking pattern 24. In addition, for transistors of the same size, the distance D2 between the light blocking pattern 24 and the first transparent electrode pattern 21 in this example is greater than the distance D1 between the light blocking pattern 24 and the first transparent electrode pattern 21 in Example 1. In other words, by adopting the solution in Example 2, the distance between the light blocking pattern 24 and the first transparent electrode pattern 21 is increased, and defects caused by process errors can be avoided.

[0070] Example 3

[0071] like Figure 8 As shown, for a low-temperature polysilicon thin film transistor, the active pattern 7 includes a non-conductorized area 71 in the middle and conductorized areas 72 on both sides thereof, and the data wiring layer 6 is arranged in the same layer as the active pattern 7. In this example, the positive projection of the non-conductorized area 71 of the active pattern 7 on the array substrate is located within the positive projection range of the light blocking pattern 24 on the array substrate, that is, as long as the size of the light blocking pattern 24 can block the non-conductorized area 71 of the active pattern 7, it can prevent light from irradiating the non-conductorized area 71 of the active pattern 7, and at the same time save the material for making the light blocking pattern 24. In addition, the scheme of this example also increases the distance between the light blocking pattern 24 and the first transparent electrode pattern 21, which can avoid defects caused by process errors.

[0072] Example 4

[0073] like Figure 10-15As shown, the main difference between this example and Example 1 is that the first transparent electrode layer further includes a second transparent electrode pattern 11, the gate layer further includes a second gate pattern 10, and a via is provided on the transistor structure layer T at a position corresponding to the second gate pattern 10, and a conductive member 23 is formed in the via. The conductive member 23 can be a part of the transparent conductive oxide film 2, that is, the conductive member 23, the light blocking pattern 24 and the first transparent electrode pattern 21 are made of the same transparent conductive oxide film 2, so as to simplify the preparation process. The light blocking pattern 24 is electrically connected to the second gate pattern 10 through the conductive member 23, and the second transparent electrode pattern 11 is electrically connected to the second gate pattern 10.

[0074] Example 5

[0075] like Fig.16 As shown, the main difference between it and Example 4 is that the size of the light blocking pattern 24 is only enough to block the part of the active pattern 7 that is not covered by the data wiring layer 6 .

[0076] Example 6

[0077] like Fig.17 As shown, the main difference between it and Example 4 is that the size of the light blocking pattern 24 only needs to block the non-conductive area 71 of the active pattern 7, and does not need to block the conductive area 72.

[0078] The effects of Examples 5 and 6 are the same as those of Examples 2 and 3, and will not be described in detail here.

[0079] In a second aspect, the present invention provides a method for preparing an array substrate, comprising the following steps:

[0080] forming a transistor structure layer T, wherein the transistor structure layer T includes a transistor region A and a non-transistor region B, wherein a transistor is formed in the transistor region A;

[0081] A light blocking pattern 24 is formed on the transistor structure layer T. The light blocking pattern 24 is located in the transistor region A. The light blocking pattern 24 is at least used to block light and protect the transistor.

[0082] As an implementable manner, the light blocking pattern 24 is formed on the transistor structure layer T, specifically:

[0083] forming a transparent conductive oxide film 2 on the transistor structure layer T;

[0084] forming a photoresist layer 1 on the transparent conductive oxide film 2;

[0085] The photoresist layer 1 is exposed and developed using a mask plate 5 including a halftone area C and a full-tone area D, wherein the halftone area C corresponds to the transistor area A, and the full-tone area D corresponds to the non-transistor area B;

[0086] Etching the transparent conductive oxide film 2 exposed to the developed photoresist layer 1 to form a first transparent electrode pattern 21 at least in the non-transistor region B;

[0087] Thinning the developed photoresist layer 1 until the transparent conductive oxide film 2 of the transistor region A is exposed;

[0088] Performing a light transmittance reduction treatment on the transparent conductive oxide film 2 of the transistor region A to obtain the light blocking pattern 24;

[0089] The remaining photoresist is stripped off.

[0090] As an achievable manner, the light transmittance reduction treatment of the transparent conductive oxide film 2 in the transistor region A is specifically performed as follows:

[0091] At least a portion of the transparent conductive oxide in the transparent conductive oxide film 2 of the transistor region A is subjected to hydrogen reduction treatment.

[0092] As an implementable manner, the forming of the transistor structure layer T is specifically as follows:

[0093] forming a gate layer, wherein the gate layer includes a first gate pattern 8 and a second gate pattern 10;

[0094] forming a gate insulating layer on the gate layer;

[0095] forming an active layer on the gate insulating layer, wherein the active layer comprises an active pattern 7;

[0096] forming a data wiring layer 6 on the active layer;

[0097] Forming a passivation layer 3 on the data wiring layer 6;

[0098] A via hole is formed from the passivation layer 3 to the second gate pattern 10 at a position corresponding to the second gate pattern 10 .

[0099] The following is an illustrative description of the method for preparing the array substrate provided by the present invention with reference to specific examples, which should not be construed as the sole limitation of the present invention.

[0100] Example 7

[0101] like Figure 1-Figure 6 As shown, the method for preparing the array substrate provided in this example includes the following steps:

[0102] S101 : forming an ITO film on a substrate, and patterning the ITO film to form a first transparent electrode layer having a third transparent electrode pattern 9 .

[0103] The substrate may be a flexible substrate, such as a polyethylene terephthalate (PET) film, a PI (Polyimide) film, etc.; or a rigid substrate, such as a glass substrate, etc.

[0104] S102: forming a transistor structure layer T on the first transparent electrode layer, the transistor structure layer T comprising a transistor region A and a non-transistor region B, and a transistor is formed in the transistor region A;

[0105] The transistor structure layer T is formed as follows:

[0106] A metal film is deposited on the first transparent electrode layer, and the metal film is patterned by a composition process to form a gate layer having a first gate pattern 8; the first gate pattern 8 is electrically connected to the third transparent electrode pattern 9, and the metal film can be made of a metal material, such as silver, copper, aluminum, molybdenum and the like, and an alloy thereof;

[0107] Depositing a gate insulating layer on the gate layer, the gate insulating layer may be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and may be a single-layer, double-layer or multi-layer structure;

[0108] An active film is deposited on the gate insulating layer, and the active film is patterned by a composition process to form an active layer having an active pattern 7; the active film can be an amorphous silicon film, and the amorphous silicon film is processed by a laser method to crystallize the amorphous silicon film into a polycrystalline silicon film to form a low-temperature polycrystalline silicon (LTPS) thin film transistor. The two ends of the active pattern 7 are made conductive by heat treatment, so that the active pattern 7 is separated into a semiconductor region and conductive regions on both sides thereof, and the conductive regions serve as the source and drain of the thin film transistor respectively.

[0109] A metal wiring film is deposited on the active layer, and the metal wiring film is patterned to form a data wiring layer 6. The data wiring patterns of the data wiring layer 6 are respectively connected to the source and drain electrodes.

[0110] A passivation layer 3 is deposited on the data wiring layer 6. For example, by plasma enhanced chemical vapor deposition, NH3 / SiH4 is used as a working gas to deposit silicon nitride as the passivation layer 3 on the data wiring layer 6. The formed passivation layer 3 contains a certain amount of hydrogen.

[0111] S103: depositing another ITO film as a transparent conductive oxide film 2 on the transistor structure layer T;

[0112] S104: coating a photoresist layer 1 on the transparent conductive oxide film 2;

[0113] S105: using a mask plate 5 including a halftone area C and a full-tone area D to expose and develop the photoresist layer 1, wherein the halftone area C corresponds to the transistor area A, and the full-tone area D corresponds to the non-transistor area B; thus corresponding photoresist patterns are formed in the transistor area A and the non-transistor area B, respectively, and the thickness of the photoresist pattern in the transistor area A is less than the thickness of the photoresist pattern in the non-transistor area B;

[0114] S106: etching the transparent conductive oxide film 2 exposed to the developed photoresist layer 1 to form corresponding ITO patterns in the transistor region A and the non-transistor region B, respectively, wherein the ITO pattern in the non-transistor region B is used as the first transparent electrode pattern 21, and the ITO pattern in the transistor region A (i.e., region 22) is used to form the light blocking pattern 24;

[0115] S107: Thinning the developed photoresist layer 1 until the ITO pattern of the transistor region A is exposed; the photoresist layer 1 can be thinned by wet etching, dry etching or laser etching. In this example, a dry etching process is used, which can also be called ashing of the photoresist. It is processed in an ECCP (Enhance Cathode Coupling Plasma) dry etching device, using NF3 and O2 as working gases, and the process conditions are: source power / bias power (Source power / Bias Power) is 12kw / 10kw, the flow rate of NF3 / O2 is 1500 / 10000sccm, and the working pressure is 40mt.

[0116] Since the thickness of the photoresist pattern in the transistor region A is less than that in the non-transistor region B, when the photoresist layer 1 is thinned until the ITO pattern in the transistor region A is exposed, the first transparent electrode pattern 21 still has photoresist, so as to protect the first transparent electrode pattern 21 in the subsequent light transmittance reduction process to prevent the light transmittance of the first transparent electrode pattern 21 from being reduced.

[0117] S108: Perform a light transmittance reduction treatment on the ITO pattern in transistor area A to obtain a light blocking pattern 24; performing a light transmittance reduction treatment on the ITO pattern can also be called a blackening treatment on the ITO pattern. Generally, the ITO is hydrogen-reduced to generate opaque (black) InO / SnO, and the amount of InO / SnO generated can be controlled by controlling the reaction conditions, such as reaction time, temperature, and amount of hydrogen, so as to achieve the purpose of reducing light transmittance or even completely blocking the passage of light. For example, the light transmittance reduction treatment can be performed in a plasma enhanced chemical vapor deposition device, using H2 as the working gas. The process conditions are a source power of 6kw6, a H2 flow rate of 80,000sccm, a working pressure of 1000mt, and a processing time of 15S. Of course, other processing times can be used depending on the degree of light transmittance reduction required, such as Fig. 9 As shown, the longer the treatment time is, the greater the degree of light transmittance reduction is (ie, the lower the light transmittance is).

[0118] In other examples, the light transmittance can be reduced by laser. By irradiating the ITO pattern in the transistor area A with laser, the passivation layer 3 of silicon nitride material underneath will release hydrogen to reduce the ITO. The laser power can be adjusted to process only the surface of the ITO without damaging the underlying functional film layer.

[0119] S109: Stripping off the remaining photoresist.

[0120] Example 8

[0121] like Figure 10-15 As shown, the method for preparing the array substrate provided in this example includes the following steps:

[0122] S201 : forming an ITO film on a substrate, and patterning the ITO film to form a first transparent electrode layer having a second transparent electrode pattern 11 and a third transparent electrode pattern 9 .

[0123] The substrate may be a flexible substrate, such as a polyethylene terephthalate (PET) film, a PI (Polyimide) film, etc.; or a rigid substrate, such as a glass substrate, etc.

[0124] S202: forming a transistor structure layer T on the first transparent electrode layer, the transistor structure layer T comprising a transistor region A and a non-transistor region B, and a transistor is formed in the transistor region A;

[0125] The transistor structure layer T is formed as follows:

[0126] A metal film is deposited on the first transparent electrode layer, and the metal film is patterned by a composition process to form a gate layer having a first gate pattern 8 and a second gate pattern 10; the first gate pattern 8 is electrically connected to the third transparent electrode pattern 9, and the second gate pattern 10 is electrically connected to the second transparent electrode pattern 11. The metal film can be made of metal material, such as one of silver, copper, aluminum, molybdenum and the like and alloys thereof;

[0127] Depositing a gate insulating layer on the gate layer, the gate insulating layer may be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and may be a single-layer, double-layer or multi-layer structure;

[0128] An active film is deposited on the gate insulating layer, and the active film is patterned through a composition process to form an active layer having an active pattern 7; the active film can be an amorphous silicon film, and the two ends of the active pattern 7 are made conductive by heat treatment, so that the active pattern 7 is separated into a semiconductor region and conductive regions on both sides thereof, and the conductive regions serve as the source and drain of the thin film transistor respectively.

[0129] A metal wiring film is deposited on the active layer, and the metal wiring film is patterned to form a data wiring layer 6. The data wiring patterns of the data wiring layer 6 are respectively connected to the source and drain electrodes.

[0130] A passivation layer 3 is deposited on the data wiring layer 6. For example, by plasma enhanced chemical vapor deposition, NH3 / SiH4 is used as a working gas to deposit silicon nitride as the passivation layer 3 on the data wiring layer 6. The formed passivation layer 3 contains a certain amount of hydrogen.

[0131] S203: forming a via hole from the passivation layer 3 to the second gate pattern 10 at a position corresponding to the second gate pattern 10;

[0132] S204: depositing another ITO film as a transparent conductive oxide film 2 on the transistor structure layer T;

[0133] S205: coating a photoresist layer 1 on the transparent conductive oxide film 2;

[0134] S206: using a mask plate 5 including a halftone area C and a full-tone area D to expose and develop the photoresist layer 1, wherein the halftone area C corresponds to the transistor area A, and the full-tone area D corresponds to the non-transistor area B; thus corresponding photoresist patterns are formed in the transistor area A and the non-transistor area B, respectively, and the thickness of the photoresist pattern in the transistor area A is less than the thickness of the photoresist pattern in the non-transistor area B;

[0135] S207: etching the ITO film exposed to the developed photoresist layer 1 to form corresponding ITO patterns in the transistor region A and the non-transistor region B, respectively, wherein the ITO pattern in the non-transistor region B is used as the first transparent electrode pattern 21, and the ITO pattern in the transistor region A (i.e., region 22) is used to form a light blocking pattern 24, and a conductive member 23 located in the via hole, the conductive member 23 is electrically connected to the second gate pattern 10, and the conductive member 23 is in an electrically connected state to the ITO pattern in the transistor region A;

[0136] S208: Thinning the developed photoresist layer 1 until the ITO pattern of the transistor region A is exposed; the photoresist layer 1 can be thinned by wet etching, dry etching or laser etching. In this example, a dry etching process is used, which can also be called ashing of the photoresist. It is processed in an ECCP (Enhance Cathode Coupling Plasma) dry etching device, using NF3 and O2 as working gases, and the process conditions are: source power / bias power (Source power / Bias Power) is 12kw / 10kw, the flow rate of NF3 / O2 is 1500 / 10000sccm, and the working pressure is 40mt.

[0137] Since the thickness of the photoresist pattern in the transistor region A is less than that in the non-transistor region B, when the photoresist layer 1 is thinned until the ITO pattern in the transistor region A is exposed, the first transparent electrode pattern 21 and the conductive member 23 still have photoresist thereon, so as to protect the first transparent electrode pattern 21 and the conductive member 23 in the subsequent light transmittance reduction process, and prevent the light transmittance of the first transparent electrode pattern 21 and the conductive member 23 from being reduced.

[0138] S209: The ITO pattern of the transistor area A is subjected to a light-reducing treatment to obtain a light-blocking pattern 24; the light-reducing treatment of the ITO pattern can also be referred to as a blackening treatment of the ITO pattern. Generally, the ITO is subjected to hydrogen reduction to generate opaque (black) InO / SnO, and the amount of InO / SnO generated can be controlled by controlling the reaction conditions, such as reaction time, temperature, and amount of hydrogen, so as to achieve the purpose of reducing light transmittance or even completely blocking the passage of light. For example, the light-reducing treatment can be performed in a plasma-enhanced chemical vapor deposition device, with H2 as the working gas. The process conditions are a source power of 6kw6, a flow rate of H2 of 80,000sccm, a working pressure of 1000mt, and a processing time of 15S. Of course, other processing times can be used according to the degree of light-reducing requirements.

[0139] In other examples, the light transmittance can be reduced by laser. By irradiating the ITO pattern in the transistor area A with laser, the passivation layer 3 of silicon nitride material underneath will release hydrogen to reduce the ITO. The laser power can be adjusted to process only the surface of the ITO without damaging the underlying functional film layer.

[0140] S210: Stripping off the remaining photoresist.

[0141] In a third aspect, the present invention provides a display device, comprising the above-mentioned array substrate.

[0142] The display device is, for example but not limited to, a mobile phone, a tablet computer, a notebook computer, a monitor, or other products or components with a display function.

[0143] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0144] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. An array substrate, characterized in that: include: A transistor structure layer, wherein the transistor structure layer includes a transistor region and a non-transistor region; The transistor region includes a transistor; The transistor region further includes a light blocking pattern, wherein an orthographic projection of the light blocking pattern on the array substrate at least partially overlaps with an orthographic projection of an active pattern of the transistor on the array substrate; The non-transistor region includes a first transparent electrode pattern, the light blocking pattern and the first transparent electrode pattern are arranged in the same layer, and the light transmittance of the light blocking pattern is less than the light transmittance of the first transparent electrode pattern; It also includes a first gate pattern and a second gate pattern arranged in the same layer as the first gate pattern, a first transparent electrode layer is arranged on a side of the first gate pattern away from the active pattern, and the first transparent electrode layer includes a second transparent electrode pattern and a third transparent electrode pattern; The transistor structure layer further comprises a via hole, a conductive member is disposed in the via hole, and the light blocking pattern is electrically connected to the second gate pattern through the conductive member; The third transparent electrode pattern is electrically connected to the first gate pattern, and the second transparent electrode pattern is electrically connected to the second gate pattern.

2. The array substrate according to claim 1, characterized in that: At least part of the orthographic projection of the active pattern of the transistor on the array substrate is located within the orthographic projection range of the light blocking pattern on the array substrate.

3. The array substrate according to claim 1, characterized in that: The light blocking pattern and the first gate pattern are disposed on both sides of the active pattern.

4. A method for preparing an array substrate, characterized in that: The method for preparing the array substrate according to any one of claims 1 to 3 comprises the following steps: forming a transistor structure layer, wherein the transistor structure layer includes a transistor region and a non-transistor region, and a transistor is formed in the transistor region; A light blocking pattern is formed on the transistor structure layer, the light blocking pattern is located in the transistor region, and the light blocking pattern is at least used to perform light blocking protection on the transistor.

5. The method for preparing an array substrate according to claim 4, characterized in that: The forming of the light blocking pattern on the transistor structure layer is specifically: forming a transparent conductive oxide film on the transistor structure layer; forming a photoresist layer on the transparent conductive oxide film; Expose and develop the photoresist layer using a mask including a halftone area and a fulltone area, wherein the halftone area corresponds to the transistor area, and the fulltone area corresponds to the non-transistor area; etching the transparent conductive oxide film exposed to the developed photoresist layer to form a first transparent electrode pattern at least in the non-transistor region; Thinning the developed photoresist layer until the transparent conductive oxide film in the transistor region is exposed; Performing a light transmittance reduction treatment on the transparent conductive oxide film in the transistor region to obtain the light blocking pattern; The remaining photoresist is stripped off.

6. The method for preparing an array substrate according to claim 5, characterized in that: The light transmittance reducing treatment of the transparent conductive oxide film in the transistor region is specifically performed as follows: A hydrogen reduction treatment is performed on at least a portion of the transparent conductive oxide in the transparent conductive oxide film in the transistor region.

7. The method for preparing an array substrate according to any one of claims 4 to 6, characterized in that: The forming of the transistor structure layer specifically comprises: forming a gate layer, the gate layer comprising a first gate pattern and a second gate pattern; forming a gate insulating layer on the gate layer; forming an active layer on the gate insulating layer, wherein the active layer includes an active pattern; forming a data wiring layer on the active layer; forming a passivation layer on the data wiring layer; A via hole is formed from the passivation layer to the second gate pattern at a position corresponding to the second gate pattern.

8. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 3.

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