Split gate mosfet device and method of fabrication

Abstract

The application discloses a Split Gate MOSFET device and a preparation method, and relates to the technical field of semiconductor power devices. The device comprises a first conductive epitaxial layer, a first trench and a second trench arranged in the first conductive epitaxial layer; the first trench comprises a first gate oxide layer and a first polysilicon layer from outside to inside; the second trench is divided into an upper part and a lower part by a second gate oxide layer from bottom to top, the lower part comprises a first gate oxide layer and a first polysilicon layer from outside to inside, and the upper part comprises a second polysilicon layer, a second gate oxide layer and an isolation oxide layer from outside to inside; a second gate oxide layer, a silicon oxynitride layer, an isolation oxide layer and a metal layer are sequentially arranged on the first conductive epitaxial layer; a contact hole is arranged on the second trench, between the first trench and the second trench, and on a side of the second trench away from the first trench.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and more specifically to Split Gate MOSFET devices and their fabrication methods. Background Technology

[0002] With the continuous maturation of process technology, split-gate MOSFET devices are gradually replacing single-trench MOSFET devices in many fields, especially in the medium-voltage range where their performance advantages are becoming increasingly apparent, leading to a year-on-year decrease in cost and a particularly rapid replacement trend. For power MOSFETs, the main losses come from two aspects: First, conduction loss, determined by the on-resistance of the power MOSFET device. To achieve lower on-resistance, the channel length must be continuously reduced. This can be achieved by reducing the device thickness and changing the unit cell structure from planar to trench, increasing the unit cell density. Increased unit cell density leads to a decrease in the overall trench resistance and epitaxial layer resistance, thus reducing the overall on-resistance. Second, switching loss, which is the power loss introduced during the switching process of the power MOSFET due to the charging and discharging process of parasitic capacitance or the reverse recovery time delay of parasitic diodes. Generally, on-resistance (Rdson) and gate charge (Qg) are selected as indicators to evaluate the magnitude of switching losses. However, since different application fields have different requirements for the switching and conduction losses of devices, the optimal product of on-resistance (Rdson) and gate charge (Qg) (FOM) is usually used as the standard for evaluating the cost-effectiveness of devices. Summary of the Invention

[0003] This invention provides a Split Gate MOSFET device and its fabrication method. By depositing a silicon oxynitride layer before etching the polysilicon layer at the source, and then using a thermal oxidation process to optimize the device structure, the device dynamic parameters can be further reduced without increasing the on-resistance, resulting in a lower optimal device value and higher cost-effectiveness.

[0004] This invention provides a Split Gate MOSFET device, comprising:

[0005] A first trench and a second trench are provided in the first conductive epitaxial layer.

[0006] The first trench includes a first gate oxide layer and a first polysilicon layer from the outside to the inside;

[0007] The second trench is divided into an upper part and a lower part from bottom to top by a second gate oxide layer. The lower part of the second trench includes a first gate oxide layer and a first polysilicon layer from the outside to the inside. The upper part of the second trench includes a second polysilicon layer, a second gate oxide layer and an isolation oxide layer from the outside to the inside.

[0008] A second gate oxide layer, a silicon oxynitride layer, an isolation oxide layer, and a metal layer are sequentially disposed on the first conductive epitaxial layer;

[0009] A contact hole is provided on the second groove, between the first groove and the second groove, and on the side of the second groove away from the first groove.

[0010] Preferably, it further includes a second conductivity type body region and a first conductivity type source region;

[0011] A second conductivity type body region is included between the first trench and the second trench;

[0012] The side of the second trench away from the first trench includes, from bottom to top, a second conductivity type body region and a first conductivity type source region;

[0013] The lower surface of the second conductive type body region is higher than the upper surface of the first polysilicon layer located in the second trench.

[0014] Preferably, the contact holes are respectively a first contact hole, a second contact hole, and a third contact hole;

[0015] The first contact hole is located on the first trench, and one end of it penetrates the silicon oxynitride layer and the second gate oxide layer and contacts the first polysilicon layer disposed in the first trench;

[0016] The second contact hole is located between the first trench and the second trench, and one end of it penetrates the silicon oxynitride layer, the second gate oxide layer and contacts the second conductivity type body region;

[0017] The third contact hole is located on the side of the second trench away from the first trench, and one end of it penetrates through the silicon oxynitride layer, the second gate oxide layer, the source region of the first conductivity type, and the body region of the second conductivity type to make contact.

[0018] This invention provides a method for fabricating a Split Gate MOSFET device, comprising:

[0019] A second photoresist layer is formed at the top of the first trench and on both sides of the top. The first gate oxide layer in the second trench and on both sides of the top of the second trench are etched by an etching method. The second photoresist layer is removed, and a second gate oxide layer is formed in the second trench, on both sides of the top of the second trench, at the top of the first trench, and on both sides of the top of the first trench by a thermal oxidation process.

[0020] A second polysilicon layer is formed in the second trench and above the second gate oxide layer; a silicon oxynitride layer and a third photoresist layer are formed at the top of the first trench, on both sides of the top of the first trench, at the top of the second trench, and on both sides of the top of the second trench; the silicon oxynitride layer, the second gate oxide layer, and the first polysilicon layer at the top of the second trench and in the second trench are etched by an etching method.

[0021] A second conductivity type body region is formed between the second trench and the first trench by ion implantation. A second conductivity type body region and a first conductivity type source region are formed from bottom to top on the side of the second trench away from the first trench. An isolation oxide layer is formed above the silicon oxynitride layer, and contact holes are formed on the isolation oxide layer.

[0022] Preferably, the step of removing the second photoresist layer and forming a second gate oxide layer in the second trench, on both sides of the top of the second trench, on the top of the first trench, and on both sides of the top of the first trench via a thermal oxidation process specifically includes:

[0023] The second photoresist layer is removed, and the top of the first trench retains the first gate oxide layer and the first polysilicon layer, and the side of the first trench away from the second trench retains the first gate oxide layer.

[0024] A second gate oxide layer is formed on both sides of the top of the second trench through a thermal oxidation process.

[0025] Through a thermal oxidation process, the first polysilicon layer at the top of the first trench is oxidized to form a second gate oxide layer, and the first gate oxide layer at the top of the first trench and the first gate oxide layer on the side of the first trench away from the second trench form a second gate oxide layer.

[0026] The height of the second gate oxide layer located at the top of the first trench and on the side of the first trench away from the second trench is higher than the height of the second gate oxide layer located at the top of the second trench and on both sides of the second trench.

[0027] Preferably, before forming the second photoresist layer on the top and both sides of the first trench, the method further includes:

[0028] The first polysilicon layer on the first conductive epitaxial layer is removed by etching, so that the upper surface of the first polysilicon layer in the first trench and the first polysilicon layer in the second trench has the same height as the upper surface of the first gate oxide layer on the first conductive epitaxial layer.

[0029] Preferably, the etching of the first gate oxide layer within the second trench and the first gate oxide layer on both sides of the top of the second trench using an etching method specifically includes:

[0030] The first gate oxide layer located in the second trench is etched so that the upper portion of the first gate oxide layer located in the second trench is etched;

[0031] The first gate oxide layer located on both sides of the top of the second trench is etched so that the first gate oxide layer located on both sides of the top of the second trench is etched; wherein, there is a gap between the lower surface of the second photoresist located between the first trench and the second trench and the upper surface of the first conductive epitaxial layer.

[0032] Preferably, the etching of the top of the second trench and the silicon oxynitride layer, the second gate oxide layer, and the first polysilicon layer within the second trench using an etching method specifically includes:

[0033] The silicon oxynitride layer located at the top of the second trench is first etched using an etching method.

[0034] The second gate oxide layer and the first polysilicon layer located in the second trench are etched so that the upper surface of the etched first polysilicon layer and the lower surface of the second polysilicon layer have the same height.

[0035] Preferably, prior to ion implantation, the procedure further includes:

[0036] A second gate oxide layer is formed by oxidizing the inner side of the second polysilicon layer located in the second trench through a thermal oxidation process, and the upper surface of the first polysilicon layer is oxidized to form the second gate oxide layer.

[0037] The second gate oxide layer located on the upper surface of the first polysilicon layer is in contact with the first gate oxide layer located below the second polysilicon layer.

[0038] Preferably, the step of forming a second conductivity type body region between the second trench and the first trench through ion implantation, and forming a second conductivity type body region and a first conductivity type source region from bottom to top on the side of the second trench away from the first trench, specifically includes:

[0039] Through the first ion implantation, a second conductivity type body region is formed on the side of the second trench away from the first trench, between the second trench and the first trench, and the lower surface of the second conductivity type body region is higher than the upper surface of the first polysilicon layer located in the second trench.

[0040] A first conductivity type source region is formed on the side of the second trench away from the first trench by a second ion implantation. The first conductivity type source region is located within the second conductivity type body region, and the upper surface of the first conductivity type source region has the same height as the upper surface of the first conductivity type epitaxial layer.

[0041] This invention provides a Split Gate MOSFET device and its fabrication method. The fabrication method includes: forming a second photoresist layer at the top and both sides of a first trench; etching a first gate oxide layer in the second trench and the first gate oxide layer on both sides of the top of the second trench using an etching method; removing the second photoresist layer; forming a second gate oxide layer in the second trench, on both sides of the top of the second trench, at the top of the first trench, and on both sides of the top of the first trench using a thermal oxidation process; forming a second polysilicon layer in the second trench and above the second gate oxide layer; and forming a second polysilicon layer at the top of the first trench and on both sides of the top of the first trench. A silicon oxynitride layer and a third photoresist layer are formed on both sides of the top of the first trench, the top of the second trench, and both sides of the top of the second trench. The silicon oxynitride layer, the second gate oxide layer, and the first polysilicon layer on the top of the second trench and inside the second trench are etched by an etching method. A second conductivity type body region is formed between the second trench and the first trench by ion implantation. A second conductivity type body region and a first conductivity type source region are formed from bottom to top on the side of the second trench away from the first trench. An isolation oxide layer is formed above the silicon oxynitride layer, and contact holes are formed on the isolation oxide layer. This method can optimize the device structure by depositing a silicon oxynitride layer before etching the first polysilicon layer and then using a thermal oxidation process. This achieves the goal of further reducing the device's dynamic parameters without increasing the on-resistance, thereby ultimately reducing the device's optimal value and providing a higher cost-performance ratio. Furthermore, this method can further reduce the device's dynamic parameters by appropriately adjusting the height of the first polysilicon layer in the second trench. Moreover, due to the introduction of the silicon oxynitride layer in this fabrication method, it is an excellent isolation layer material that can effectively reduce the entry of metal ions, mobile ions, and charged particles into the device, thus giving the device high stability. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1AThis is a schematic diagram of the Split Gate MOSFET device structure provided in an embodiment of the present invention;

[0044] Figure 1B A schematic diagram of the gate bus fingerpick-up structure included in the Split Gate MOSFET device provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the fabrication process of the Split Gate MOSFET device provided in an embodiment of the present invention;

[0046] Figure 3A This is a schematic diagram of the structure for fabricating a first oxide layer on a first conductive epitaxial layer, provided in an embodiment of the present invention.

[0047] Figure 3B This is a schematic diagram of the trench fabrication provided in an embodiment of the present invention;

[0048] Figure 3C This is a schematic diagram of the fabrication of the first gate oxide layer in the trench provided by an embodiment of the present invention;

[0049] Figure 3D This is a schematic diagram of the fabrication of a first polycrystalline silicon layer in a trench, provided in an embodiment of the present invention;

[0050] Figure 3E This is a schematic diagram of the etching of the first polysilicon layer provided in an embodiment of the present invention;

[0051] Figure 3F This is a schematic diagram of the preparation of the second photoresist layer provided in an embodiment of the present invention;

[0052] Figure 3G This is a schematic diagram of the etching of the first gate oxide layer provided in an embodiment of the present invention;

[0053] Figure 3H This is a schematic diagram of the fabrication of the second gate oxide layer provided in an embodiment of the present invention;

[0054] Figure 3I This is a schematic diagram of the fabrication of the second polycrystalline silicon layer provided in an embodiment of the present invention;

[0055] Figure 3J This is a schematic diagram of the etching of the second polysilicon layer provided in an embodiment of the present invention;

[0056] Figure 3K This is a schematic diagram of the preparation of the silicon oxynitride layer provided in an embodiment of the present invention;

[0057] Figure 3L This is a schematic diagram of the preparation of the third photoresist layer provided in an embodiment of the present invention;

[0058] Figure 3MThis is a schematic diagram of the etching of the second gate oxide layer and the first polysilicon layer in the second trench provided in an embodiment of the present invention;

[0059] Figure 3N This is a schematic diagram of the removal of the third photoresist layer provided in an embodiment of the present invention;

[0060] Figure 3O This is a schematic diagram of two ion implantations provided in an embodiment of the present invention;

[0061] Figure 3P This is a schematic diagram illustrating the preparation of the isolation oxide layer provided in an embodiment of the present invention;

[0062] Figure 3Q This is a schematic diagram of the preparation of contact holes provided in an embodiment of the present invention;

[0063] Figure 3R This is a schematic diagram of the preparation of the metal layer provided in an embodiment of the present invention;

[0064] Wherein, 101-first conductivity type substrate layer; 102-first conductivity epitaxial layer; 103-first oxide layer; 105-1-first trench; 105-2-second trench; 106-1-first gate oxide layer; 107-1-first polysilicon layer; 106-2-second gate oxide layer; 107-2-second polysilicon layer; 108-second photoresist layer; 109-silicon oxynitride layer; 110-first photoresist layer; 111-second conductivity type body region; 112-first conductivity type source region; 113-isolation oxide layer; 114-contact hole; 115-metal layer. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Figure 1A This is a schematic diagram of the Split Gate MOSFET device structure provided in an embodiment of the present invention; Figure 1B A schematic diagram of the gate bus finger pick-up structure included in the Split Gate MOSFET device provided in this embodiment of the invention; as shown. Figure 1A and Figure 1BAs shown, the Split Gate MOSFET device mainly includes a first trench 105-1, a second trench 105-2, a first conductive epitaxial layer 102, a first polysilicon layer 107-1, a second polysilicon layer 107-2, a first gate oxide layer 106-1, a second gate oxide layer 106-2, a silicon oxynitride layer 109, a second conductivity type body region 111, and a first conductivity type source region 112.

[0067] Specifically, the openings of the first trench 105-1 and the second trench 105-2 have the same height as the upper surface of the first conductive epitaxial layer 102, that is, the openings of the first trench 105-1 and the second trench 105-2 are located on the upper surface of the first conductive epitaxial layer 102; and the lower ends of the first trench 105-1 and the second trench 105-2 extend into the first conductive epitaxial layer 102.

[0068] Furthermore, the first trench 105-1 is provided with a first gate oxide layer 106-1, a first polysilicon layer 107-1, and a contact hole 114 sequentially from the outside to the inside; the lower half of the second trench 105-2 is provided with a first gate oxide layer 106-1 and a first polysilicon layer 107-1 from the outside to the inside, and the upper half is provided with a second polysilicon layer 107-2, a second gate oxide layer 106-2, and an isolation oxide layer 113 from the outside to the inside, and a second gate oxide layer 106-2 is provided between the first polysilicon layer 107-1 and the second polysilicon layer 107-2, that is, the second trench 105-2 is divided into an upper half and a lower half from top to bottom by the second gate oxide layer 106-2 provided between the first polysilicon layer 107-1 and the second polysilicon layer 107-2.

[0069] Furthermore, a second gate oxide layer 106-2, a silicon oxynitride layer 109, an isolation oxide layer 113, and a metal layer 115 are sequentially disposed above the first conductive epitaxial layer 102.

[0070] In this embodiment of the invention, by setting a silicon oxynitride layer 109 above the second gate oxide layer 106-2, i.e., before etching the first polysilicon layer 107-1 within the second trench 105-2, the device structure can be optimized using a thermal oxidation process. This achieves the goal of further reducing the device's dynamic parameters without increasing the on-resistance, ultimately resulting in a lower optimal device value and higher cost-effectiveness. Furthermore, this method can further reduce the device's dynamic parameters by appropriately adjusting the height of the first polysilicon layer 107-1 within the second trench 105-2. Moreover, the introduction of the silicon oxynitride layer 109 in this fabrication method provides an excellent insulating layer material, effectively reducing the entry of metal ions, mobile ions, and charged particles into the device, thus ensuring high device stability.

[0071] Furthermore, a second conductive type body region 111 and a first conductive type source region 112 are distributed on the side of the second trench 105-2 away from the first trench 105-1, wherein the first conductive type source region 112 is located within the second conductive type body region 111, and the first conductive type source region 112, the second conductive type body region 111 and the upper surface of the first conductive epitaxial layer 102 have the same height; the second conductive type body region 111 is disposed between the second trench 105-2 and the first trench 105-1.

[0072] Furthermore, the first contact hole 114 is located on the first trench 105-1, with one end penetrating through the silicon oxynitride layer 109 and the second gate oxide layer 106-2 and contacting the first polysilicon layer 107-1 disposed in the first trench 105-1; the second contact hole 114 is located between the first trench 105-1 and the second trench 105-2, with one end penetrating through the silicon oxynitride layer 109 and the second gate oxide layer 106-2 and contacting the second conductivity type body region 111; the third contact hole 114 is located on the side of the second trench 105-2 away from the first trench 105-1, with one end penetrating through the silicon oxynitride layer 109, the second gate oxide layer 106-2, the first conductivity type source region 112 and contacting the second conductivity type body region 111.

[0073] Figure 2 This is a schematic diagram of the fabrication process of the Split Gate MOSFET device provided in an embodiment of the present invention; Figure 3A This is a schematic diagram of the structure for fabricating a first oxide layer on a first conductive epitaxial layer, provided in an embodiment of the present invention. Figure 3B This is a schematic diagram of the trench fabrication provided in an embodiment of the present invention; Figure 3C This is a schematic diagram of the fabrication of the first gate oxide layer in the trench provided by an embodiment of the present invention; Figure 3D This is a schematic diagram of the fabrication of a first polycrystalline silicon layer in a trench, provided in an embodiment of the present invention; Figure 3E This is a schematic diagram of the etching of the first polysilicon layer provided in an embodiment of the present invention; Figure 3F This is a schematic diagram of the preparation of the second photoresist layer provided in an embodiment of the present invention; Figure 3G This is a schematic diagram of the etching of the first gate oxide layer provided in an embodiment of the present invention; Figure 3H This is a schematic diagram of the fabrication of the second gate oxide layer provided in an embodiment of the present invention; Figure 3I This is a schematic diagram of the fabrication of the second polycrystalline silicon layer provided in an embodiment of the present invention; Figure 3J This is a schematic diagram of the etching of the second polysilicon layer provided in an embodiment of the present invention; Figure 3K This is a schematic diagram of the preparation of the silicon oxynitride layer provided in an embodiment of the present invention; Figure 3L This is a schematic diagram of the preparation of the third photoresist layer provided in an embodiment of the present invention; Figure 3M This is a schematic diagram of the etching of the second gate oxide layer and the first polysilicon layer in the second trench provided in an embodiment of the present invention; Figure 3N This is a schematic diagram of the removal of the third photoresist layer provided in an embodiment of the present invention; Figure 3O This is a schematic diagram of two ion implantations provided in an embodiment of the present invention; Figure 3P This is a schematic diagram illustrating the preparation of the isolation oxide layer provided in an embodiment of the present invention; Figure 3Q This is a schematic diagram of the preparation of contact holes provided in an embodiment of the present invention; Figure 3R This is a schematic diagram of the preparation of the metal layer provided in an embodiment of the present invention;

[0074] The following is Figure 2 The provided method for fabricating Split Gate MOSFET devices, combined with Figures 3A to 3R The provided fabrication diagrams illustrate the detailed fabrication method of Split Gate MOSFET devices, specifically as follows: Figure 2 As shown, the method mainly includes the following steps:

[0075] Specifically, such as Figure 3A As shown, a first conductive epitaxial layer 102 is formed on the provided first conductive substrate layer, and a first oxide layer 103 is generated on the first conductive epitaxial layer 102 as a barrier layer for trench etching.

[0076] In this embodiment of the invention, a first conductivity type substrate layer may be provided first, and a first conductive epitaxial layer may be generated on the first conductivity type substrate layer. The first conductivity type substrate layer may be an N-type substrate or a P-type substrate. When the first conductivity type substrate layer is an N-type substrate, the first conductive epitaxial layer disposed on the N-type substrate is an N-type epitaxial layer; when the first conductivity type substrate layer is a P-type substrate, the first conductive epitaxial layer disposed on the P-type substrate is a P-type epitaxial layer.

[0077] A first photoresist layer is formed on the first oxide layer 103, and the opening positions of the first trench and the second trench are defined by the first photoresist layer. Then, the first oxide layer 103 is etched to the upper surface of the first conductive epitaxial layer 102, that is, the first oxide layer 103 on the first conductive epitaxial layer 102 is etched into the shape of trenches.

[0078] like Figure 3B As shown, a first trench 105-1 and a second trench 105-2 are etched within the first conductive epitaxial layer 102. It should be noted that the first trench 105-1 is located in the terminal region within the first conductive epitaxial layer 102, and the second trench 105-2 is located in the region within the first conductive epitaxial layer 102.

[0079] Furthermore, the first photoresist layer and the first oxide layer 103 located on the upper surface of the first conductive epitaxial layer 102 are removed, and a sacrificial oxide layer is generated inside the first trench 105-1, inside the second trench 105-2, and on the upper surface of the first conductive epitaxial layer 102. It should be noted that the sacrificial oxide layer is located at the bottom and sidewalls of the first trench 105-1 and the second trench 105-2.

[0080] like Figure 3C As shown, the sacrificial oxide layer is removed, and then a first gate oxide layer 106-1 is formed inside the first trench 105-1, inside the second trench 105-2, and on the upper surface of the first conductive epitaxial layer 102. The first gate oxide layer 106-1 is located on the bottom and sidewalls of the first trench 105-1 and the second trench 105-2.

[0081] like Figure 3D and Figure 3E As shown, a first polysilicon layer 107-1 is formed in the first trench 105-1, the second trench 105-2, and the top side of the two trenches. The first polysilicon layer 107-1 is etched for the first time by dry etching, that is, the first polysilicon layer 107-1 located on both sides of the two trenches is removed, that is, only the first polysilicon layer 107-1 in the first trench 105-1 and the second trench 105-2 is retained. After etching, the upper surface of the first polysilicon layer 107-1 located in the first trench 105-1 and the second trench 105-2 has the same height as the upper surface of the first gate oxide layer 106-1 disposed above the first conductive epitaxial layer 102.

[0082] It should be noted that the first gate oxide layer here is liner oxide, and the first polysilicon layer is sourcepoly.

[0083] Step 21: A second photoresist layer is formed at the top of the first trench and on both sides of the top. The first gate oxide layer in the second trench and on both sides of the top of the second trench are etched by an etching method. The second photoresist layer is removed, and a second gate oxide layer is formed in the second trench, on both sides of the top of the second trench, at the top of the first trench, and on both sides of the top of the first trench by a thermal oxidation process.

[0084] Specifically, such as Figure 3F As shown, a second photoresist layer 108 is formed on the top of the first trench 105-1 and on both sides of the top of the first trench 105-1. That is, the second photoresist layer 108 covers the top of the first trench 105-1 and both sides of the first trench 105-1. It should be noted that the second photoresist only covers a part of the first trench 105-1 and the second trench 105-2, that is, the side closer to the second trench 105-2 is not covered by the second photoresist.

[0085] like Figure 3G As shown, the first gate oxide layer 106-1 inside the second trench 105-2 and on both sides of the top of the second trench 105-2 is etched. Specifically, the first gate oxide layer 106-1 located inside the second trench 105-2 is etched such that the upper surface of the first gate oxide layer 106-1 inside the second trench 105-2 is lower than the upper surface of the first polysilicon layer 107-1 inside the second trench 105-2, wherein the upper surface of the first polysilicon layer 107-1 inside the second trench 105-2 has the same height as the upper surface of the first conductive epitaxial layer 102. Furthermore, the first gate oxide layer 106-1 on both sides of the top of the second trench 105-2 is etched away, so that the first gate oxide layer 106-1 on both sides of the top of the second trench 105-2 is etched away. It should be noted that since part of the second photoresist is located between the first trench and the second trench, after the first gate oxide layer between the first trench and the second trench is etched away, there will be a gap between the lower surface of the second photoresist located between the first trench and the second trench and the upper surface of the first conductive epitaxial layer.

[0086] It should be noted that the etching depth of the first gate oxide layer in the second trench can be determined according to specific process parameters. In this embodiment of the invention, the etching depth of the first gate oxide layer in the second trench is not specifically limited.

[0087] Furthermore, such as Figure 3H As shown, when the second photoresist is removed, since only the first gate oxide layer 106-1 inside the second trench 105-2 and on both sides of the top of the second trench 105-2 were etched, the top of the first trench 105-1 still includes the first gate oxide layer 106-1 and the first polysilicon layer 107-1 after the second photoresist is removed. Similarly, the first gate oxide layer 106-1 is still retained on the side of the first trench 105-1 away from the second trench 105-2.

[0088] Furthermore, through a thermal oxidation process, a high-quality gate oxide layer, referred to here as the second gate oxide layer 106-2, is formed within the second trench 105-2, on both sides of the top of the second trench 105-2, and on the top of the first trench 105-1. It should be noted that the second gate oxide layer formed within the second trench is located on the upper surface of the first gate oxide layer, on both sides of the second trench, and on the upper surface of the first polysilicon layer; the second gate oxide layer formed on both sides of the top of the second trench is located on the upper surface of the first conductive epitaxial layer; the second gate oxide layer formed at the top of the first trench is located on the upper surfaces of the first gate oxide layer and the first polysilicon layer; and the second gate oxide layer formed on the side of the first trench away from the second trench is located on the upper surface of the first gate oxide layer. Based on this, it can be determined that the height of the second gate oxide layer located at the top of the first trench and on the side of the first trench away from the second trench is higher than the height of the second gate oxide layer located at the top of the second trench and on both sides of the second trench.

[0089] Step 22: A second polysilicon layer is formed in the second trench and above the second gate oxide layer; a silicon oxynitride layer and a third photoresist layer are formed at the top of the first trench, on both sides of the top of the first trench, at the top of the second trench, and on both sides of the top of the second trench; the silicon oxynitride layer, the second gate oxide layer, and the first polysilicon layer at the top of the second trench and in the second trench are etched by an etching method.

[0090] Specifically, such as Figure 3I As shown, through a deposition process, a heavily doped gate polysilicon layer, namely the second polysilicon layer, is formed on the top of the first trench 105-1, on both sides of the first trench 105-1, inside the second trench 105-2, and on both sides of the top of the second trench 105-2. Here, the second polysilicon layer is called gate poly.

[0091] Furthermore, such as Figure 3J As shown, the second polysilicon layer 107-2 located on the top two sides of the first trench 105-1 and the top two sides of the second trench 105-2 is etched away. Specifically, the upper surface of the second trench 105-2 includes the second polysilicon layer 107-2 and the second gate oxide layer 106-2 from the outside to the inside, while the upper surface of the first trench 105-1 only includes the second gate oxide layer 106-2. The top two sides of the second trench 105-2 and the top two sides of the first trench 105-1 only include the second gate oxide layer 106-2.

[0092] like Figure 3KAs shown, a silicon oxynitride layer 109 is deposited on the top of the second trench 105-2, on both sides of the top of the second trench 105-2, on the top of the first trench 105-1, and on both sides of the top of the first trench 105-1, that is, a silicon oxynitride layer is deposited on the upper surface of the second gate oxide layer 106-2 and the second polysilicon layer 107-2.

[0093] In this embodiment of the invention, a silicon oxynitride layer is deposited, and then a thermal oxidation process is used to optimize the device structure, so as to further reduce the dynamic parameters of the device (such as gate charge Qg) without increasing the on-resistance, thereby ultimately reducing the device's optimal value FOM and achieving a higher cost-performance ratio.

[0094] like Figure 3L As shown, a third photoresist layer 110 is formed on the top of the first trench 105-1, on both sides of the top of the first trench 105-1, on the top of the second trench 105-2, and on both sides of the top of the second trench 105-2, that is, on the upper surface of the silicon oxynitride layer 109. It should be noted that the third photoresist leaves a window on the upper surface of the second trench where the silicon oxynitride layer needs to be etched.

[0095] like Figure 3M As shown, the second gate oxide layer 106-2 on top of the first polysilicon layer 107-1 and the silicon oxynitride layer 109 above the second gate oxide layer 106-2 are etched away by dry etching. Then, the etching depth of the first polysilicon layer 107-1 is determined according to the process parameters. Here, the etching depth of the first polysilicon layer 107-1 is not limited.

[0096] Furthermore, such as Figure 3N As shown, the third photoresist is removed, and a thermal oxidation process is used to oxidize the first polysilicon layer 107-1 located inside the second polysilicon layer 107-2 in the second trench 105-2 to form a second gate oxide layer 106-2. The upper surface of the first polysilicon layer 107-1 is oxidized to form the second gate oxide layer 106-2. Specifically, the second gate oxide layer 106-2 located on the upper surface of the first polysilicon layer 107-1 is in contact with the first gate oxide layer 106-1 located below the second polysilicon layer 107-2.

[0097] It should be noted that in the above steps, the silicon oxynitride layer formed above the second gate oxide layer can protect the surface silicon from oxidation during the thermal oxidation process, and only the first polysilicon layer remaining on the sidewall of the second trench will be completely oxidized.

[0098] Step 23: By ion implantation, a second conductivity type body region is formed between the second trench and the first trench. The second conductivity type body region and the first conductivity type source region are formed from bottom to top on the side of the second trench away from the first trench. An isolation oxide layer is formed above the silicon oxynitride layer, and contact holes are prepared on the isolation oxide layer.

[0099] Specifically, such as Figure 3O As shown, a second conductive type body region 111 photoresist layer, i.e., the fourth photoresist layer, is formed on the silicon oxynitride layer 109 using photolithography. Specifically, the third photoresist layer 110 is located on the side of the first trench 105-1 away from the second trench 105-2 and at the top of the first trench 105-1. The implantation region of the second conductive type body region 111 is defined in the first conductive epitaxial layer 102 using photolithography. A first ion implantation is performed into the first conductive epitaxial layer 102. After removing the fourth photoresist, the second conductive type body region 111 is pushed to the required junction depth using a thermal push trap, forming the second conductive type body region 111 within the first conductive epitaxial layer 102 on both sides of the second trench 105-2. It should be noted that the lower surface of the second conductive type body region is higher than the upper surface of the first polysilicon layer located in the second trench, i.e., the junction depth is located above the bottom of the gate polysilicon layer.

[0100] A first conductivity type source region 112 photolithography layer, i.e., a fifth photoresist layer, is formed on the silicon oxynitride layer 109 using a photolithography process. Specifically, the fifth photoresist layer is located at the top of the first trench 105-1, on both sides of the top of the first trench 105-1, between the second trench 105-2 and the first trench 105-1, and at the top of the first trench. After defining the implantation region of the first conductivity type source region 112, a second ion implantation is performed into the first conductive epitaxial layer 102 to form the first conductivity type source region 112 within the first conductive epitaxial layer 102.

[0101] like Figure 3P As shown, after the second conductivity type body region 111 and the first conductivity type source region 112 are sequentially formed in the first conductive epitaxial layer 102, an isolation oxide layer 113 is formed on the upper surface of the silicon oxynitride layer 109, and an isolation oxide layer 113 is also formed above the second gate oxide layer 106-2 in the second trench 105-2. In this embodiment of the invention, the isolation oxide layer is BPSG.

[0102] like Figure 3QAs shown, after the isolation oxide layer 113 is formed, a sixth photoresist layer is formed on the isolation oxide layer 113. The position of the contact hole 114 is defined by the photoresist, and the contact hole 114 is formed on the isolation oxide layer 113. The first contact hole 114 is located on the first trench 105-1, with one end penetrating through the silicon oxynitride layer 109 and the second gate oxide layer 106-2 and contacting the first polysilicon layer 107-1 disposed in the first trench 105-1; the second contact hole 114 is located between the first trench 105-1 and the second trench 105-2, with one end penetrating through the silicon oxynitride layer 109 and the second gate oxide layer 106-2 and contacting the second conductivity type body region 111; the third contact hole 114 is located on the side of the second trench 105-2 away from the first trench 105-1, with one end penetrating through the silicon oxynitride layer 109, the second gate oxide layer 106-2, the first conductivity type source region 112 and contacting the second conductivity type body region 111.

[0103] Furthermore, a Ti / TiN layer is deposited on the isolation oxide layer, and then a good ohmic contact is formed on the contact hole surface through a suitable high-temperature process. A tungsten layer is then deposited, and the surface tungsten metal of the isolation oxide layer is removed by an etching process.

[0104] like Figure 3R As shown, a metal layer 115 is deposited above the isolation oxide layer 113. Then, the source metal region and the gate metal region are defined by photolithography, and the source metal layer 115 and the gate metal layer 115 are defined by etching, forming as shown. Figure 1A The active region periphery and Figure 1B The optimized structural morphology of the gate bus finger pick-up position is shown.

[0105] It should be noted that the silicon oxynitride layer formed above the second gate oxide layer in the above steps is an excellent insulating oxide layer material, which can effectively reduce the entry of metal ions, mobile ions and charged particles into the device, thus giving the device high stability.

[0106] In summary, the embodiments of the present invention provide a Split Gate MOSFET device and a fabrication method. The fabrication method includes: forming a second photoresist layer at the top and on both sides of a first trench; etching a first gate oxide layer in the second trench and the first gate oxide layer on both sides of the top of the second trench using an etching method; removing the second photoresist layer; forming a second gate oxide layer in the second trench, on both sides of the top of the second trench, at the top of the first trench, and on both sides of the top of the first trench using a thermal oxidation process; forming a second polysilicon layer in the second trench and above the second gate oxide layer; forming a second polysilicon layer at the top of the first trench and on both sides of the top of the second trench; and forming a second polysilicon layer at the top of the first trench and on both sides of the top of the second trench. A silicon oxynitride layer and a third photoresist layer are formed on both sides of the top of the first trench, the top of the second trench, and both sides of the top of the second trench. The silicon oxynitride layer, the second gate oxide layer, and the first polysilicon layer on the top of the second trench and inside the second trench are etched by an etching method. A second conductivity type body region is formed between the second trench and the first trench by ion implantation. A second conductivity type body region and a first conductivity type source region are formed from bottom to top on the side of the second trench away from the first trench. An isolation oxide layer is formed above the silicon oxynitride layer, and contact holes are formed on the isolation oxide layer. This method can optimize the device structure by depositing a silicon oxynitride layer before etching the first polysilicon layer and then using a thermal oxidation process. This achieves the goal of further reducing the device's dynamic parameters without increasing the on-resistance, thereby ultimately reducing the device's optimal value and providing a higher cost-performance ratio. Furthermore, this method can further reduce the device's dynamic parameters by appropriately adjusting the height of the first polysilicon layer in the second trench. Moreover, due to the introduction of the silicon oxynitride layer in this fabrication method, it is an excellent isolation layer material that can effectively reduce the entry of metal ions, mobile ions, and charged particles into the device, thus giving the device high stability.

[0107] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0108] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method of fabricating a split gate MOSFET device, characterized by, The method comprises the following steps: forming a second photoresist layer on the top of the first trench and the two sides of the top of the first trench, etching the first gate oxide layer in the second trench and the first gate oxide layer on the two sides of the top of the second trench by an etching method; removing the second photoresist layer and forming a second gate oxide layer in the second trench, on the two sides of the top of the second trench, on the top of the first trench and on the two sides of the top of the first trench by a thermal oxidation process; forming a second polysilicon layer in the second trench and above the second gate oxide layer, forming a silicon oxynitride layer and a third photoresist layer on the top of the first trench, on the two sides of the top of the first trench, on the top of the second trench and on the two sides of the top of the second trench, and etching the silicon oxynitride layer, the second gate oxide layer and the first polysilicon layer on the top of the second trench and in the second trench by an etching method; forming a second conductive type body region between the second trench and the first trench by ion implantation, and forming a second conductive type body region and a first conductive type source region from bottom to top on the side of the second trench away from the first trench; forming an isolation oxide layer above the silicon oxynitride layer and preparing a contact hole on the isolation oxide layer; before the ion implantation, the method further comprises the following steps: forming the second gate oxide layer by a thermal oxidation process, so that the inner side of the second polysilicon layer in the second trench is oxidized to form the second gate oxide layer, and the upper surface of the first polysilicon layer is oxidized to form the second gate oxide layer; wherein the second gate oxide layer on the upper surface of the first polysilicon layer is in contact with the first gate oxide layer below the second polysilicon layer.

2. The production method according to claim 1, wherein The method further comprises the following steps of removing the second photoresist layer and forming a second gate oxide layer in the second trench, on the two sides of the top of the second trench, on the top of the first trench and on the two sides of the top of the first trench by a thermal oxidation process: removing the second photoresist layer, and the first gate oxide layer and the first polysilicon layer are reserved on the top of the first trench, and the first gate oxide layer is reserved on the side of the first trench away from the second trench; forming a second gate oxide layer in the second trench and on the two sides of the top of the second trench by a thermal oxidation process; forming a second gate oxide layer by a thermal oxidation process, so that the first polysilicon layer on the top of the first trench is oxidized to form the second gate oxide layer, and the first gate oxide layer on the top of the first trench and the first gate oxide layer on the side of the first trench away from the second trench form the second gate oxide layer; wherein the height of the second gate oxide layer on the top of the first trench and on the side of the first trench away from the second trench is higher than the height of the second gate oxide layer on the top of the second trench and on the two sides of the second trench.

3. The production method according to claim 1, wherein Before the step of forming a second photoresist layer on the top of the first trench and on the two sides of the top of the first trench, the method further comprises the following step: removing the first polysilicon layer on the first conductive epitaxial layer by an etching method, so that the upper surface of the first polysilicon layer in the first trench and the first polysilicon layer in the second trench has the same height as the upper surface of the first gate oxide layer on the first conductive epitaxial layer.

4. The production method according to claim 1, wherein The etching method is used to etch the first gate oxide layer in the second trench and the first gate oxide layer on both sides of the top of the second trench, specifically including: The first gate oxide layer in the second trench is etched so that the upper part of the first gate oxide layer in the second trench is etched; The first gate oxide layer on both sides of the top of the second trench is etched so that the first gate oxide layer on both sides of the top of the second trench is etched; wherein there is a gap between the lower surface of the second photoresist between the first trench and the second trench and the upper surface of the first conductive epitaxial layer.

5. The production method according to claim 1, wherein The etching method is used to etch the silicon oxynitride layer, the second gate oxide layer and the first polysilicon layer in the second trench and on the top of the second trench, specifically including: The silicon oxynitride layer on the top of the second trench is etched by the etching method; The second gate oxide layer and the first polysilicon layer in the second trench are etched so that the upper surface of the etched first polysilicon layer has the same height as the lower surface of the second polysilicon layer.

6. The production method according to claim 1, wherein The ion implantation is used to form a second conductive type body region between the second trench and the first trench, and a first conductive type source region from bottom to top on the side of the second trench away from the first trench, specifically including: The first ion implantation is used to form a second conductive type body region on the side of the second trench away from the first trench and between the second trench and the first trench, and the lower surface of the second conductive type body region is higher than the upper surface of the first polysilicon layer in the second trench; The second ion implantation is used to form a first conductive type source region on the side of the second trench away from the first trench, the first conductive type source region is located in the second conductive type body region, and the upper surface of the first conductive type source region has the same height as the upper surface of the first conductive epitaxial layer.

7. A split gate MOSFET device characterized by The SplitGate MOSFET device prepared by the preparation method of any one of claims 1-6, the device comprising: A first conductive epitaxial layer is provided with a first trench and a second trench; The first trench comprises a first gate oxide layer and a first polysilicon layer from outside to inside; The second trench is divided into an upper part and a lower part by a second gate oxide layer from bottom to top, the lower part of the second trench comprises a first gate oxide layer and a first polysilicon layer from outside to inside, and the upper part of the second trench comprises a second polysilicon layer, a second gate oxide layer and an isolation oxide layer from outside to inside; The second gate oxide layer, the silicon oxynitride layer, the isolation oxide layer and the metal layer are sequentially arranged on the first conductive epitaxial layer; The contact hole is arranged on the second trench, between the first trench and the second trench, and on the side of the second trench away from the first trench.

8. The Split Gate MOSFET device of claim 7, wherein, It also includes a second conductive type body region and a first conductive type source region; The second conductive type body region is between the first trench and the second trench; The second conductive type body region and the first conductive type source region are included from bottom to top on the side of the second trench away from the first trench; The lower surface of the second conductive type body region is higher than the upper surface of the first polysilicon layer located in the second trench.

9. The Split Gate MOSFET device of claim 8, wherein, The contact holes include a first contact hole, a second contact hole and a third contact hole; The first contact hole is located on the first trench and has one end penetrating the silicon oxynitride layer, the second gate oxide layer and the first polysilicon layer arranged in the first trench to contact; The second contact hole is located between the first trench and the second trench and has one end penetrating the silicon oxynitride layer, the second gate oxide layer and the second conductive type body region to contact; The third contact hole is located on the side of the second trench away from the first trench and has one end penetrating the silicon oxynitride layer, the second gate oxide layer, the first conductive type source region and the second conductive type body region to contact.

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