Lower electrode of resistive memory and preparation method thereof

Abstract

The present invention provides a lower electrode of a resistive random access memory and a method for preparing the same. The method comprises: flattening the surface of a bottom dielectric layer to expose all or part of a conductive material layer filled in the dielectric layer; etching back the conductive material layer and performing dry and / or wet cleaning to ensure that the surface height of the conductive material layer is lower than that of the dielectric layer; reducing the conductive material layer exposed on the upper end of the dielectric layer and selectively growing a lower electrode layer on the surface of the conductive material layer, wherein the surface height of the lower electrode layer is not lower than that of the dielectric layer; growing a resistive random access layer and an upper electrode stack on the upper portion of the lower electrode layer, and then sequentially etching the resulting memory infrastructure; and filling the etched memory structure with an intermetallic dielectric and flattening the etched memory structure to complete the preparation of the lower electrode of the resistive random access memory. The above invention can simplify the preparation process of the resistive random access memory and improve the preparation quality.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and more particularly to a lower electrode of a resistive random access memory and a preparation method thereof. Background Art

[0002] In the design process of resistive random access memory (RRAM), in order to obtain better performance (such as device reliability and stability, data retention, high uniformity, and low leakage), the metal film of the bottom electrode (BE) of the RRAM must have a very flat surface with a roughness threshold (Rmax, Maximum Roughness) below 2nm. This prevents a series of problems such as short circuits and uneven cell performance caused by uneven thickness of the resistive switching layer (SL) above the metal film.

[0003] Currently, most existing RRAM structures are metal injection molded (MIM) structures, with both upper and lower electrodes being metal flat plates. The traditional manufacturing process typically involves depositing a lower electrode metal layer, then patterning it through photolithography, etching, and cleaning. The resistive switching layer and upper electrode metal layer are then deposited, followed by masking and etching the upper electrode to form the RRAM device. This existing RRAM structure cannot simultaneously meet the Rmax accuracy requirements for the metal film's top surface and the required thickness for the metal film.

[0004] The existing RRAM structure has two main formation processes:

[0005] The first method generally involves the following main process steps: forming ReRAM and thin film stacks on the planarized BE VIA surface, followed by photolithography, etching, and cleaning to form the ReRAM cell structure. Intermetallic dielectric filling and planarization are then performed to form the final device structure. The main difficulty and problem with this process lies in the etching process. In particular, during the etching of the BE metal film, the metal film is very prone to resputtering and adhering to the cell sidewalls, leading to a series of problems such as short circuits, residues, and defects, resulting in device failure.

[0006] The second method generally goes through the following main process steps: Compared with the first method, Spacer and SpacerEtch are added in order to prevent the influence of BE metal film resputtering on the side wall, specifically: ReRAM film stacks are formed in sequence on the flattened BE VIA surface, and lithography and etching cleaning (Step 4) and other steps are performed. In particular, in the etching and cleaning step, the endpoint stops on the BE metal film, and then the dielectric spacer space isolation layer is formed, and BE W etching is performed. In this way, not only the probability of metal film resputter is reduced, even if splashback occurs, it will not affect the device performance of ReRAM Cell. Finally, the intermetallic dielectric filling and flattening are performed to form the final device structure. The process steps of this process are relatively complex and lengthy, and the main difficulty and problem lies in the Spacer Etch & Wet Clean process. During the etching of the BE metal film and the subsequent cleaning process, the bottom of the cell is prone to side digging problems, resulting in a series of problems such as ReRAM Film Damage & Loss, Undesired Profile, Cell Missing, etc., leading to device failure.

[0007] To solve the above technical problems, there is an urgent need for a method that can not only ensure that the Rmax of the upper surface of the BE metal film of RRAM meets the requirements, but also reduce the difficulty of the ReRAM etching process and its impact on the cell sidewall (grooved sidewall), while also effectively controlling the size of the lower electrode. Summary of the Invention

[0008] In view of the above problems, the purpose of the present invention is to provide a lower electrode of a resistive random access memory and a preparation method to solve the problems existing in the preparation process of the existing resistive random access memory, such as the complexity and length, the susceptibility to undercutting at the bottom of the device, as well as short circuits, residues, defective states, etc., which easily lead to device failure.

[0009] The present invention provides a method for preparing a lower electrode of a resistive random access memory, comprising: flattening the surface of a bottom dielectric layer to expose all or part of a conductive material layer filled in the dielectric layer; etching back the conductive material layer, and performing dry and / or wet cleaning to ensure that the surface height of the conductive material layer is lower than that of the dielectric layer; reducing the conductive material layer exposed on the upper end of the dielectric layer, and selectively growing a lower electrode layer on the surface of the conductive material layer, wherein the surface height of the lower electrode layer is not lower than that of the dielectric layer; growing a resistive random access layer and an upper electrode stack on the upper portion of the lower electrode layer, and sequentially etching the obtained memory basic structure; and filling the etched memory structure with an intermetallic dielectric and flattening the memory structure to complete the preparation of the lower electrode of the resistive random access memory.

[0010] In addition, an optional technical solution is to provide at least one electrode through-hole on the dielectric layer; the conductive material layer is filled in the electrode through-hole, and all or part of the conductive material layer is exposed in the electrode through-hole.

[0011] In addition, an optional technical solution is that the material of the conductive material layer is at least any one of Cu, W, Al, Co, Ru, Au, Ta, Ti, TaN, and TiN.

[0012] In addition, an optional technical solution is to perform a planarization process on the surface of the lower electrode layer after the lower electrode layer is selectively grown on the surface of the conductive material layer.

[0013] In addition, an optional technical solution is to sequentially perform etching processing on the obtained memory infrastructure structure, including: the etching endpoint of the memory infrastructure structure stays on the surface of the resistive switching layer.

[0014] In addition, an optional technical solution is to sequentially perform etching processing on the obtained memory infrastructure structure, including: the etching endpoint of the memory infrastructure structure stays on the upper surface of the dielectric layer.

[0015] In addition, an optional technical solution is to provide a metal wiring layer at the bottom of the electrode through hole; an electrode etching stop layer is provided between the metal wiring layer and the bottom of the conductive material layer; and the height of the electrode etching stop layer is not lower than the height of the metal wiring layer.

[0016] In addition, an optional technical solution is to sequentially perform etching processing on the obtained memory infrastructure structure, including: the etching endpoint of the memory infrastructure structure stops at the electrode etching stop layer.

[0017] In addition, an optional technical solution is that the materials of the intermetallic dielectric, the resistive switching layer, the dielectric layer, the metal wiring layer, and the electrode etching stop layer are respectively the same or different.

[0018] According to another aspect of the present invention, a lower electrode of a resistive random access memory is provided, which is prepared using the above-mentioned method for preparing a lower electrode of a resistive random access memory.

[0019] By utilizing the above-mentioned lower electrode of the resistive random access memory and its preparation method, self-alignment (Self-alignment) of the lower electrode in contact with the conductive material layer can be achieved, which not only effectively reduces the size of the lower electrode, but also expands the optical alignment window (Alignment & Overlay) between the upper and lower electrodes, thereby effectively improving the setting density of the resistive random access memory; in addition, the thickness of the film of the lower electrode layer and the roughness threshold of the surface (especially the upper surface in contact with the resistive random access layer) can be effectively controlled, thereby improving the uniformity and consistency of the surface; at the same time, the lower electrode layer is tightly wrapped and covered by the dielectric layer, so that it will not be damaged by the etching and / or cleaning steps, thereby improving the overall yield.

[0020] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0022] Figure 1 Flowchart of a method for preparing a lower electrode of a resistive random access memory according to an embodiment of the present invention;

[0023] Figure 2 Detailed flow chart of a method for preparing a lower electrode of a resistive random access memory according to an embodiment of the present invention.

[0024] The reference numerals include: electrode through hole 1, dielectric layer 2, conductive material layer 3, lower electrode layer 4, resistive switching layer 5, upper electrode stack 6, electrode etching stop layer 7, and metal wiring layer 8.

[0025] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0026] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0027] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0028] To describe the lower electrode of the resistive random access memory and the manufacturing method thereof in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 and Figure 2 The schematic process and principle of the method for preparing the lower electrode of the resistive random access memory according to an embodiment of the present invention are respectively shown.

[0030] like Figure 1 and Figure 2 As shown together, the method for preparing the lower electrode of the resistive random access memory according to the embodiment of the present invention mainly includes the following steps:

[0031] S110 : performing a planarization process on the surface of the bottom dielectric layer 2 so that the conductive material layer 3 filled in the dielectric layer 2 is fully or partially exposed.

[0032] Among them, this step first flattens the bottom electrode metal, that is, the surface of the dielectric layer 2, so that the conductive material filled in the dielectric layer 2 is fully or partially exposed; wherein, at least one electrode through hole 1 can be set on the dielectric layer 2, and the cross-sectional shape of the electrode through hole 1 is a trapezoidal structure, and then the conductive material layer 3 is filled in the electrode through hole 1, and the entire or partial structure of the conductive material layer 3 is exposed in the electrode through hole 1, so as to carry out subsequent lower electrode etching processing.

[0033] Furthermore, the material of the conductive material layer 3 can be selected from at least any one of Cu, W, Al, Co, Ru, Au, Ta, Ti, TaN, and TiN, and can be flexibly selected according to the requirements of the processing technology or the application scenario.

[0034] S120 : performing back etching and dry and / or wet cleaning on the conductive material layer 3 , so that the surface height of the conductive material layer 3 is lower than the surface of the dielectric layer 2 .

[0035] Among them, the conductive material layer 3 is etched back and dry and / or wet cleaned, so that the height of the conductive material layer 3 located in the electrode through hole 1 is lower than the surface of the dielectric layer 2, providing an avoidance space for the subsequent growth of the lower electrode layer 4, and can effectively control the thickness of the lower electrode layer 4 to prevent it from being corroded or damaged during the subsequent chemical treatment process.

[0036] S130 : performing a reduction treatment on the conductive material layer 3 exposed on the upper end of the dielectric layer 2 , and selectively growing a lower electrode layer 4 on the surface of the conductive material layer 3 , wherein the surface height of the lower electrode layer 4 is not lower than the surface height of the dielectric layer 2 .

[0037] Specifically, the conductive material layer 3 after etching and cleaning is reduced, and the lower electrode layer 4 is selectively grown on the surface of the conductive material layer 3. Moreover, the surface height of the lower electrode layer 4 is not lower than the surface height of the dielectric layer 2, that is, the height of the lower electrode layer 4 is equal to or slightly higher than the surface height of the dielectric layer 2, so as to facilitate the subsequent growth of the resistive layer 5 and the upper electrode stack 6.

[0038] The grown lower electrode layer 4 , ie, the bottom electrode layer, may also be planarized to improve the surface uniformity of the lower electrode layer 4 .

[0039] S140: growing a resistive switching layer 5 and an upper electrode stack 6 on the upper portion of the lower electrode layer 4, and sequentially etching the obtained memory basic structure.

[0040] Specifically, a resistive layer 5 and an upper electrode stack 6 are grown on the upper portion of the lower electrode layer 4, and then the structure is etched, wherein the etching process includes photolithography and etching. First, the memory infrastructure structure after the growth of the resistive layer 5 and the upper electrode stack 6 is photolithographically processed, and then etched until it is etched to a preset designated position.

[0041] S150: performing intermetallic dielectric filling and planarization processing on the etched memory structure to complete the preparation of the lower electrode of the resistive memory.

[0042] In a specific embodiment of the method for preparing the lower electrode of the variable mode memory of the present invention, etching the obtained memory basic structure in sequence may include: the etching end point of the memory basic structure stays on the surface of the resistive switching layer 5 .

[0043] In another embodiment, the obtained memory infrastructure is sequentially etched, including: the etching endpoint of the memory infrastructure is stopped at the upper surface of the dielectric layer 2 .

[0044] In another embodiment, a metal wiring layer 8 is provided at the bottom of the electrode through hole 1; an electrode etching stop layer 7 is provided between the metal wiring layer 8 and the bottom of the conductive material layer 3; and the height of the electrode etching stop layer 7 is not lower than the height of the metal wiring layer 8.

[0045] Furthermore, the obtained memory infrastructure structure is sequentially etched, including: the etching endpoint of the memory infrastructure structure stops at the electrode etching stop layer 7 .

[0046] It should be noted that the materials of the intermetallic dielectric, the resistive switching layer 5 , the dielectric layer 2 , the metal wiring layer 8 , and the electrode etching stop layer 7 may be the same material or different materials.

[0047] As a specific example, Figure 2 The method for preparing the lower electrode of the resistive random access memory shown includes:

[0048] Step 1: Planarize the surface of the bottom dielectric layer 2 so that the conductive material layer 3 filled in the dielectric layer 2 is fully or partially exposed;

[0049] Step 2: performing back etching and dry and / or wet cleaning on the conductive material layer 3 so that the surface height of the conductive material layer 3 is lower than the surface of the dielectric layer 2;

[0050] Step 3: Performing a reduction treatment on the conductive material layer 3 exposed on the upper end of the dielectric layer 2, selectively growing a lower electrode layer 4 on the surface of the conductive material layer 3, and ensuring that the surface height of the lower electrode layer 4 is not lower than that of the dielectric layer 2; then, growing a resistive switching layer 5 and an upper electrode stack 6 on the upper portion of the lower electrode layer 4;

[0051] Step 4: Perform photolithography on the obtained memory infrastructure;

[0052] Step 5: Etching the obtained memory infrastructure to a predetermined designated position, such as the resistive switching layer 5 , the dielectric layer 2 , or the electrode etching stop layer 7 ; the designated position shown in the figure is the resistive switching layer 5 .

[0053] Step 6: Fill the etched memory structure with an intermetallic dielectric.

[0054] Step 7: Planarize the filled intermetallic dielectric to complete the preparation of the lower electrode of the resistive random access memory.

[0055] Corresponding to the above-mentioned method for preparing the lower electrode of the resistive random access memory, the present invention further provides a lower electrode of the resistive random access memory.

[0056] The embodiment of the lower electrode of the resistive random access memory may refer to the description in the embodiment of the method for preparing the lower electrode of the resistive random access memory, and will not be described in detail here.

[0057] According to the lower electrode of the resistive random access memory and the preparation method thereof of the present invention, by reducing the conductive material layer exposed in the electrode through-hole and then selectively growing the lower electrode layer on the surface of the reduced conductive material layer, self-alignment of the lower electrode to the conductive material layer can be achieved. This not only effectively reduces the size of the lower electrode, but also expands the optical alignment window (Alignment & Overlay) between the upper and lower electrodes, thereby effectively improving the arrangement density of the resistive random access memory. By selectively growing the lower electrode layer, the thickness of the film of the lower electrode layer and the surface roughness threshold can also be effectively controlled, thereby improving the surface uniformity and consistency. At the same time, during the preparation process, the lower electrode layer avoids the height difference between it and the dielectric layer and is tightly wrapped and covered by the dielectric layer, so that it will not be damaged by the etching and / or cleaning steps, thereby improving the yield.

[0058] As above Figure 1 and Figure 2 The lower electrode of a resistive random access memory and its manufacturing method according to the present invention are described by way of example. However, those skilled in the art will appreciate that various improvements may be made to the lower electrode of a resistive random access memory and its manufacturing method as described above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A method for preparing a lower electrode of a resistive random access memory, characterized in that: include: The surface of the bottom dielectric layer is planarized to expose all or part of the conductive material layer filled in the dielectric layer; wherein at least one electrode through-hole is provided on the dielectric layer, the cross-section of the electrode through-hole is trapezoidal, the conductive material layer is filled in the electrode through-hole, and all or part of the structure of the conductive material layer is exposed in the electrode through-hole; Performing back etching and dry and / or wet cleaning on the conductive material layer so that the surface height of the conductive material layer is lower than the surface of the dielectric layer; Performing a reduction treatment on the conductive material layer exposed on the upper end of the dielectric layer, and selectively growing a lower electrode layer on the surface of the conductive material layer, wherein the surface height of the lower electrode layer is not lower than the surface height of the dielectric layer; After growing a resistive switching layer and an upper electrode stack on the upper portion of the lower electrode layer, etching the obtained memory infrastructure in sequence; The etched memory structure is filled with an intermetallic dielectric and planarized to complete the preparation of the lower electrode of the resistive random access memory.

2. The method for preparing a lower electrode of a resistive random access memory according to claim 1, wherein: The material of the conductive material layer is at least any one of Cu, W, Al, Co, Ru, Au, Ta, Ti, TaN, and TiN.

3. The method for preparing a lower electrode of a resistive random access memory according to claim 1, wherein: After a lower electrode layer is selectively grown on the surface of the conductive material layer, a planarization process is performed on the surface of the lower electrode layer.

4. The method for preparing a lower electrode of a resistive random access memory according to claim 1, wherein: The etching process is performed on the obtained memory infrastructure in sequence, including: The etching endpoint of the memory infrastructure stops at the surface of the resistive switching layer.

5. The method for preparing a lower electrode of a resistive random access memory according to claim 1, wherein: The etching process is performed on the obtained memory infrastructure in sequence, including: The etching endpoint of the memory infrastructure stops at the upper surface of the dielectric layer.

6. The method for preparing a lower electrode of a resistive random access memory according to claim 1, wherein: A metal wiring layer is provided at the bottom of the electrode through hole; An electrode etching stop layer is provided between the metal wiring layer and the bottom of the conductive material layer; and The height of the electrode etching stop layer is not lower than the height of the metal wiring layer.

7. The method for preparing a lower electrode of a resistive random access memory according to claim 6, wherein: The etching process is performed on the obtained memory infrastructure in sequence, including: The etching endpoint of the memory infrastructure stops at the electrode etching stop layer.

8. The method for preparing a lower electrode of a resistive random access memory according to claim 6, wherein: The materials of the intermetallic dielectric, the resistive switching layer, the dielectric layer, the metal wiring layer, and the electrode etching stop layer are respectively the same or different.

9. A lower electrode of a resistive random access memory, characterized in that: The method for preparing the lower electrode of a resistive random access memory is used for preparation.

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