Method and system for correcting quantization error of SAR-ADC using perturbation processing

Abstract

The application provides a method and system for correcting quantization error of a SAR-ADC by using disturbance, and belongs to the technical field of data processing. p and V n ; 2) quantizing the sampled differential analog signals V p and V n ; 3) injecting a disturbance period T D , randomly injecting disturbances V Dp and V Dn into the positive phase of the auxiliary DAC capacitor array of the SAR-ADC main capacitor array and / or the negative phase of the SAR-ADC main capacitor array in the disturbance period T D , re-quantizing the lowest bit digital signals of the differential analog signals V p and V n M times, generating M1 positive correction codes and M0 negative correction codes after M times of quantization, and lowering quantization error caused by quantization resolution by using the method of introducing random disturbance in the quantization process of the differential SAR-ADC without changing the SAR-ADC main capacitor array, so that the precision of the SAR-ADC is improved.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology and relates to SAR-ADC data calibration technology, specifically a method and system for correcting SAR-ADC quantization errors using perturbation processing. Background Technology

[0002] With the continuous development of modern technology, analog-to-digital conversion technology is also constantly innovating, and various other analog-to-digital converters such as flash-ADC, pipelined ADC, and delta-sigma ADC have been developed one after another. Among them, SAR-ADC has gradually become a member of the mainstream digital-to-analog converters due to its advantages of low power consumption, small size, and high accuracy.

[0003] The basic structure of a traditional differential SAR-ADC includes a main DAC capacitor array, a comparator, and a successive approximation logic controller. Its operation can be summarized as comparing the analog signal bit by bit using a binary search method, quantizing the analog signal into a digital signal within a certain range. The core of this binary search bit-by-bit comparison is the main DAC capacitor array utilizing charge redistribution technology. The number of stages in the main DAC capacitor array directly determines the quantization accuracy of the SAR-ADC. The binary search approach requires that the ratio of the capacitor area between adjacent stages of the main DAC capacitor array in the SAR-ADC be 2. This means that the total capacitor area increases exponentially with the increase in the number of bits in the SAR-ADC, which is one of the main challenges in improving the accuracy of SAR-ADCs.

[0004] To maximize the accuracy of SAR-ADCs without excessively increasing the capacitor area, most commercially available high-bit SAR-ADCs employ a two-step DAC design. This involves assigning different DAC structures to the high-bit and low-bit quantization processes. For example, high-bit quantization, which requires coarse quantization, is performed using a flash-ADC, while low-bit quantization, which requires precise quantization, uses a SAR-ADC structure. While the two-step approach achieves higher accuracy with a smaller capacitor area, it introduces new challenges in analog signal amplification and transmission between the two ADC stages, and can also introduce errors due to the different ADC structures. Besides using a two-step approach to increase the ADC bit depth, another method is to improve quantization accuracy by simply repeating the least significant bit quantization. However, this method offers very limited improvement in accuracy. Summary of the Invention

[0005] To address the aforementioned problem that existing designs introduce errors and limit accuracy improvements in SAR-ADCs without increasing the main capacitor area, this invention proposes a method and system for correcting SAR-ADC quantization errors using perturbation processing.

[0006] This invention utilizes a method of introducing random perturbations during the quantization process of the differential SAR-ADC main capacitor array to reduce the quantization error caused by quantization resolution without changing the SAR-ADC main capacitor array, thereby improving the accuracy of the SAR-ADC main capacitor array; the specific technical solution is as follows:

[0007] The method for correcting quantization errors using SAR-ADC with perturbation processing includes the following steps:

[0008] 1) SAR-ADC for differential analog signal V p and V n Perform sampling;

[0009] 2) For the sampled differential analog signal V p and V n Quantify;

[0010] 3) After quantization, inject a perturbation period T. D During the disturbance period T D The internal auxiliary DAC capacitor array randomly injects perturbations V into the positive phase and / or negative phase of the SAR-ADC main capacitor array. Dp With V Dn For differential analog signal V p and V n The least significant bit of the digital signal is requantized M times, and the differential analog signal V p and V n During the quantization process, the least significant bit of the digital signal will randomly generate M1 positive correction codes and M0 negative correction codes, where M1 + M0 = M; M, M1, and M0 are all natural numbers. The M1 positive correction codes represent the number of digital signals with higher analog voltage inputs, and the M0 negative correction codes represent the number of digital signals with lower analog voltage inputs.

[0011] The correction voltage of the least significant bit digital signal is calculated based on M1 and M0 using the following formula:

[0012]

[0013] V C The least significant correction voltage, V LSB This is the resolution voltage for the least significant bit.

[0014] Further defined, the disturbance injection cycle in step 3) includes disturbance amplitude control logic that controls the magnitude of disturbance injection and disturbance polarity control logic that controls the random injection logic in the positive phase and / or negative phase of the SAR-ADC main capacitor array.

[0015] The disturbance amplitude control logic includes a first PRBS generator, a second PRBS generator, shift register A, shift register B, decoder A, and decoder B. The first PRBS generator is connected to decoder A via shift register A. Decoder A is connected to the positive phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the first PRBS generator is stored in shift register A and continuously updated. The pseudo-random code in shift register A controls the states of switches S1, S2, S3, and S4 corresponding to the positive phase of the auxiliary DAC capacitor array via decoder A. The second PRBS generator is connected to decoder B via shift register B. Decoder B is connected to the negative phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the second PRBS generator is stored in shift register B and continuously updated. The pseudo-random code in shift register B controls the states of switches S1, S2, S3, and S4 corresponding to the negative phase of the auxiliary DAC capacitor array via decoder B. The first PRBS generator has x stages. n The second PRBS generator has x stages. p ;

[0016] The disturbance polarity control logic includes a third PRBS generator and a shift register C. The third PRBS generator has x stages. o The pseudo-random code generated by the third PRBS generator is stored in shift register C and continuously updated. The pseudo-random code in shift register C controls the working state of decoder A and decoder B, thereby controlling whether disturbances are injected into the positive phase and / or negative phase of the SAR-ADC main capacitor array.

[0017] Further defined, the disturbance period T D =M×T0, where M is the number of times the least significant bit digital signal is requantized, and T0 is the time required for the SAR-ADC main capacitor array to perform one bit quantization.

[0018] Further specifying, step 1) specifically includes:

[0019] Both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm The lower plates of the positive and negative phase capacitors of the SAR-ADC main capacitor array are connected to the differential analog signal V, respectively. p The acquisition port and differential analog signal V n Connect the acquisition port to perform differential analog signal V. p and V n Sampling; the upper plate and lower plate of the auxiliary DAC capacitor array are both connected to the common-mode level V. cmconnect.

[0020] Further specifying, step 2) specifically includes:

[0021] Before quantization, both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm Disconnect the lower plate of the positive capacitor of the SAR-ADC main capacitor array from the reference ground voltage V. GND Connect the lower plate of the negative phase capacitor of the SAR-ADC main capacitor array to the reference voltage V. ref connect;

[0022] During quantization, the lower plate of the highest-position capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the highest-position capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the highest-order state of the positive and negative capacitors, thus completing the quantization of the highest-order capacitor. Keeping the highest-order capacitor unchanged as the highest-order quantization result, the lower plate of the second-highest-order capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the second-highest capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the second-highest bit state of the positive and negative phase capacitors, thus completing the quantization of the second-highest bit capacitor. This process continues until the differential analog signal V is completed. p and V n Quantization of all bits; during quantization, the lower plate of the auxiliary DAC capacitor array is connected to the reference ground voltage V. GND .

[0023] Furthermore, the method for correcting SAR-ADC quantization errors using perturbation processing also includes:

[0024] After quantization, the state of the lower plate of each capacitor in the positive phase of the SAR-ADC main capacitor array is represented as B. pi The state of the lower plate of each capacitor in the negative phase of the SAR-ADC main capacitor array is represented as B. ni i represents the number of bits, p represents the positive phase of the SAR-ADC main capacitor array, n represents the negative phase of the SAR-ADC main capacitor array, and B pi A value of "1" indicates that the lower plate of the capacitor in the positive phase of the SAR-ADC main capacitor array is in contact with the reference voltage V. ref Connection, B ni A value of "1" indicates that the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array is connected to the reference voltage V. ref Connection, Bpi A value of "0" indicates that the voltage V between the lower plate of the positive phase capacitor in the SAR-ADC main capacitor array and the reference ground voltage is... GND Connection, B ni A value of "0" indicates that the voltage V between the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array and the reference ground voltage. GND If connected, the differential analog signal V p and V n The difference voltage V represented by the N-bit digital signal obtained by quantization pq -V nq for:

[0025] Where i = 1, 2, 3…N, N is an integer; V pq For V p The analog voltage value obtained after quantization; V nq For V n The simulated voltage value obtained after quantization;

[0026] Quantization error voltage ΔV o =(V p -V n )-(V pq -V nq );

[0027] According to V pq -V nq and the least significant correction voltage V C The corrected conversion voltage V can be obtained. po -V no The calculation formula is as follows:

[0028] V po -V no =(V pq -V nq )+V C

[0029] Among them, (V) po -V no ) is (V pq -V nq The corrected conversion voltage.

[0030] Further specified, M ≥ 10 and ≤ 20; x p =7; the x n =9; the x o =5.

[0031] The system for correcting SAR-ADC quantization errors using the above-described method of perturbation processing comprises a positive-phase SAR-ADC main capacitor array, a negative-phase SAR-ADC main capacitor array, a positive-phase auxiliary DAC capacitor array, a negative-phase auxiliary DAC capacitor array, a comparator, perturbation injection logic, and SAR-ADC logic. The positive-phase SAR-ADC main capacitor array is connected to the positive-phase auxiliary DAC capacitor array, and the negative-phase SAR-ADC main capacitor array is connected to the negative-phase auxiliary DAC capacitor array. The positive-phase auxiliary DAC capacitor array is connected to the positive terminal of the comparator, and the negative-phase auxiliary DAC capacitor array is connected to the negative terminal of the comparator. The output terminal of the comparator is connected to both the input terminal of the SAR-ADC logic and the input terminal of the perturbation injection logic. The output terminal of the SAR-ADC logic is connected to both the positive-phase and negative-phase SAR-ADC main capacitor arrays, and the output terminal of the perturbation injection logic is connected to both the positive-phase and negative-phase auxiliary DAC capacitor arrays.

[0032] Furthermore, the system for correcting SAR-ADC quantization errors using perturbation processing also includes a quantization result register and a perturbation result register. The input terminals of both the quantization result register and the perturbation result register are connected to the output terminal of the comparator. The output terminals of both the quantization result register and the perturbation result register are connected to the input terminal of the SAR-ADC logic. The output terminal of the perturbation result register is connected to the input terminal of the perturbation injection logic.

[0033] Furthermore, the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary DAC capacitor array are symmetrically arranged on both sides of the comparator;

[0034] The non-phase auxiliary DAC capacitor array includes non-phase auxiliary switches S0, S1, S2, S3, and S4. These switches are connected in parallel. Each of the non-phase auxiliary switches S0, S1, S2, S3, and S4 has a capacitor connected in series. The non-phase auxiliary switch S0 is connected to a capacitor... The positive phase auxiliary switch S1 is connected to both the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor; the positive phase auxiliary switch S2 is connected to both the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor; the positive phase auxiliary switch S3 is connected to both the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor; and the positive phase auxiliary switch S4 is connected to both the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor.

[0035] The negative phase auxiliary DAC capacitor array includes negative phase auxiliary switches S0, S1, S2, S3, and S4. These switches are connected in parallel. Each of the negative phase auxiliary switches S0, S1, S2, S3, and S4 has a capacitor connected in series. The negative phase auxiliary switch S0 is connected to a capacitor... The negative phase auxiliary switch S1 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S2 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S3 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S4 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] 1. This invention utilizes a perturbation-based SAR-ADC quantization error correction method, which adds a perturbation period after quantization is completed, during which a perturbation period T is applied. D The internal auxiliary DAC capacitor array randomly injects perturbations V into the positive phase and / or negative phase of the SAR-ADC main capacitor array, respectively. Dp With V Dn For differential analog signal V p and V nThe least significant bit digital signal is requantized M times to correct the voltage value of the least significant bit. This invention utilizes the method of introducing random disturbances during the differential SAR-ADC quantization process to reduce the quantization resolution, optimize the quantization error, and correct the error without changing the SAR-ADC main capacitor array, thereby improving the accuracy of the SAR-ADC. Moreover, the method of this invention does not introduce other errors and can ensure the accuracy of quantization.

[0038] 2. The perturbation injection logic includes perturbation amplitude control logic that controls the magnitude of the perturbation injection and perturbation polarity control logic that controls the random injection logic in the positive phase and / or negative phase of the SAR-ADC main capacitor array. The perturbation amplitude control logic includes a first PRBS generator, a second PRBS generator, shift register A, shift register B, decoder A, and decoder B. The perturbation polarity control logic includes a third PRBS generator and shift register C. After each quantization of the SAR-ADC main capacitor array, a perturbation injection period is added. The N-bit digital signal quantized by the SAR-ADC main capacitor array is stored in the quantization result register, and the correction code generated during the quantization period is stored in the perturbation result register. The least significant bit digital signal is corrected by the correction code to reduce the quantization error of the SAR-ADC.

[0039] 3. In the differential analog signal acquisition process, this invention connects both the upper plate and the lower plate of the auxiliary DAC capacitor array to the common-mode level V. cm The connection is made, and during the quantization process, the lower plate of the auxiliary DAC capacitor array is connected to the reference ground level V. GND The connection can prevent the auxiliary DAC capacitor array from affecting the sampling and quantization process of the differential analog signal.

[0040] 4. The auxiliary DAC capacitor array applicable to this invention adopts a series-parallel capacitor structure, which can generate a disturbance voltage with an amplitude lower than the minimum resolution of the SAR-ADC main capacitor array using a unit capacitor of the same size as the SAR-ADC main capacitor array. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the system for correcting SAR-ADC quantization errors using perturbation processing according to the present invention;

[0042] Figure 2 This is a schematic diagram showing the connection between the SAR-ADC main capacitor array and the auxiliary ADC capacitor array in the SAR-ADC quantization error correction system using perturbation processing according to the present invention.

[0043] Figure 3 This is a schematic diagram illustrating the process of the method for correcting SAR-ADC quantization errors using perturbation processing according to the present invention.

[0044] Figure 4 Timing diagram for disturbance injection control of SAR-ADC main capacitor array and auxiliary ADC capacitor array;

[0045] Figure 5 Example diagram of an auxiliary ADC capacitor array for injecting perturbations;

[0046] Figure 6 To calculate the correction voltage value V using the correction code generated by the disturbance. C Principle explanation diagram;

[0047] Figure 7 This diagram illustrates the principle of random control implementation of disturbance control logic during the disturbance injection period. Detailed Implementation

[0048] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings and embodiments, but the present invention is not limited to the embodiments described below.

[0049] Example 1

[0050] See Figure 3 The method for correcting quantization errors using SAR-ADC with perturbation processing includes the following steps:

[0051] 1) SAR-ADC for differential analog signal V p and V n Perform sampling;

[0052] See Figure 4 Specifically, both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm The lower plates of the positive and negative phase capacitors of the SAR-ADC main capacitor array are connected to the differential analog signal V, respectively. p The acquisition port and differential analog signal V n The acquisition port is connected; both the upper plate and the lower plate of the auxiliary DAC capacitor array are connected to the common-mode level V. cm The connections are made so that switches S0, S1, S2, S3, and S4 of both the positive and negative auxiliary DAC capacitor arrays are connected to the common-mode level V. cm Connections are made to ensure no disturbances are injected during the acquisition process; differential analog signal V is then processed. p and V n Collection;

[0053] 2) The acquired differential analog signal V p and V n Quantify;

[0054] Specifically, before quantization, both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm Disconnect, and then connect the lower plate of the positive capacitor of the SAR-ADC main capacitor array to the reference ground voltage V. GND Connect the lower plate of the negative phase capacitor of the SAR-ADC main capacitor array to the reference voltage V. ref connect;

[0055] During quantization, the lower plate of the highest-position capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the highest-position capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the highest-order state of the positive and negative capacitors, thus completing the quantization of the highest-order capacitor. Keeping the highest-order capacitor unchanged as the highest-order quantization result, the lower plate of the second-highest-order capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the second-highest capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the second-highest bit state of the positive and negative phase capacitors, thus completing the quantization of the second-highest bit capacitor. This process continues until the differential analog signal V is completed. p and V n Quantization of all bits; during quantization, the auxiliary DAC maintains the lower plate connected to the reference ground voltage V. GND To prevent affecting the quantification results;

[0056] 3) After quantization is complete, see Figure 6 and Figure 7 The N-bit digital signal obtained by quantization is stored in the quantization result register. Before starting the next quantization, a perturbation period T is added. D The disturbance period T D The length of T is determined by the number of injected perturbations M. D = M × T0, where M is the number of times the least significant bit digital signal is requantized, and T0 is the time required for the SAR-ADC main capacitor array to perform one bit quantization; during the disturbance period T D The internal auxiliary DAC capacitor array randomly injects perturbations V into the positive phase and / or negative phase of the SAR-ADC main capacitor array. Dp With V DnThe auxiliary DAC capacitor array will requantize the least significant bit of the digital signal M times while keeping the remaining (N-1) bits unchanged, i.e., perform M random perturbations. After M quantizations, M1 positive correction codes and M0 negative correction codes are generated, where M1 + M0 = M; M, M1, and M0 are all natural numbers. The M1 positive correction codes represent the number of digital signals with higher analog voltage inputs, and the M0 negative correction codes represent the number of digital signals with lower analog voltage inputs. The perturbation period T is... D The Mth quantization result of the least significant bit digital signal is stored in the perturbation result register;

[0057] The correction voltage of the least significant bit digital signal is calculated based on M1 and M0 using the following formula:

[0058]

[0059] V C The least significant correction voltage, V LSB The resolution voltage for the least significant bit;

[0060] During the disturbance, the switches S0 of the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary DAC capacitor array are related to the reference ground voltage V. GND The connection, random perturbation injection logic circuit will control one of the switches S1, S2, S3 and S4 of the non-inverting auxiliary DAC capacitor array to be randomly connected to the reference voltage V. ref One of the switches S1, S2, S3, and S4 of the negative phase auxiliary DAC capacitor array is randomly connected to the reference voltage V. ref And the other three switches remain connected to the reference ground voltage V. GND This will make V Dp With V Dn The amplitude of the disturbance voltage will randomly change from In the selection, whether the positive and negative phases of the SAR-ADC main capacitor array are perturbed is random, and the maximum and minimum values ​​of the final injected equivalent perturbation are... and

[0061] In step 3) of this implementation, the disturbance injection cycle includes disturbance amplitude control logic that controls the magnitude of the disturbance injection and / or disturbance polarity control logic that controls the random injection logic in the positive phase and negative phase of the SAR-ADC main capacitor array.

[0062] The disturbance amplitude control logic includes a first PRBS generator, a second PRBS generator, shift register A, shift register B, decoder A, and decoder B. The first PRBS generator is connected to decoder A via shift register A. Decoder A is connected to the positive phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the first PRBS generator is stored in shift register A and continuously updated. The pseudo-random code in shift register A controls the states of switches S1, S2, S3, and S4 corresponding to the positive phase of the auxiliary DAC capacitor array via decoder A. The second PRBS generator is connected to decoder B via shift register B. Decoder B is connected to the negative phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the second PRBS generator is stored in shift register B and continuously updated. The pseudo-random code in shift register B controls the states of switches S1, S2, S3, and S4 corresponding to the negative phase of the auxiliary DAC capacitor array via decoder B. The first PRBS generator has x stages. n The second PRBS generator has x stages. p ;

[0063] The disturbance polarity control logic includes a third PRBS generator and a shift register C. The third PRBS generator has x stages. o The pseudo-random code generated by the third PRBS generator is stored in shift register C and continuously updated. The pseudo-random code in shift register C controls the working state of decoder A and decoder B, thereby controlling whether disturbances are injected into the positive phase and / or negative phase of the SAR-ADC main capacitor array.

[0064] Preferably, in this embodiment, M ≥ 10 and ≤ 20, where M can be 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20; x p It must be an odd number, specifically, it can be 5, 7, 9, 11, 13, etc., preferably x. p =7;x n It must be an odd number, specifically, it can be 5, 7, 9, 11, 13, etc., preferably x. n =9;x o It must be an odd number, specifically, it can be 5, 7, 9, 11, 13, etc., preferably x. o =5.

[0065] Example 2

[0066] This embodiment utilizes a perturbation-processed SAR-ADC quantization error correction method, which, based on Embodiment 1, further includes:

[0067] After quantization, the state of the lower plate of each capacitor in the positive phase of the SAR-ADC main capacitor array is represented as B.pi The state of the lower plate of each capacitor in the negative phase of the SAR-ADC main capacitor array is represented as B. ni i represents the number of bits, p represents the positive phase of the SAR-ADC main capacitor array, n represents the negative phase of the SAR-ADC main capacitor array, and B pi A value of "1" indicates that the lower plate of the capacitor in the positive phase of the SAR-ADC main capacitor array is in contact with the reference voltage V. ref Connection, B ni A value of "1" indicates that the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array is connected to the reference voltage V. ref Connection, B pi A value of "0" indicates that the voltage V between the lower plate of the positive phase capacitor in the SAR-ADC main capacitor array and the reference ground voltage is... GND Connection, B ni A value of "0" indicates that the voltage V between the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array and the reference ground voltage. GND If connected, the differential analog signal V p and V n The difference voltage V represented by the N-bit digital signal obtained by quantization pq -V nq for:

[0068] Where i = 1, 2, 3…N, N is an integer; V pq For V p The analog voltage value obtained after quantization; V nq For V n The simulated voltage value obtained after quantization;

[0069] Quantization error voltage ΔV o =(V p -V n )-(V pq -V nq );

[0070] According to V pq -V nq and the least significant correction voltage V C The corrected conversion voltage V can be obtained. po -V no The calculation formula is as follows:

[0071] V po -V no =(V pq -V nq )+V C

[0072] Among them, (V) po -V no ) is (V pq -Vnq The corrected conversion voltage. See [link / reference] Figure 5 Using a single-ended three-dimensional SAR-ADC main capacitor array as an example, the amplitude control of the disturbance generated by the auxiliary DAC capacitor array is illustrated. Since the disturbance injection system for differential SAR-ADC designed in this invention is completely symmetrical in the positive and negative phases, and the disturbance voltage injected in the positive and negative phases is equivalent to the output with only different signs, this application uses a single-ended SAR-ADC main capacitor array as an example to reduce complexity.

[0073] See Figure 5 (a) The upper plate of the SAR-ADC main capacitor array is connected to the common-mode level V. cm Switch S m Connect analog input signal V in and the analog input signal V in Connected to the lower plate of the SAR-ADC main capacitor array; switch S s Connected to common-mode level V cm Connect both the upper and lower plates of the auxiliary DAC capacitor array to the common-mode level V. cm In the auxiliary DAC capacitor array, capacitors C1, C2, C3, C4, and C5 have their lower plates connected to a common-mode voltage V. cm Therefore, the series and parallel connection of capacitors can be equivalently represented as:

[0074] C T1～5 =(((C1+C2) / / C3)+C4) / / C5=1C

[0075] In the above formula, C T1～5 The symbol represents the equivalent capacitance value after C1, C2, C3, C4, and C5 are connected in series and parallel. " / / " indicates that the two capacitors are connected in series.

[0076] Thus, the charge value Q of the upper plate of the capacitor array during the sampling stage is obtained. x0 :

[0077] Q x0 =V cm ×(C T +C7+C6+C T1～5 )-V in ×C T -V cm ×(C6+C T1～5 )

[0078] Q x0 =8V cm C-8V in C

[0079] In the above formula, C TThis is the sum of the capacitances of the main capacitor array of a single-ended SAR-ADC.

[0080] See Figure 5 (b) represents the quantization state without any introduced disturbance, during which switch S is used. m Connect to reference voltage V ref Switch S s Connected to reference voltage V ref The quantization result is "010". At this time, the states of auxiliary DAC switches S4, S3, S2, and S1 are "0000", where "0" indicates that the reference ground voltage V is connected. GND "1" indicates that the reference voltage V is connected. ref The charge value Q on the upper plate of the capacitor array can be calculated at this time. xb :

[0081] Q xb =V xb ×(C T +C7+C6+C T1～5 )-V ref ×2C=12V xb C-2V ref C

[0082] In the above formula, V xb The voltage at point X at this moment can be obtained from the conservation of charge on the upper plate:

[0083] Q x0 =Q xb

[0084] Right now:

[0085] 8V cm C-8V in C = 12V xb C-2V ref C

[0086] Solving for:

[0087]

[0088] This shows that although an auxiliary DAC capacitor array is added to the circuit, it will not affect the normal quantization results when no disturbance is introduced.

[0089] See Figure 5 (c) This represents the state after quantization following the introduction of a disturbance. The quantization result is set to "010". At this time, the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "1000". The charge value Q on the upper plate of the capacitor array can be calculated at this time. xc :

[0090] Q xc=V xc ×(C T +C7+C6+C T1～5 )-V ref ×2C-V ref ×2C=12V xc C-4V ref C

[0091] In the above formula, V xc The voltage at point X at this moment can be obtained from the conservation of charge on the upper plate:

[0092] Q x0 =Q xc

[0093] 8V cm C-8V in C = 12V xc C-4V ref C

[0094] Solving for:

[0095]

[0096] Therefore, it can be seen that when the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "1000", it is equivalent to the analog input signal V... in The amplitude was injected on The negative perturbation.

[0097] See Figure 5 (d) represents the state after quantization following the introduction of a disturbance. The quantization result is set to "010". At this time, the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0100". The charge value Q on the upper plate of the capacitor array can be calculated at this time. xd :

[0098] Q xd =V xd ×(C T +C7+C6+C T1～5 )-V ref ×2C-V ref ×C=12V xd C-3V ref C

[0099] In the above formula, V xd The voltage at point X at this moment can be obtained from the conservation of charge on the upper plate:

[0100] Q x0 =Q xd

[0101] Right now:

[0102] 8V cm C-8V in C = 12V xd C-3V ref C

[0103] Solving for:

[0104]

[0105] Therefore, it can be seen that when the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0100", it is equivalent to the analog input signal V... in The amplitude was injected on The negative perturbation.

[0106] See Figure 5 (e) is the state after quantization following the introduction of a disturbance. The quantization result is taken as "010". At this time, the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0010". Since the potentials of the lower plates of C1, C2, and C4 are different in this state, C1 cannot continue to be used. T1～5 This represents the equivalent capacitance value after C1, C2, C3, C4, and C5 are connected in series and parallel. Here, the equivalent capacitance value of C1, C2, and C3 after being connected in series and parallel is represented by C. T1～3 It indicates that:

[0107] C T1～3 = (C1 + C2) / / C3 = 1C

[0108] The charge value Q on the upper plate of the capacitor array can be calculated at this time. xe With the charge value Q at point Y at this time ye :

[0109] Q xe =V xe ×(C T +C7+C6+C5)-V ref ×2C-V ye ×C5,

[0110] Q ye =V ye ×(C5+C4+C T1～3 )-V xe ×C5-V ref ×C4,

[0111] In the above formula, V xe Let V be the voltage at point X. ye Let Y be the voltage at point Y. By the law of charge conservation, we can obtain:

[0112] Q x0 =Q xe

[0113] 0 = Q ye

[0114] Right now:

[0115] 8V cm C-8V in C = V xe ×13C-V ref ×2C-V ye ×2C

[0116] 0 = V ye ×4C-V xe ×2C-V ref ×C

[0117] Solving for:

[0118]

[0119] Therefore, it can be seen that when the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0010", it is equivalent to the analog input signal V... in The amplitude was injected on The negative perturbation.

[0120] See Figure 5 (f) represents the state after quantization following the introduction of a disturbance. The quantization result is set to "010". At this time, the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0001". The charge value Q on the upper plate of the capacitor array can be calculated at this time. xf With the charge value Q at point Y at this time yf With the Z-point charge value Q zf :

[0121] Q xf =V xf ×(C T +C7+C6+C5)-V ref ×2C-V yf ×C5

[0122] Q yf =V yf ×(C5+C4+C3)-V xf ×C5-V zf ×C3

[0123] Q zf =V zf ×(C3+C2+C1)-V yf ×C3-V ref ×C2

[0124] In the above formula, V xf The voltage at point X at this moment, Vyf The voltage at point Y at this moment, V zf The voltage at point Z at this moment can be obtained from the law of charge conservation:

[0125] Q x0 =Q xf

[0126] 0 = Q yf

[0127] 0 = Q zf

[0128] Right now:

[0129] 8V cm C-8V in C = V xf ×13C-V ref ×2C-V yf ×2C

[0130] 0 = V yf ×5C-V xf ×2C-V zf ×2C

[0131] 0 = V zf ×4C-V yf ×2C-V ref ×C

[0132] Solving for:

[0133]

[0134] Therefore, it can be seen that when the states of switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array are "0010", it is equivalent to the analog input signal V... in The amplitude was injected on The negative perturbation.

[0135] The above analysis shows that the disturbance amplitudes introduced by the switches S4, S3, S2, and S1 of the auxiliary DAC capacitor array when they are in the states of "1000", "0100", "0010", and "0001" are respectively...

[0136] See Figure 6 This explains how to calculate the correction voltage value V using the correction code. C The specific principle is shown in the diagram V. in V represents the actual analog input voltage value. inq To quantize the analog voltage value represented by the digital signal, we can see V in With V inq There is a certain quantization error ΔV between them o :

[0137] ΔV o =V in -V inq

[0138] During the perturbation period, due to the introduction of the perturbation, the least significant bit will randomly change during the M repetitions of quantization within that period. This change is called the M correction code, which can be divided into two types: the correction code corresponding to the higher analog voltage is called the positive correction code, and the correction code corresponding to the lower analog voltage is called the negative correction code. The number of these correction codes are M1 and M0, respectively, and they satisfy the following equation:

[0139] M1 + M0 = M

[0140] This allows us to obtain the calculated correction voltage value V. C The specific formula is:

[0141]

[0142] Where V LSB This is the minimum resolution voltage for an N-bit differential SAR-ADC. The larger the value of M, the higher the correction voltage V. C The more accurate the value, the better it indicates that the corrected voltage value V is within the allowable error range. C With quantization error voltage ΔV o The signs are the same, and the correction voltage value V is smaller when the quantization error voltage V0 is smaller. C The smaller the absolute value of V, and the larger the quantization error voltage V0, the higher the correction voltage value V. C The larger the absolute value of V, the greater the potential value of V. inq With V C Adding them together yields a result with lower quantization error.

[0143] As described above, the amplitudes of the injected disturbance voltages controlled by the control switches S1, S2, S3, and S4 of the auxiliary DAC capacitor array in a single phase are respectively... Because the perturbation control logic randomly generates positive and negative phase perturbations, in this differential SAR-ADC capacitor array, for the differential analog input signal (V... p -V n For example, the equivalent value probability of positive and negative phase injection perturbations is: 0, There are a total of 15 perturbation values, which can better improve accuracy.

[0144] Example 3

[0145] See Figure 1This embodiment utilizes a system for SAR-ADC quantization error correction using perturbation processing. It is formed based on the method for SAR-ADC quantization error correction using perturbation processing in Embodiment 1 or Embodiment 2. It includes a positive-phase SAR-ADC main capacitor array, a negative-phase SAR-ADC main capacitor array, a positive-phase auxiliary DAC capacitor array, a negative-phase auxiliary DAC capacitor array, a comparator, perturbation injection logic, and SAR-ADC logic. The positive-phase SAR-ADC main capacitor array is connected to the positive-phase auxiliary DAC capacitor array, the negative-phase SAR-ADC main capacitor array is connected to the negative-phase auxiliary DAC capacitor array, the positive-phase auxiliary DAC capacitor array is connected to the positive terminal of the comparator, the negative-phase auxiliary DAC capacitor array is connected to the negative terminal of the comparator, the output terminal of the comparator is connected to both the input terminal of the SAR-ADC logic and the input terminal of the perturbation injection logic, the output terminal of the SAR-ADC logic is connected to both the positive-phase SAR-ADC main capacitor array and the negative-phase SAR-ADC main capacitor array, and the output terminal of the perturbation injection logic is connected to both the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary DAC capacitor array.

[0146] The system for correcting SAR-ADC quantization errors using perturbation processing also includes a quantization result register and a perturbation result register. The input terminals of both the quantization result and the perturbation result are connected to the output terminal of the comparator. The output terminals of both the quantization result and the perturbation result are connected to the input terminal of the SAR-ADC logic. The output terminal of the perturbation result is connected to the input terminal of the perturbation injection logic.

[0147] The positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary DAC capacitor array are symmetrically arranged on both sides of the comparator;

[0148] See Figure 2 The positive phase auxiliary DAC capacitor array includes positive phase auxiliary switches S0, S1, S2, S3, and S4. These switches are connected in parallel. Each of the positive phase auxiliary switches S0, S1, S2, S3, and S4 has a capacitor connected in series. Positive phase auxiliary switch S0 is connected to the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor. Positive phase auxiliary switch S1 is connected to the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor. Positive phase auxiliary switch S2 is connected to the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor. Positive phase auxiliary switch S3 is connected to the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor. Positive phase auxiliary switch S4 is connected to the main capacitor array of the positive phase SAR-ADC and the positive terminal of the comparator via a capacitor.

[0149] The negative phase auxiliary DAC capacitor array includes negative phase auxiliary switches S0, S1, S2, S3, and S4. These switches are connected in parallel. Each of the negative phase auxiliary switches S0, S1, S2, S3, and S4 has a capacitor connected in series. Negative phase auxiliary switch S0 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. Similarly, negative phase auxiliary switches S1, S2, S3, and S4 are also connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor.

[0150] A common-mode level V is correspondingly set on both the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary DAC capacitor array. cm Reference ground voltage V GND and reference voltage V ref .

[0151] The capacitors of both the positive-phase SAR-ADC main capacitor array and the negative-phase SAR-ADC main capacitor array are C. The capacitors connected to the positive-phase auxiliary switch S0 of the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary switch S0 of the negative-phase auxiliary DAC capacitor array are also C. The capacitors connected to the positive-phase auxiliary switch S1 of the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary switch S1 of the negative-phase auxiliary DAC capacitor array are C and 2C respectively. Specifically, the capacitor C corresponding to the positive-phase auxiliary switch S0 of the positive-phase auxiliary DAC capacitor array and the capacitor C corresponding to the negative-phase auxiliary switch S0 of the negative-phase auxiliary DAC capacitor array are connected to the corresponding switches S1 with C and 2C respectively. The capacitors connected to the positive-phase auxiliary switch S2 of the positive-phase auxiliary DAC capacitor array and the negative-phase auxiliary switch S2 of the negative-phase auxiliary DAC capacitor array are both C and 2C. Specifically, the capacitor 2C corresponding to the positive-phase auxiliary switch S1 of the positive-phase auxiliary DAC capacitor array is... The capacitor 2C corresponding to the negative auxiliary switch S1 of the negative auxiliary DAC capacitor array is connected to the C and 2C of the corresponding positive auxiliary switch S2 and negative auxiliary switch S2, respectively. The capacitors connected to the positive auxiliary switch S3 of the positive auxiliary DAC capacitor array and the negative auxiliary switch S3 of the negative auxiliary DAC capacitor array are both C, and the capacitors connected to the positive auxiliary switch S4 of the positive auxiliary DAC capacitor array and the negative auxiliary switch S4 of the negative auxiliary DAC capacitor array are both 2C. This setting can generate a disturbance voltage with an amplitude lower than the minimum resolution of the SAR-ADC using a unit capacitor of the same size as the SAR-ADC main capacitor array. The capacitors corresponding to the five switches of the auxiliary DAC capacitor array can adjust their connected levels through switches S0, S1, S2, S3, and S4. The lower plate of the capacitor controlled by switch S0 can be connected to the common-mode level V. cm Or reference ground voltage V GND The lower plate of the capacitor controlled by switches S1, S2, S3, and S4 can be connected to the common-mode voltage V. cm Reference voltage V ref Or reference ground voltage V GND Switches S0, S1, S2, S3, and S4 are controlled by disturbance injection logic; this allows the generation of disturbance voltages with amplitudes lower than the minimum resolution of the SAR-ADC using a unit capacitor of the same size as the SAR-ADC main capacitor array.

[0152] The auxiliary DAC capacitor array control switches S1, S2, S3, and S4 can only close one switch at a time during each disturbance injection. The corresponding disturbance voltage amplitudes controlled by switches S1, S2, S3, and S4 are as follows:

[0153] For a single phase, the auxiliary DAC capacitor array used to generate and inject disturbances can only generate negative voltage disturbances. In order to make the injected disturbances both positive and negative, auxiliary DAC circuits are added to both the positive and negative phase capacitor arrays of the differential SAR-ADC, namely, a positive phase auxiliary DAC capacitor array and a negative phase auxiliary DAC capacitor array. When a disturbance is applied in the positive phase, it is equivalent to a negative disturbance injection, and when a disturbance is applied in the negative phase, it is equivalent to a positive disturbance injection.

[0154] The SAR-ADC in this invention is a successive approximation analog-to-digital converter.

[0155] The above describes an implementation method and system for SAR-ADC quantization error correction using perturbation processing according to the present invention. The scope of protection of the present invention is not limited to the specific implementation methods described above. Modifications and equivalent substitutions made according to the present invention are all included within the scope of protection of this application.

Claims

1. A method for correcting quantization errors in SAR-ADC using perturbation processing, characterized in that, Includes the following steps: 1) SAR-ADC for differential analog signal V p and V n Perform sampling; 2) For the sampled differential analog signal V p and V n Quantify; 3) After quantization, inject a perturbation period T. D During the disturbance period T D The internal auxiliary DAC capacitor array randomly injects perturbations V into the positive phase and / or negative phase of the SAR-ADC main capacitor array. Dp With V Dn For differential analog signal V p and V n The least significant bit of the digital signal is requantized M times, and the differential analog signal V p and V n During the quantization process, the least significant bit of the digital signal will randomly generate M1 positive correction codes and M0 negative correction codes, where M1 + M0 = M; M, M1, and M0 are all natural numbers. The M1 positive correction codes represent the number of digital signals with higher analog voltage inputs, and the M0 negative correction codes represent the number of digital signals with lower analog voltage inputs. The correction voltage of the least significant bit digital signal is calculated based on M1 and M0 using the following formula: V C The least significant correction voltage, V LSB This is the resolution voltage for the least significant bit.

2. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 1, characterized in that, The disturbance injection cycle in step 3) includes disturbance amplitude control logic that controls the magnitude of disturbance injection and disturbance polarity control logic that controls the random injection logic in the positive phase and / or negative phase of the SAR-ADC main capacitor array. The disturbance amplitude control logic includes a first PRBS generator, a second PRBS generator, shift register A, shift register B, decoder A, and decoder B. The first PRBS generator is connected to decoder A via shift register A. Decoder A is connected to the positive phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the first PRBS generator is stored in shift register A and continuously updated. The pseudo-random code in shift register A controls the states of switches S1, S2, S3, and S4 corresponding to the positive phase of the auxiliary DAC capacitor array via decoder A. The second PRBS generator is connected to decoder B via shift register B. Decoder B is connected to the negative phase of the auxiliary DAC capacitor array. The pseudo-random code generated by the second PRBS generator is stored in shift register B and continuously updated. The pseudo-random code in shift register B controls the states of switches S1, S2, S3, and S4 corresponding to the negative phase of the auxiliary DAC capacitor array via decoder B. The first PRBS generator has x stages. n The second PRBS generator has x stages. p ; The disturbance polarity control logic includes a third PRBS generator and a shift register C. The third PRBS generator has x stages. o The pseudo-random code generated by the third PRBS generator is stored in shift register C and continuously updated. The pseudo-random code in shift register C controls the working state of decoder A and decoder B, thereby controlling whether disturbances are injected into the positive phase and / or negative phase of the SAR-ADC main capacitor array.

3. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 1, characterized in that, The disturbance period T D =M×T0, where M is the number of times the least significant bit digital signal is requantized, and T0 is the time required for the SAR-ADC main capacitor array to perform one bit quantization.

4. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 1, characterized in that, Step 1) specifically refers to: Both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm The lower plates of the positive and negative phase capacitors of the SAR-ADC main capacitor array are connected to the differential analog signal V, respectively. p The acquisition port and differential analog signal V n Connect the acquisition port to perform differential analog signal V. p and V n Sampling; the upper plate and lower plate of the auxiliary DAC capacitor array are both connected to the common-mode level V. cm connect.

5. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 4, characterized in that, Step 2) specifically refers to: Before quantization, both the upper plates of the positive and negative capacitors of the SAR-ADC main capacitor array are connected to the common-mode level V. cm Disconnect the lower plate of the positive capacitor of the SAR-ADC main capacitor array from the reference ground voltage V. GND Connect the lower plate of the negative phase capacitor of the SAR-ADC main capacitor array to the reference voltage V. ref connect; During quantization, the lower plate of the highest-position capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the highest-position capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the highest-order state of the positive and negative capacitors, thus completing the quantization of the highest-order capacitor. Keeping the highest-order capacitor unchanged as the highest-order quantization result, the lower plate of the second-highest-order capacitor in the positive phase of the SAR-ADC main capacitor array is switched to V. ref Simultaneously, the lower plate of the second-highest capacitor in the negative phase of the SAR-ADC main capacitor array is switched to the reference ground voltage V. GND The comparator compares the positive and negative phase voltages to determine the second-highest bit state of the positive and negative phase capacitors, thus completing the quantization of the second-highest bit capacitor. This process continues until the differential analog signal V is completed. p and V n Quantization of all bits; during quantization, the lower plate of the auxiliary DAC capacitor array is connected to the reference ground voltage V. GND .

6. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 5, characterized in that, The method for correcting SAR-ADC quantization errors using perturbation processing further includes: After quantization, the state of the lower plate of each capacitor in the positive phase of the SAR-ADC main capacitor array is represented as B. pi The state of the lower plate of each capacitor in the negative phase of the SAR-ADC main capacitor array is represented as B. ni i represents the number of bits, p represents the positive phase of the SAR-ADC main capacitor array, n represents the negative phase of the SAR-ADC main capacitor array, and B pi A value of "1" indicates that the lower plate of the capacitor in the positive phase of the SAR-ADC main capacitor array is in contact with the reference voltage V. ref Connection, B ni A value of "1" indicates that the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array is connected to the reference voltage V. ref Connection, B pi A value of "0" indicates that the voltage V between the lower plate of the capacitor in the positive phase of the SAR-ADC main capacitor array and the reference ground voltage is... GND Connection, B ni A value of "0" indicates that the voltage V between the lower plate of the capacitor in the negative phase of the SAR-ADC main capacitor array and the reference ground voltage. GND If connected, the differential analog signal V p and V n The difference voltage V represented by the N-bit digital signal obtained by quantization pq -V nq for: Where i = 1, 2, 3…N, N is an integer; V pq For V p The analog voltage value obtained after quantization; V nq For V n The simulated voltage value obtained after quantization; Quantization error voltage ΔV o =(V p -V n )-(V pq -V nq ); According to V pq -V nq and the least significant correction voltage V C The corrected conversion voltage V can be obtained. po -V no The calculation formula is as follows: V po -V no =(V pq -V nq )+V C Among them, (V) po -V no ) is (V pq -V nq The corrected conversion voltage.

7. The method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 2, characterized in that, The M ≥ 10 and ≤ 20; the x p =7; the x n =9; the x o =5.

8. A system for correcting SAR-ADC quantization errors using perturbation processing, based on the method for correcting SAR-ADC quantization errors using perturbation processing as described in claim 6, characterized in that... The system includes a positive-phase SAR-ADC main capacitor array, a negative-phase SAR-ADC main capacitor array, a positive-phase auxiliary DAC capacitor array, a negative-phase auxiliary DAC capacitor array, a comparator, perturbation injection logic, and SAR-ADC logic. The positive-phase SAR-ADC main capacitor array is connected to the positive-phase auxiliary DAC capacitor array, and the negative-phase SAR-ADC main capacitor array is connected to the negative-phase auxiliary DAC capacitor array. The positive-phase auxiliary DAC capacitor array is connected to the positive terminal of the comparator, and the negative-phase auxiliary DAC capacitor array is connected to the negative terminal of the comparator. The output terminal of the comparator is connected to both the input terminals of the SAR-ADC logic and the perturbation injection logic. The output terminal of the SAR-ADC logic is connected to both the positive-phase and negative-phase SAR-ADC main capacitor arrays, and the output terminal of the perturbation injection logic is connected to both the positive-phase and negative-phase auxiliary DAC capacitor arrays.

9. The system for correcting SAR-ADC quantization errors using perturbation processing as described in claim 8, characterized in that, The system for correcting SAR-ADC quantization errors using perturbation processing further includes a quantization result register and a perturbation result register. The input terminals of the quantization result register and the perturbation result register are both connected to the output terminal of the comparator. The output terminals of the quantization result register and the perturbation result register are both connected to the input terminal of the SAR-ADC logic. The output terminal of the perturbation result register is connected to the input terminal of the perturbation injection logic.

10. The system for correcting SAR-ADC quantization errors using perturbation processing as described in claim 9, characterized in that, The positive phase auxiliary DAC capacitor array and the negative phase auxiliary DAC capacitor array are symmetrically arranged on both sides of the comparator; The positive phase auxiliary DAC capacitor array includes a positive auxiliary switch S0, a positive auxiliary switch S1, a positive auxiliary switch S2, a positive auxiliary switch S3, and a positive auxiliary switch S4. These positive auxiliary switches S0, S1, S2, S3, and S4 are connected in parallel. Each of these switches has a capacitor connected in series. The positive auxiliary switch S0 is connected through a capacitor. The positive auxiliary switch S1 is connected to both the main capacitor array of the positive SAR-ADC and the positive terminal of the comparator via a capacitor; the positive auxiliary switch S2 is connected to both the main capacitor array of the positive SAR-ADC and the positive terminal of the comparator via a capacitor; the positive auxiliary switch S3 is connected to both the main capacitor array of the positive SAR-ADC and the positive terminal of the comparator via a capacitor; and the positive auxiliary switch S4 is connected to both the main capacitor array of the positive SAR-ADC and the positive terminal of the comparator via a capacitor. The negative phase auxiliary DAC capacitor array includes negative phase auxiliary switches S0, S1, S2, S3, and S4. These switches are connected in parallel. Each of the negative phase auxiliary switches S0, S1, S2, S3, and S4 has a capacitor connected in series. The negative phase auxiliary switch S0 is connected to a capacitor... The negative phase auxiliary switch S1 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S2 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S3 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor. The negative phase auxiliary switch S4 is connected to both the main capacitor array of the negative phase SAR-ADC and the negative terminal of the comparator via a capacitor.

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