Method for manufacturing semiconductor substrate, semiconductor substrate, and method for suppressing generation of growth layer cracks

Abstract

The present invention is a method for manufacturing a semiconductor substrate, comprising: a brittle processing step (S10) for reducing the strength of a base substrate (10); and a crystal growth step (S20) for forming a growth layer (20) on the base substrate (10). Furthermore, the present invention is a method for suppressing the generation of cracks in a growth layer (20), comprising a brittle processing step (S10) for reducing the strength of a base substrate (10) before forming the growth layer (20) on the base substrate (10).

Description

TECHNICAL FIELD

[0001] The present application relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, and a method for suppressing generation of cracks in a growth layer. BACKGROUND

[0002] Conventionally, in the manufacturing of a semiconductor substrate, a semiconductor substrate of a desired semiconductor material is manufactured by causing a semiconductor material different from a base substrate to grow crystals on the base substrate (so-called hetero-epitaxial growth).

[0003] However, in the hetero-epitaxial growth, a problem is that cracks in the growth layer, dislocation generation, surface morphology deterioration, substrate warping, and the like are caused due to a difference in lattice constant or a difference in thermal expansion coefficient of the two materials.

[0004] In order to solve the problem of generation of cracks and the like in the growth layer, an intermediate layer (so-called buffer layer) for absorbing stress caused by a difference in lattice constant or a difference in thermal expansion coefficient is formed between the base substrate and the growth layer.

[0005] For example, in Patent Literature 1, a two-step growth method is disclosed, in which a low-temperature growth layer is formed before a compound semiconductor layer is formed in order to absorb stress or crystal defects caused by a difference in lattice constant and a difference in thermal expansion coefficient between a Si substrate and a compound semiconductor.

[0006] Further, in Patent Literature 2, a technique is disclosed in which an aluminum nitride (AIN) layer is inserted as a buffer layer between a silicon carbide (SiC) layer and a gallium nitride (GaN) layer.

[0007] PRIOR ART DOCUMENTS

[0008] PATENT LITERATURE

[0009] Patent Literature 1: Japanese Patent Application Laid-Open No. 2000-311903

[0010] Patent Literature 2: Japanese Patent Application Laid-Open No. 2013-179121 SUMMARY

[0011] PROBLEMS TO BE SOLVED BY THE INVENTION

[0012] In addition, the generation of cracks in the growth layer described above occurs even in a case where the same semiconductor material as the base substrate is caused to grow crystals on the base substrate (so-called homo-epitaxial growth). That is, in a case where the doping concentration of the base substrate and the growth layer is different, cracks are generated due to a difference in interlattice distance between the base substrate and the growth layer.

[0013] The problem to be solved by the present application is to provide a novel technique capable of suppressing generation of cracks in a growth layer.

[0014] Means for solving the problem

[0015] The present application that solves the above problem is a method for manufacturing a semiconductor substrate, including: a brittle processing step of reducing the strength of a base substrate; and a crystal growth step of forming a growth layer on the base substrate.

[0016] Thus, by including a brittle processing step of reducing the strength of a base substrate, stress generated in a growth layer can be released to the base substrate, and generation of cracks in the growth layer is suppressed.

[0017] In a preferred embodiment of the present application, the crystal growth step is a step of forming the growth layer having a shrinkage rate different from that of the base substrate.

[0018] According to the present application, by releasing stress caused by a difference in shrinkage rate between a base substrate and a growth layer to the base substrate, generation of cracks on the growth layer side can be suppressed.

[0019] In a preferred embodiment of the present application, the base substrate and the growth layer are different in doping concentration.

[0020] According to the present application, generation of cracks caused by a difference in doping concentration between a base substrate and a growth layer can be suppressed. That is, generation of cracks in a growth layer in homoepitaxial growth can be suppressed.

[0021] In a preferred embodiment of the present application, the base substrate and the growth layer are different in material.

[0022] According to the present application, generation of cracks caused by a difference in physical properties (lattice constant, thermal expansion coefficient) of semiconductor materials between a base substrate and a growth layer can be suppressed. That is, generation of cracks in a growth layer in heteroepitaxial growth can be suppressed.

[0023] In a preferred embodiment of the present application, the brittle processing step has: a through-hole forming step of forming a through-hole in the base substrate; and a strain layer removing step of removing a strain layer introduced by the through-hole forming step.

[0024] In a preferred embodiment of the present application, the through-hole forming step forms a through-hole by irradiating laser light to the base substrate.

[0025] In a preferred embodiment of the present application, the strain layer removing step removes a strain layer of the base substrate by performing heat treatment.

[0026] In a preferred embodiment of the present application, the base substrate is silicon carbide; and the strain layer removing step etches the base substrate in a silicon atmosphere.

[0027] In a preferred embodiment of the present application, the crystal growth step is performed using a physical vapor transport method.

[0028] Further, the present application also relates to a method for suppressing the generation of cracks in a growth layer. That is, the present application that solves the above-described problem is a method for suppressing the generation of cracks in a growth layer, which includes a brittle processing step of reducing the strength of a base substrate before forming a growth layer on the base substrate.

[0029] In a preferred embodiment of the present application, the brittle processing step has a through-hole forming step of forming a through-hole in the base substrate; and a strain layer removing step of removing a strain layer introduced by the through-hole forming step.

[0030] In a preferred embodiment of the present application, the strain layer removing step etches the base substrate by performing a heat treatment.

[0031] In a preferred embodiment of the present application, the base substrate is silicon carbide; and the strain layer removing step etches the base substrate in a silicon atmosphere.

[0032] Effects of the Invention

[0033] According to the disclosed technology, it is possible to provide a novel technology capable of suppressing the generation of cracks in a growth layer.

[0034] Other problems, features, and advantages will become apparent from reading the following description of embodiments of the present application, taken in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 is an explanatory view that explains a step of a method for manufacturing a semiconductor substrate according to an embodiment.

[0036] Figure 2 is an explanatory view that explains a step of a method for manufacturing a semiconductor substrate according to an embodiment.

[0037] Figure 3 is an explanatory view of a through-hole forming step according to an embodiment.

[0038] Figure 4 is an explanatory view that explains a crystal growth step according to an embodiment.

[0039] Figure 5 is an explanatory view of a through-hole forming step according to Embodiment 1.

[0040] Figure 6 is an explanatory view of a strain layer removing step according to Embodiment 1.

[0041] Figure 7 is an explanatory view of a crystal growth step according to Embodiment 1.

[0042] Figure 8 is a schematic view of the cooling step according to Embodiment 1. DETAILED DESCRIPTION

[0043] A preferred embodiment of a method for manufacturing a semiconductor substrate according to the present application will be described in detail below with reference to the accompanying drawings. The technical scope of the present application is not limited to the embodiment illustrated in the drawings, and can be appropriately changed within the scope of the claims. Furthermore, the drawings are conceptual views, and the relative sizes of the components, etc. are not limited to the present application. Furthermore, in the present specification, there are cases in which the upper and lower directions are referred to based on the drawings, for the purpose of illustrating the present application, but the upper and lower directions are not limited in terms of the usage mode of the semiconductor substrate of the present application, etc. In addition, the same reference numerals are applied to the same structures in the description of the following embodiments and the drawings, and repeated description is omitted.

[0044] Method for manufacturing a semiconductor substrate

[0045] Figure 1 and Figure 2 A step of a method for manufacturing a semiconductor substrate according to an embodiment of the present application is shown.

[0046] The method for manufacturing a semiconductor substrate according to the embodiment can include a brittle processing step S10 of reducing the strength of the base substrate 10, a crystal growth step S20 of forming a growth layer 20 on the base substrate 10, and a cooling step S30 of cooling the base substrate 10 and the growth layer 20 after the crystal growth step S20.

[0047] Furthermore, the present embodiment can be understood as a method for suppressing generation of cracks in the growth layer 20 by including the brittle processing step S10 of reducing the strength of the base substrate 10 before forming the growth layer 20 on the base substrate 10.

[0048] Hereinafter, each step of the embodiment will be described in detail.

[0049] <Brittle processing step>

[0050] The brittle processing step is a step of reducing the strength of the base substrate 10. In other words, the brittle processing step S10 is a step of processing so as to make the base substrate 10 easily deformed or damaged by an external force. Further in other words, the brittle processing step S10 is a step of increasing the fragility of the base substrate 10. In addition, the "strength" in the present specification refers to the durability against physical external forces such as compression, stretching, etc., and includes the concept of mechanical strength.

[0051] The brittle processing step S10 according to the embodiment reduces the strength of the base substrate 10 by forming the through-hole 11 on the base substrate 10. That is, the volume of the base substrate 10 is reduced to make it easy to deform or be damaged by an external force.

[0052] More specifically, the brittle processing step S10 has a through-hole forming step S11 of forming the through-hole 11 on the base substrate 10, and a strain layer removing step S12 of removing the strain layer 12 introduced by the through-hole forming step S11.

[0053] The base substrate 10 can be made of a material generally used in manufacturing semiconductor substrates. The material of the base substrate 10 is, for example, a known Group IV material such as silicon (Si), germanium (Ge), diamond (C), and the like. Further, the material of the base substrate 10 is, for example, a known Group IV-IV compound material such as silicon carbide (SiC), and the like. Further, the material of the base substrate 10 is a known Group II-VI compound material such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), cadmium telluride (CdTe), and the like. Further, the material of the base substrate 10 is, for example, a known Group III-V compound material such as boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AIN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), indium antimonide (InSb), and the like. Further, the material of the base substrate 10 is, for example, an oxide material such as aluminum oxide (AI2O3), gallium oxide (Ga2O3), and the like. Further, the material of the base substrate 10 is, for example, a metal material such as copper (Cu), nickel (Ni), and the like. In addition, the base substrate 10 can also be a structure in which a known additive atom is appropriately added according to the material used.

[0054] In addition, the base substrate 10 can use a wafer or a substrate processed from a bulk crystal, or a substrate that has a buffer layer made of the above-described semiconductor material alone.

[0055] The through-hole forming step S11 reduces the strength of the base substrate 10 by forming the through-hole 11 on the base substrate 10. The through-hole forming step S11 can be any method that can form the through-hole 11 on the base substrate 10.

[0056] The method of forming the through-hole 11 can use, for example, laser processing, a focused ion beam system (FIB), plasma etching such as reactive ion etching (RIE), and the like. In addition, in the Figure 2 A method of forming the through-hole 11 by irradiating laser light L on the base substrate 10 is exemplified in the embodiment shown in FIG. 1.

[0057] The through hole 11 can adopt a shape that reduces the strength of the base substrate 10, and can be formed as a single or multiple through holes 11. Further, a group (pattern) of through holes 11 in which multiple through holes 11 are arranged can be adopted.

[0058] Hereinafter, an example of a pattern at the time of growth of a hexagonal semiconductor material will be described in detail.

[0059] Figure 3 is an explanatory view illustrating a pattern 100 according to an embodiment. The line segment indicated by the pattern 100 is a base substrate 10. The pattern 100 preferably assumes a triply symmetric regular hexagonal displacement shape. Hereinafter, the pattern 100 will be described with reference to Figure 3 The "regular hexagonal displacement shape" in the description in the present specification will be described in detail. The regular hexagonal displacement shape is a dodecagon. Further, the regular hexagonal displacement shape is composed of 12 line segments that assume equal lengths and are straight. The pattern 100 that assumes the regular hexagonal displacement shape includes a reference figure 101 that has an area and includes three vertices 104 as an equilateral triangle. Each of the three vertices 104 is included in the vertices of the pattern 100. Here, the three vertices 104 can be understood as being present on the line segments that compose the pattern 100. The pattern 100 includes a line segment 102 (corresponding to a first line segment) that extends from the vertex 104 and includes the vertex 104, and a line segment 103 (corresponding to a second line segment) that is adjacent to the line segment 102 and does not extend from the vertex 104 and does not include the vertex 104. Here, the angle Θ of two adjacent line segments 102 in the pattern 100 is constant, and is equal to the angle Θ of two adjacent line segments 103 in the pattern 100. In addition, the "regular hexagonal displacement shape" in the description in the present specification can be understood as a dodecagon that is obtained by displacing (deforming) a regular hexagon based on an angle Θ that indicates the degree of concave-convex while maintaining the area of the regular hexagon.

[0060] The angle Θ is preferably greater than 60°, more preferably 66° or greater, more preferably 80° or greater, more preferably 83° or greater, more preferably 120° or greater, more preferably 150° or greater, more preferably 155° or greater. Further, the angle Θ is preferably 180° or less, more preferably 155° or less, more preferably 150° or less, more preferably 120° or less, more preferably 83° or less, more preferably 80° or less, more preferably 66° or less.

[0061] The pattern 100 according to the embodiment can also be a structure of a regular dodecagon displacement form which is six-fold symmetric, instead of a regular hexagon displacement form which is three-fold symmetric. The regular dodecagon displacement form is a twenty-four-sided polygon. Further, the regular dodecagon displacement form is composed of 24 line segments which exhibit equal lengths and are straight. The pattern 100 exhibiting a regular dodecagon displacement form includes a reference figure 101 which is a regular hexagon having an area and includes 6 vertices 104. Each of the 6 vertices 104 is included in the vertices of the pattern 100. Further, as with the regular hexagon displacement form, the angle θ formed by two adjacent line segments 102 in the pattern 100 is constant, and is equal to the angle θ formed by two adjacent line segments 103 in the pattern 100. That is, the "regular dodecagon displacement form" in the present specification can be understood as a twenty-four-sided polygon which is formed by displacing (deforming) a regular dodecagon based on the angle θ which indicates the degree of concave-convex while maintaining the area of the regular dodecagon. Further, the pattern 100 can also be a structure of a 4n-sided polygon, i.e., a 2n-sided displacement form, which is formed by displacing (deforming) a regular 2n-sided polygon based on the angle θ which indicates the degree of concave-convex while maintaining the area of the regular 2n-sided polygon, the regular 2n-sided polygon exhibiting a regular 2n-sided displacement form including a regular hexagon displacement form and a regular 12-sided displacement form. At this time, the 2n-sided displacement form can be understood as including a regular n-sided polygon (corresponding to the reference figure 101). Here, the reference figure 101 can be understood as including n vertices.

[0062] The pattern 100 according to the embodiment can also be a structure including a regular 2n-sided displacement form including a regular hexagon displacement form and a regular 12-sided displacement form. Further, the pattern 100 can also be a structure including at least one line segment (corresponding to a third line segment) which connects the intersection of two adjacent line segments 103 in the regular 2n-sided displacement form to the center of gravity of the reference figure 101, in addition to the line segments which constitute the regular 2n-sided displacement form. Further, the pattern 100 can also be a structure including at least one line segment which connects the intersection of two adjacent line segments 103 in the regular 2n-sided displacement form to a vertex 104 constituting the reference figure 101, in addition to the line segments which constitute the regular 2n-sided displacement form. Further, the pattern 100 can also be a structure including at least one line segment which constitutes a line segment constituting the reference figure 101 included in the regular 2n-sided displacement form, in addition to the line segments which constitute the regular 2n-sided displacement form.

[0063] Further, the through-hole forming step S11 is preferably a step of removing 50% or more of the effective area of the base substrate 10. Further, it is more preferable to be a step of removing 60% or more of the effective area, it is further preferable to be a step of removing 70% or more of the effective area, and it is further preferable to be a step of removing 80% or more of the effective area.

[0064] In addition, the effective area in the present specification refers to the surface of the base substrate 10 to which the raw material is attached in the crystal growth step S20. In other words, it refers to the remaining area in the growth surface of the base substrate 10 except for the area removed by the through-hole 11.

[0065] In addition, it is desirable that the effective area of the base substrate 10 or the shape / pattern of the through-hole 11 be set in consideration of the difference in lattice constant or the difference in coefficient of thermal expansion between the base substrate 10 and the growth layer 20, the crystal structure of the growth layer 20, the growth method.

[0066] The strain layer removal step S12 is a step of removing the strain layer 12 formed on the base substrate 10 by the through-hole formation step S11. The strain layer removal step S12 can be adopted as long as it is a means capable of removing the strain layer 12 introduced into the base substrate 10.

[0067] The method of removing the strain layer 12 can employ, for example, a hydrogen etching method using hydrogen gas as an etching gas, a Si vapor etching (SiVE) method in which heating is performed under a Si atmosphere, and the etching method described in Embodiment 1 described later.

[0068] <Crystal growth step>

[0069] The crystal growth step S20 is a step of forming a growth layer 20 on the base substrate 10 after the brittle processing step S10.

[0070] The semiconductor material of the growth layer 20 can be either the same semiconductor material as the base substrate 10 (homoepitaxial growth) or a different semiconductor material from the base substrate 10 (heteroepitaxial growth). In addition, a case in which the strength of the semiconductor material of the growth layer 20 is lower than the strength of the semiconductor material of the base substrate 10 can be exemplified.

[0071] As the material of the growth layer 20, a material that is normally epitaxially grown as a semiconductor material can be adopted. The material of the growth layer 20 can be either the material of the base substrate 10, a known material that can be adopted as the material of the base substrate 10, or a known material that can be epitaxially grown on the base substrate 10.

[0072] Specifically, the material of the growth layer 20 can employ, for example, Si, Ge, GaN, AlN, InN, ZnS, ZnSe, CdTe, GaP, GaAs, InP, InAs, InSb, SiC, or the like.

[0073] The combination of the material of the base substrate 10 and the material of the growth layer 20 can be appropriately selected in consideration of the difference in lattice constant or the difference in coefficient of thermal expansion of the two materials.

[0074] As the growth method of the growth layer 20, the crystal growth step S20 can employ a known vapor phase growth method (corresponding to a vapor phase epitaxy method) such as a physical vapor transport method (Physical Vapor Transport: PVT), a sublimation recrystallization method, a modified Rayleigh method, a chemical vapor transport method (Chemical Vapor Transport: CVT), a molecular-organic vapor phase epitaxy method (Molecular-Organic Vapor Phase Epitaxy: MOVPE), a hydride vapor phase epitaxy method (Hydride Vapor Phase Epitaxy: HVPE), and the like. In addition, the crystal growth step S20 can employ a physical vapor deposition method (Physical Vapor Deposition: PVD) instead of the PVT. In addition, the crystal growth step S20 can employ a chemical vapor deposition method (Chemical Vapor Deposition: CVD) instead of the CVT. Further, as the growth method of the growth layer 20, the crystal growth step S20 can employ a known liquid phase growth method (corresponding to a liquid phase epitaxy method) such as a TSSG method (Top-Seeded Solution Growth method), a metastable solvent epitaxy method (Metastable Solvent Epitaxy: MSE), and the like. Further, as the growth method of the growth layer 20, the crystal growth step S20 can employ a CZ method (Czochralski method, pulling method). The crystal growth step S20 can appropriately select and employ a growth method according to the materials of the base substrate 10 and the growth layer 20.

[0075] Figure 4 is an explanatory view that explains the crystal growth step S20 according to the embodiment.

[0076] The crystal growth step S20 according to the embodiment is a step of arranging the base substrate 10 and the semiconductor material 40, which is a raw material of the growth layer 20, in opposition (facing each other) in the crucible 30 having a quasi-enclosed space and heating. In addition, the "quasi-enclosed space" in the present specification means a space in which at least a part of vapor generated in the container can be enclosed although evacuation of the space can be performed.

[0077] Further, the crystal growth step S20 is a step of heating so as to form a temperature gradient in the vertical direction of the base substrate 10. By heating the crucible 30 (the base substrate 10 and the semiconductor material 40) in this temperature gradient, the raw material is transported from the semiconductor material 40 to the base substrate 10 through the raw material transport space 31.

[0078] As a driving force for transporting the raw material, the temperature gradient or the chemical potential difference between the base substrate 10 and the semiconductor material 40 described above can be employed.

[0079] Specifically, in the quasi-enclosed space, the vapor composed of the elements sublimated from the semiconductor material 40 is transported by diffusion in the raw material transport space 31, and reaches supersaturation and condenses on the base substrate 10 whose temperature is set lower than the semiconductor material 40. Alternatively, the vapor reaches supersaturation and condenses on the base substrate 10 whose chemical potential is lower than the semiconductor material 40. As a result, the growth layer 20 is formed on the base substrate 10.

[0080] In addition, in the crystal growth step S20, an inert gas or a dopant gas can also be introduced into the raw material transport space 31 and the doping concentration or the growth environment of the growth layer 20 can be controlled.

[0081] The present embodiment illustrates an embodiment in which the growth layer 20 is formed by the PVT method, however, any method that can form the growth layer 20 can of course be employed.

[0082] <cooling step>

[0083] The cooling step S30 is a step of cooling the base substrate 10 and the growth layer 20 heated in the crystal growth step S20.

[0084] In the cooling step S30, the base substrate 10 and the growth layer 20 shrink according to their respective thermal expansion coefficients due to the decrease in temperature. At this time, the base substrate 10 and the growth layer 20 generate a difference in shrinkage rate in the case where the semiconductor material or the doping concentration is different.

[0085] According to the present embodiment, since the strength of the base substrate 10 is reduced in the brittle processing step S10, even in the case where the base substrate 10 and the growth layer 20 generate a difference in shrinkage rate, the base substrate 10 is deformed or a crack 13 is formed (refer to FIG. 2B). Figure 2 and Figure 8 ).

[0086] That is, the crystal growth step S20 according to the present application is a step of forming the growth layer 20 having a different shrinkage rate from the base substrate 10. Specifically, the base substrate 10 and the growth layer 20 can be exemplified as being different in doping concentration, or the base substrate 10 and the growth layer 20 can be exemplified as being different in material.

[0087] In other words, the crystal growth step S20 according to the present embodiment is a step of forming the growth layer 20 having a different doping concentration from the base substrate 10. In addition, the crystal growth step S20 according to the present embodiment is a step of forming the growth layer 20 having a different material from the base substrate 10.

[0088] According to the present application, by including the brittle processing step S10 of reducing the strength of the base substrate 10, stress generated between the base substrate 10 and the growth layer 20 can be released to the base substrate 10, and generation of cracks in the growth layer 20 is suppressed.

[0089] As one embodiment of the method of manufacturing a semiconductor substrate according to the present application, as shown in the following example, an embodiment in which AlN is grown on a SiC substrate is cited.

[0090] Further, as one embodiment of the method of manufacturing a semiconductor substrate according to the present application, an embodiment in which the embodiment in which AlN is grown on a SiC substrate is not included is cited.

[0091] Example

[0092] Example 1 and Comparative Example 1 are cited to explain the present application more specifically.

[0093] In addition, Example 1 and Comparative Example 1 grow the growth layer 20 of AlN on the base substrate 10 of SiC to manufacture a semiconductor substrate.

[0094] The lattice mismatch of AlN to SiC is about 1%, and the difference in the coefficient of thermal expansion from SiC is about 23%. In Example 1, by releasing stress caused by this lattice mismatch and the difference in the coefficient of thermal expansion to the base substrate 10 of SiC, generation of cracks in the growth layer 20 of AlN is suppressed.

[0095] Example 1

[0096] <Through-hole forming step S11>

[0097] The base substrate 10 was irradiated with laser light and a through-hole 11 was formed under the following conditions.

[0098] (Base substrate 10)

[0099] Semiconductor material: 4H-SiC

[0100] Substrate size: 11 mm in lateral width x 11 mm in longitudinal length x 524 μm in thickness

[0101] Growth surface: Si surface

[0102] Misalignment angle: coaxial

[0103] (Laser processing conditions)

[0104] Type: green laser

[0105] Wavelength: 532 nm

[0106] Spot diameter: 40 μm

[0107] Average output: 4W (at 30 kHz)

[0108] (Details of the pattern)

[0109] Figure 5 is an explanatory view that explains the pattern of the through hole 11 formed in the through hole formation step S11 according to Embodiment 1. Figure 5 (a) of is an explanatory view that shows the arrangement state of the plurality of through holes 11. In this Figure 5 In (a) of, the region shown in black color indicates the portion of the through hole 11, and the region shown in white color remains as the base substrate 10.

[0110] Figure 5 (b) of is an explanatory view that shows the enlarged state of the through hole 11 of (a) of Figure 5 In (b) of, the region shown in white color indicates the portion of the through hole 11, and the region shown in black color remains as the base substrate 10. Figure 5

[0111] In addition, in the pattern of, more than 80% of the effective area of the base substrate 10 is removed, and the strength of the base substrate 10 is reduced. Figure 5

[0112] (Strained layer removal step S12)

[0113] Figure 6 is an explanatory view that explains the strained layer removal step S12 according to Embodiment 1.

[0114] The base substrate 10 in which the through hole 11 is formed by the through hole formation step S11 is housed in the SiC container 50, the SiC container 50 is further housed in the TaC container 60, and heating is performed under the following conditions.

[0115] (Heating conditions)

[0116] Heating temperature: 1800°C

[0117] Heating time: 2 hours

[0118] Etching amount: 8 μm

[0119] (SiC container 50)

[0120] Material: Polycrystalline SiC

[0121] Container size: Diameter 60 mm x height 4 mm

[0122] Distance between the base substrate 10 and the bottom surface of the SiC container 50: 2 mm

[0123] (Details of the SiC container 50) ​​

[0124] As Figure 6 shown, the SiC container 50 is a fitting container including an upper container 51 and a lower container 52 that can be fitted to each other. A minute gap 53 is formed at a fitting portion of the upper container 51 and the lower container 52, and the SiC container 50 is configured to be capable of exhausting (evacuating) the inside of the SiC container 50 from the gap 53.

[0125] The SiC container 50 has an etching space 54 formed by opposing a portion of the SiC container 50 disposed on the low-temperature side of the temperature gradient and the base substrate 10 in a state where the base substrate 10 is disposed on the low-temperature side of the temperature gradient. The etching space 54 is a space in which Si atoms and C atoms are transported from the base substrate 10 to the SiC container 50 and etched using a temperature difference provided between the base substrate 10 and a bottom surface of the SiC container 50 as a driving force.

[0126] Further, the SiC container 50 has a substrate holder 55 that holds the base substrate 10 in the air and forms the etching space 54. Alternatively, the substrate holder 55 can not be provided depending on the direction of the temperature gradient of the heating furnace. For example, in a case where the heating furnace forms a temperature gradient so that the temperature decreases from the lower container 52 to the upper container 51, the base substrate 10 can be disposed on a bottom surface of the lower container 52 without providing the substrate holder 55.

[0127] (TaC container 60)

[0128] Material: TaC

[0129] Container size: diameter 160 mm x height 60 mm

[0130] Si vapor supply source 64 (Si compound): TaSi2

[0131] (Details of the TaC container 60)

[0132] Like the SiC container 50, the TaC container 60 is a fitting container including an upper container 61 and a lower container 62 that can be fitted to each other, and is configured to be capable of accommodating the SiC container 50. A minute gap 63 is formed at a fitting portion of the upper container 61 and the lower container 62, and the TaC container 60 is configured to be capable of exhausting (evacuating) the inside of the TaC container 60 from the gap 63.

[0133] The TaC container 60 has a Si vapor supply source 64 that is capable of supplying a vapor pressure of a gas-phase species containing the Si element inside the TaC container 60. The Si vapor supply source 64 is only required to be a structure that generates a vapor pressure of a gas-phase species containing the Si element inside the TaC container 60 at the time of heat treatment.

[0134] <Crystal growth step S20>

[0135] Figure 7 is an explanatory view that explains the crystal growth step S20 according to Embodiment 1.

[0136] The base substrate 10 from which the strain layer 12 is removed by the strain layer removal step S12 is housed in the crucible 30 in a manner opposite to the semiconductor material 40, and heating is performed under the following conditions.

[0137] (Heating conditions)

[0138] Heating temperature: 2040°C

[0139] Heating time: 70 hours

[0140] Grown thickness: 500 μm

[0141] N2 gas pressure: 10 kPa

[0142] (Crucible 30)

[0143] Material: Tantalum carbide (TaC) and / or tungsten (W)

[0144] Container size: 10 mm x 10 mm x 1.5 mm

[0145] Distance between the base substrate 10 and the semiconductor material 40: 1 mm

[0146] (Details of the crucible 30)

[0147] The crucible 30 has a raw material delivery space 31 between the base substrate 10 and the semiconductor material 40. The raw material is delivered from the semiconductor material 40 to the base substrate 10 through the raw material delivery space 31.

[0148] Figure 7 (a) of FIG. 8 is an example of the crucible 30 used in the crystal growth step S20. Like the SiC container 50 and the TaC container 60, this crucible 30 is a fitting container including an upper container 32 and a lower container 33 that can be fitted to each other. A minute gap 34 is formed at the fitting portion of the upper container 32 and the lower container 33, and is configured to enable evacuation (vacuuming) from the gap 34 inside the crucible 30.

[0149] In addition, the crucible 30 has a substrate holder 35 for forming the raw material delivery space 31. The substrate holder 35 is provided between the base substrate 10 and the semiconductor material 40, and the semiconductor material 40 is disposed on the high-temperature side and the base substrate 10 is disposed on the low-temperature side to form the raw material delivery space 31.

[0150] Figure 7 (b) and Figure 7 (c) of FIG. 9 are other examples of the crucible 30 used in the crystal growth step S20. This Figure 7(b) of (c) of Figure 7 the temperature gradient of (a) of Figure 7 is opposite to that of (a) of Figure 7

[0151] Figure 7 (b) of (c) of

[0152] Figure 7 (c) of (c) of Figure 8 (c) of (c) of

[0153] (Semiconductor material 40)

[0154] Material: AlN sintered body

[0155] Dimensions: 20 mm in lateral width x 20 mm in longitudinal length x 5 mm in thickness

[0156] (Details of semiconductor material 40)

[0157] The AlN sintered body of the semiconductor material 40 is sintered by the following sequence.

[0158] The AlN powder is put into the frame of the TaC block, and is press-solidified with moderate force. After that, the press-solidified AlN powder and the TaC block are housed in a thermal decomposition carbon crucible, and are heated under the following conditions.

[0159] Heating temperature: 1850°C

[0160] N2 gas pressure: 10 kPa

[0161] Heating time: 3 hours

[0162] (Cooling step)

[0163] Finally, the substrate substrate 10 and the growth layer 20 after the crystal growth step S20 are cooled under the following conditions.

[0164] (Cooling conditions)

[0165] Substrate temperature before cooling: 2040°C

[0166] Substrate temperature after cooling: room temperature​

[0167] Cooling rate: 128℃ / min

[0168] ​ The image is an SEM image obtained by observing the substrate 10 and the growth layer 20 after cooling under the above conditions from the substrate 10 side. It can be seen that crack 13 was formed at the substrate 10.

[0169] Multiple cracks 13 were observed in the substrate 10 of the semiconductor substrate manufactured in Example 1. On the other hand, no cracks were observed in the growth layer 20. That is, it was confirmed that there were no cracks in the entire 10 mm × 10 mm area of ​​the AlN crystal growth surface (0001).

[0170] Comparative Example 1

[0171] For the same substrate 10 as in Example 1, the crystal growth step S20 and the cooling step S30 were performed under the same conditions as in Example 1. That is, Comparative Example 1 performed the crystal growth step S20 but did not perform the brittle processing step S10.

[0172] No crack 13 was observed in the substrate 10 of the semiconductor substrate manufactured using Comparative Example 1. On the other hand, in the growth layer 20, at a thickness of 1.0 mm... -1 Cracks were observed at the crack line density. Furthermore, the crack line density in this specification refers to the value obtained by dividing the sum of the lengths of all cracks observed in the measured area by the measured area (total crack length (mm) / measured area (mm)). 2 Crack linear density (mm) -1 )).

[0173] The results from Example 1 and Comparative Example 1 can be understood that by using the brittle processing step S10 to reduce the strength of the substrate 10, the stress generated in the growth layer 20 can be released to the substrate 10, and the generation of cracks in the growth layer 20 can be suppressed.

[0174] Explanation of reference numerals in the attached figures

[0175] 10. Substrate

[0176] 11 Through Holes

[0177] 12 Strain Layer

[0178] 13 Cracks

[0179] 20 growth layers

[0180] 30 crucibles

[0181] 31 Raw material conveying space

[0182] 40 semiconductor material

[0183] 50 SiC container

[0184] 60 TaC container

[0185] S10 brittle processing step

[0186] S11 via formation step

[0187] S12 strain layer removal step

[0188] S20 crystal growth step

[0189] S30 temperature reduction step

Claims

1. A manufacturing method of a semiconductor substrate, comprising: a brittle processing step of reducing strength of a base substrate; and a crystal growth step of forming a growth layer on the base substrate, the brittle processing step has a through-hole forming step of forming a through-hole on the base substrate, the through-hole forming step is a step of removing 50% or more of an effective area, the effective area being an area of a surface of the base substrate on which a raw material of the growth layer is attached in the crystal growth step, the crystal growth step is a step of forming a growth layer on the base substrate having the through-hole.

2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the crystal growth step forms the growth layer having a shrinkage rate different from that of the base substrate.

3. The method of manufacturing a semiconductor substrate according to claim 1 or 2, wherein, the base substrate and the growth layer are different in a doping concentration.

4. The method of manufacturing a semiconductor substrate according to claim 1 or 2, wherein, the base substrate and the growth layer are different in a material.

5. The method for manufacturing a semiconductor substrate according to claim 1 or 2, wherein the brittle processing step further has: a strain layer removing step of removing a strain layer introduced by the through-hole forming step.

6. The method of manufacturing a semiconductor substrate according to claim 5, wherein the through-hole forming step forms the through-hole by irradiating laser light to the base substrate.

7. The method of producing a semiconductor substrate according to claim 5, wherein the strain layer removing step removes the strain layer of the base substrate by performing heat treatment.

8. The manufacturing method of a semiconductor substrate according to claim 5, wherein the base substrate is silicon carbide; the strain layer removing step etches the base substrate under a silicon atmosphere.

9. The method of producing a semiconductor substrate according to claim 1 or 2, wherein the crystal growth step grows using a physical vapor transport method.

10. A semiconductor substrate manufactured by the manufacturing method according to any one of claims 1 to 9.

11. A method of inhibiting the generation of growth layer cracks comprising: a brittle processing step of reducing strength of a base substrate before forming a growth layer on the base substrate, the brittle processing step has a through-hole forming step of forming a through-hole on the base substrate, the through-hole forming step is a step of removing 50% or more of an area of a growth surface formed by the growth layer of the base substrate.

12. The method of claim 11, wherein, the brittle processing step further has: a strain layer removing step of removing a strain layer introduced by the through-hole forming step.

13. The method of claim 12, wherein, the strain layer removing step etches the base substrate by performing heat treatment.

14. The method according to claim 12 or 13, wherein the base substrate is silicon carbide; the strain layer removing step etches the base substrate under a silicon atmosphere.

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