System and method for identifying unswitched semiconductor switches

Abstract

The invention relates to a system (30) and a method for identifying a non-switched semiconductor switch (34a, 36a). The system (30) has a first semiconductor switch (34a), a first semiconductor device (34b), a second semiconductor switch (36a), a second semiconductor device (36b), a first resistor (64b), a second resistor (66b), and a determination unit (38). The determination unit (38) is configured to identify whether the first semiconductor switch (34a) is non-switched based on a profile of a first voltage drop across the first resistor (64b). The determination unit (38) is configured to identify whether the second semiconductor switch (36a) is non-switched based on a profile of a second voltage drop across the second resistor (66b).

Description

TECHNICAL FIELD

[0001] The present invention generally relates to the identification of non-switching semiconductor switches. In particular, the present invention relates to a system and a method for identifying non-switching semiconductor switches. BACKGROUND

[0002] In electronic power distributors, in particular in electronic power distributors with high functional safety requirements, it is of particular importance to know the health status (SoH) of the power semiconductors used at all times as far as possible. For this purpose, it is important to know whether the power semiconductors used as switches can reliably switch, in particular turn off, under all circumstances during operation. If this is not possible, the only possibility is to connect a second power semiconductor in series with the power semiconductor. This, however, increases the cost, the space requirement and the power loss of the current path. In addition, the series connection of a second power semiconductor only statistically reduces the probability of a fault in the current path. Only by turning off the semiconductor can a successful switching operation of the semiconductor be practically checked and / or diagnosed.

[0003] DE 43 01 605 C1 discloses a method and an arrangement for monitoring the turn-on and turn-off of controllable power semiconductor devices in a power electronic circuit. In the case of a control signal for turning on the power semiconductor device, a count signal is formed from the level changes of the signal supplied to the gate electrode and the level changes at the output electrode during the switching of the power semiconductor device. The count signal is added in a first counter and compared with a predefined count value associated with the fault-free operation of the power semiconductor device. When there is a difference between the sum of the count signals and the predefined count value, a fault signal is issued.

[0004] This method and the associated arrangement are disadvantageous at least because they only work in the case of a continuous switching of the switch. In static operation, the system cannot directly diagnose a fault. The method and the arrangement of DE 43 01 605 C1 are therefore not sufficiently reliable for identifying a fault, in particular in static operation.

[0005] There is therefore a need to reliably and accurately identify non-switching semiconductor switches. In particular, the identification should take place without having to turn off the associated load.

[0006] According to a first aspect of the present application, a system for identifying a non-switching semiconductor switch is provided. The system has a first semiconductor switch, a first semiconductor device, a second semiconductor switch, a second semiconductor device, a first resistor, a second resistor and a determining unit. The first semiconductor switch is controllable by means of a first control signal. The first semiconductor device is configured and arranged to prevent a current flow through the first semiconductor device at least in one direction. The second semiconductor switch is controllable by means of a second control signal. The second semiconductor device is configured and arranged to prevent a current flow through the second semiconductor device at least in one direction.

[0007] One end of the first resistor is connected between the first semiconductor switch and the first semiconductor device. The other end of the first resistor is connected to a reference potential, e.g. ground. One end of the second resistor is connected between the second semiconductor switch and the second semiconductor device. The other end of the second resistor is connected to a reference potential, e.g. ground. The determining unit is configured to identify whether the first semiconductor switch is non-switching based on a profile of a first voltage drop across the first resistor. The determining unit is configured to identify whether the second semiconductor switch is non-switching based on a profile of a second voltage drop across the second resistor.

[0008] In this way, it can be simply and accurately determined whether at least one of the two semiconductor switches is not switching. The profile is in particular a profile over time.

[0009] For example, the determining unit can be configured to identify whether the first semiconductor switch is correctly switching directly based on or only based on the profile of the first voltage over time. The determining unit can further be configured to determine an output signal allowing / enabling a fault in the switching of the first semiconductor switch to be identified based on the profile of the first voltage over time. For example, the determining unit can be configured to identify whether the second semiconductor switch is correctly switching directly based on or only based on the profile of the second voltage over time. The determining unit can further be configured to determine an output signal allowing / enabling a fault in the switching of the second semiconductor switch to be identified based on the profile of the second voltage over time.

[0010] The first semiconductor switch can assume a broken / open switch state and a closed switch state. The first semiconductor switch can be switched from the open switch state to the closed switch state and vice versa by means of the first control signal. To this end, the first control signal can be applied to a terminal of the first semiconductor switch, e.g. a gate terminal (in case of a field effect transistor).

[0011] The determining unit can be configured to identify a fault in the switching of the first semiconductor switch from the closed switch state to the open switch state. Additionally or alternatively, the determining unit can be configured to identify a fault in the switching of the second semiconductor switch from the closed switch state to the open switch state. The determining unit can be configured to identify whether the second switch correctly switches from the closed switch state to the open switch state based on the curve of the second voltage. The determining unit can be configured to identify whether the second switch correctly switches from the open switch state to the closed switch state based on the curve of the second voltage. In other words, the determining unit is able to identify whether the first and / or the second semiconductor switch can or can not (correctly) be transferred from the closed switch state to the open switch state.

[0012] The second semiconductor switch can assume a disengaged / open switch state and a closed switch state. The second semiconductor switch can be transferred from the open switch state to the closed switch state and vice versa by means of a second control signal. To this end, the second control signal can be applied to a terminal of the second semiconductor switch, for example (in the case of a field effect transistor) the gate terminal.

[0013] The determining unit can be configured to identify a fault in the switching of the first semiconductor switch from the open switch state to the closed switch state. Additionally or alternatively, the determining unit can be configured to identify a fault in the switching of the second semiconductor switch from the open switch state to the closed switch state. The determining unit can be configured to identify whether the second switch correctly switches from the closed switch state to the open switch state based on the curve of the second voltage. The determining unit can be configured to identify whether the second switch correctly switches from the open switch state to the closed switch state based on the curve of the second voltage. In other words, the determining unit is able to identify whether the first and / or the second semiconductor switch can or can not (correctly) be transferred from the open switch state to the closed switch state.

[0014] The system for identifying a fault in the switching of a semiconductor switch can also be referred to as a system for identifying a fault in the switching of a semiconductor switch. The fault can be identified manually, for example by considering the curve of the first and / or second voltage or a signal derived from the curve of the first and / or second voltage. Alternatively, the fault can be identified in an automated manner by an identifying component based on the curve of the first and / or second voltage or a signal derived from the curve of the first and / or second voltage. The system can also have an identifying component. The identifying component can be configured to identify a fault in the switching of the first semiconductor switch based on the output signal. Additionally or alternatively, the identifying component can be configured to identify a fault in the switching of the second semiconductor switch based on the output signal.

[0015] To obtain the first voltage drop across the first resistor, a first voltage obtaining component, e.g. a voltmeter / volt ohm meter, can be provided. The first voltage obtaining component can be configured to obtain a profile of the first voltage drop across the first resistor. The first resistor can be part of the first voltage divider. To obtain the second voltage drop across the second resistor, a second voltage obtaining component, e.g. a voltmeter / volt ohm meter, can be provided. The second voltage obtaining component can be configured to obtain a profile of the second voltage drop across the second resistor. The second resistor can be part of the second voltage divider.

[0016] The first semiconductor device can be configured as a semiconductor diode. The semiconductor diode will be referred to as first semiconductor diode in the following. The first semiconductor diode can form a first semiconductor device pair with the first semiconductor switch. The first semiconductor diode can be arranged to form a first path with the first resistor when the first semiconductor switch is in an open circuit state. The first semiconductor diode can be configured to prevent a current from flowing through the first path formed when the first semiconductor switch is in an open circuit state. Because one end of the first resistor, regardless of whether the first resistor is part of the first voltage divider, is connected between the first semiconductor switch and the first semiconductor diode, the resistor and the first semiconductor diode form a series circuit as the first path when the first semiconductor switch is in an open switch state. In this case, a current can flow into the first resistor via the first semiconductor device and tamper the result of the determination unit regarding whether the first semiconductor switch is switched correctly. To reduce or even prevent such tampering, the first semiconductor diode can be arranged to prevent a current from flowing through the first semiconductor diode in the direction of the first resistor connected in series when the first semiconductor switch is open. In this way, the accuracy of the determination can be improved.

[0017] The second semiconductor device can be configured as a semiconductor diode. The semiconductor diode will be referred to as second semiconductor diode in the following. The second semiconductor diode can form a second semiconductor device pair with the second semiconductor switch. The second semiconductor diode can be arranged to form a second path with the second resistor when the second semiconductor switch is in an open circuit state. The second semiconductor diode can be configured to prevent a current from flowing through the second path formed when the second semiconductor switch is in an open circuit state. Because one end of the second resistor is connected between the second semiconductor switch and the second semiconductor diode, the resistor and the second semiconductor diode form a series circuit as the second path when the second semiconductor switch is in an open switch state. In this case, a current can flow into the second resistor via the second semiconductor device and tamper the result of the determination unit regarding whether the second semiconductor switch is switched correctly. To reduce or even prevent such tampering, the second semiconductor diode can be arranged to prevent a current from flowing through the second semiconductor diode in the direction of the second resistor connected in series when the second semiconductor switch is open. In this way, the accuracy of the determination can be improved.

[0018] The first semiconductor device can be configured as a semiconductor switch. The first semiconductor device configured as a semiconductor switch can be connected anti-serially to the first semiconductor switch. Anti-serial here can be understood as two components, i.e. semiconductor switches, connected in series with opposite polarity. Two semiconductor switches connected in this way can form a first semiconductor switch pair and can be called as such. The semiconductor switches of the first semiconductor switch pair can be controlled by a first control signal. For example, in each case the same terminal, e.g. the gate terminal, of the semiconductor switches of the first semiconductor switch pair can be controlled by the first control signal.

[0019] The second semiconductor device can be configured as a semiconductor switch. The second semiconductor device configured as a semiconductor switch can be connected anti-serially to the second semiconductor switch. Anti-serial here can be understood as two components, i.e. semiconductor switches, connected in series with opposite polarity. Two semiconductor switches connected in this way can form a second semiconductor switch pair and can be called as such. The semiconductor switches of the second semiconductor switch pair can be controlled by a second control signal. For example, in each case the same terminal, e.g. the gate terminal, of the semiconductor switches of the second semiconductor switch pair can be controlled by the second control signal.

[0020] The system can have a first voltage divider circuit. The first voltage divider circuit can have a first resistor and at least one additional resistor. One end of the first voltage divider circuit can be connected between the first semiconductor switch and the first semiconductor device. The other end of the first voltage divider circuit can be connected to a reference potential, e.g. ground. For example, the first resistor can be the resistor of the voltage divider circuit which is directly connected to the reference potential, e.g. ground. With the help of the voltage divider circuit, the voltage across the first resistor can for example be brought down to a value which can be input to and processed by a first comparison component, which will be explained in the following.

[0021] The system can have a second voltage divider circuit. The second voltage divider circuit can have a second resistor and at least one additional resistor. One end of the second voltage divider circuit can be connected between the second semiconductor switch and the second semiconductor device. The other end of the second voltage divider circuit can be connected to a reference potential, e.g. ground. The second resistor can for example be the resistor of the voltage divider circuit which is directly connected to the reference potential, e.g. ground. With the help of the voltage divider circuit, the voltage across the second resistor can for example be brought down to a value which can be input to and processed by a second comparison component, which will be explained in the following.

[0022] The determining unit can have a first comparing component. The first comparing component can be configured to determine a first comparison curve by comparing a curve of the first voltage with a curve of a reference voltage falling across a reference resistor. One end of the reference resistor can be connected to a voltage source. The other end of the reference resistor can be connected to a reference potential, e.g. ground. The voltage source can be connected to the first semiconductor switch, the first semiconductor device, the second semiconductor switch and / or the second semiconductor device.

[0023] The system can have a reference voltage divider. The reference voltage divider can have a reference resistor and at least one additional resistor. In other words, the reference resistor can be part of the reference voltage divider. One end of the reference voltage divider can be connected to a voltage source or said voltage source. The other end of the reference voltage divider can be connected to a reference potential, e.g. ground. The reference resistor can for example be a resistance of the reference voltage divider directly connected to the reference potential, e.g. ground.

[0024] The first comparing component can have or be configured as a first comparator. The first comparator can be formed / implemented by one or more operational amplifiers and other components. The first comparing component can be configured to determine a first comparison curve of an electrical variable of the first semiconductor switch with a reference value or a reference value curve. The comparison curve can for example be determined by comparing a curve of the first voltage with a curve of a reference voltage falling across a reference resistor. This applies regardless of whether the reference resistor is a reference voltage divider or part of a reference voltage divider. The reference voltage can be largely constant.

[0025] The determining unit can have a second comparing component. The second comparing component can be configured to determine a second comparison curve by comparing a curve of the second voltage with a curve of a reference voltage falling across a reference resistor. The second comparing component can have or be configured as a second comparator. The second comparator can be formed / implemented by one or more operational amplifiers and other components. The second comparing component can be configured to determine a second comparison curve of an electrical variable of the second semiconductor switch

[0026] The determining unit can have a first logic component. The first logic component can be configured to determine a first logic signal by combining the first comparison curve with a first control signal. The first logic component can have or be configured as an exclusive OR gate (XOR gate).

[0027] The determining unit can have a second logic component. The second logic component can be configured to determine the second logic signal by combining the second comparison curve with the second control signal. For example, the second logic component can have or be configured as an XOR gate.

[0028] The determining unit can also have a third logic component. The third logic component can be configured to determine the output signal by combining the first logic signal with the second logic signal. The third logic component can have or be configured as an OR gate.

[0029] The system can also have a time delay element, which is also referred to herein as a delay element. The delay element can be configured to determine the fault signal by applying an on-delay. The delay element can be configured to determine the fault signal by combining the output signal with the on-delay. With the help of the delay element, errors in the diagnosis can be at least reduced, if not completely avoided, which are caused by signal transmission times and switching delays.

[0030] The system can have a phase generator. The phase generator can be configured to generate the first control signal, for example, from a clock signal. Additionally or alternatively, the phase generator can be configured to generate the second control signal, for example, from the clock signal. The phase generator can thus be configured to alternate the on of the present semiconductor switches.

[0031] Although reference is made herein to a first and a second semiconductor switch, the present application is not limited to the identification of an unswitched semiconductor switch from exactly two parallel connected semiconductor switches. For example, three or more than three semiconductor switches can also be connected in parallel. In other words, a system for identifying an unswitched semiconductor switch from at least two parallel connected semiconductor switches can be provided. For example, a first semiconductor switch, a second semiconductor switch and at least one third semiconductor switch can be connected in parallel to each other. In this case, the system can identify an unswitched semiconductor switch from the first semiconductor switch, the second semiconductor switch and the at least one third semiconductor switch. If the first and / or the second semiconductor switch is no longer able to switch from an open state to a closed state, an emergency operation can be ensured with the help of the at least one third semiconductor switch. If there is no at least one third semiconductor switch, the load would be switched off at least for a short time in the above-mentioned case.

[0032] If the first semiconductor device and the second semiconductor device are both configured as semiconductor switches and accordingly form a pair of semiconductor switches, respectively, although it is mentioned herein to the first and second pair of semiconductor switches, the present application is not limited to identifying the non-switched semiconductor switch of a pair of semiconductor switches or the pair of semiconductor switches of exactly two parallel connected pairs of semiconductor switches. For example, three or more than three pairs of semiconductor switches can be parallel connected as well. In other words, a system for identifying the non-switched semiconductor switch or the pair of semiconductor switches from at least two parallel connected pairs of semiconductor switches can be provided. For example, a first pair of semiconductor switches, a second pair of semiconductor switches and at least one third pair of semiconductor switches can be parallel connected to each other. In this case, the system can identify the non-switched semiconductor or the non-switched pair of semiconductor switches from the first pair of semiconductor switches, the second pair of semiconductor switches and the at least one third pair of semiconductor switches. If the first and / or the second pair of semiconductor switches is no longer able to be switched from an open state to a closed state, an emergency operation can be ensured by means of the at least one third pair of semiconductor switches. If there is no at least one third pair of semiconductor switches, the load would be switched off at least for a short time in the above-mentioned case.

[0033] The system can be part of a power distribution system such as for example a power distribution system having high requirements in terms of functional safety and / or reliability. It is generally in power distribution systems and in particular in power distribution systems having high safety requirements important to be able to identify and / or verify the operability of the used semiconductor switches, especially without adversely affecting a load connected downstream of the semiconductor switches, preferably during operation.

[0034] The first semiconductor switch can be configured as a power semiconductor / power semiconductor switch. Additionally or alternatively, the second semiconductor switch can be configured as a power semiconductor / power semiconductor switch. For example, all semiconductor switches of the parallel connected pairs of semiconductor switches present can be configured as power semiconductors / power semiconductor switches. The system can be embedded into a power distributor of a complete system such as for example can be part of a power distributor of a complete system. The complete system can have at least one voltage source for current supply (power supply) and at least one consumer. The power distributor can be located between the at least one voltage source and the at least one consumer. The power distributor can distribute the current provided by the at least one voltage source to the at least one consumer. The first semiconductor switch and / or the second semiconductor switch can be arranged in the power distributor in order to switch on (connect to the at least one voltage source) or switch off (disconnect from the at least one voltage source) the at least one consumer. The at least one voltage source and / or the at least one consumer can be arranged on both the input side of the power distributor and the output side of the power distributor.

[0035] Arranging the semiconductor switches anti-serially in pairs, i.e. forming pairs of semiconductor switches, has the advantage of bidirectional operation. Thus, the system can have, for example, two voltage sources, for example one at the input side and one at the output side. The system can also have two consumers, for example one at the input side and one at the output side. The first semiconductor switch of the first pair of semiconductor switches can be arranged, for example, to switch on (connect to the voltage source) or switch off (disconnect from the voltage source) the first consumer. The other semiconductor switch of the first pair of semiconductor switches can be arranged, for example, to switch on (connect to the voltage source) or switch off (disconnect from the voltage source) the other consumer. The second pair of semiconductor switches can function accordingly and provide redundancy for the system.

[0036] The first semiconductor switch can be configured as a field effect transistor. The first semiconductor device can be configured in the form of a diode or a field effect transistor. The second semiconductor switch can be configured as a field effect transistor. The second semiconductor device can be configured as a diode or a field effect transistor.

[0037] According to a second aspect of the application, a method for identifying non-switching semiconductor switches is provided. The method comprises controlling a first semiconductor switch by means of a first control signal. The method further comprises controlling a second semiconductor switch connected in parallel with the first semiconductor switch by means of a second control signal. The method further comprises identifying whether the first semiconductor switch is non-switching based on a curve of a first voltage drop across a first resistor. One end of the first resistor is connected between the first semiconductor switch and a first semiconductor device. The other end of the first resistor is connected to a reference potential, for example ground. The first semiconductor device is configured and arranged to prevent current flow through the first semiconductor device in at least one direction. The method comprises identifying whether the second semiconductor switch is non-switching based on a curve of a second voltage drop across a second resistor. One end of the second resistor is connected between the second semiconductor switch and a second semiconductor device. The other end of the second resistor is connected to a reference potential, for example ground. The second semiconductor device is configured and arranged to prevent current flow through the second semiconductor device in at least one direction.

[0038] Although some of the aspects described above have been described in relation to the system, these aspects can also be implemented in the method in a corresponding manner. BRIEF DESCRIPTION OF DRAWINGS

[0039] The present disclosure will be further explained with reference to the accompanying drawings. These drawings show schematically:

[0040] Figure 1 for a complete system with current sources, consumers and consumers;

[0041] Figure 2 for Figure 1 possible configurations of the consumer in the middle;

[0042] Figure 3a Fig. 1 shows a possible configuration of a switching system according to exemplary embodiments, which can be used in a power distributor of Figure 2 Fig. 2 shows a possible configuration of a switching system according to exemplary embodiments, which can be used in a power distributor of

[0043] Figure 3b Fig. 3 shows a possible configuration of a switching system according to exemplary embodiments, which can be used in a power distributor of Figure 2 Fig. 4 shows a possible configuration of a switching system according to exemplary embodiments, which can be used in a power distributor of

[0044] Figure 4a Fig. 5 shows exemplary signal curves of electrical variables used in the system of Figure 3a Fig. 6 shows exemplary signal curves of electrical variables used in the system of 3b. DETAILED DESCRIPTION

[0045] The specific details are set forth in the following to provide a thorough understanding of the disclosure, but not limited thereto. It will be apparent to those skilled in the art that the disclosure can be used in other exemplary embodiments that differ from those set forth below without departing from the scope of the disclosure. For example, the specific configuration and form of the system are described below without being considered limiting.

[0046] Figure 1 A power distribution system is shown in diagrammatic form, which has a voltage source 10 as a current source, a power distributor 20 and a consumer 40. The voltage source 10 has a positive terminal 12 and a negative terminal 14. The power distributor 20 has a positive terminal 22 and a negative terminal 26 on the input side. The power distributor 20 also has a positive terminal 24 on the output side. The power distributor 20 has a switching system 30, with which the consumer 40 can be switched on and off. The switching system 30 has a controller 28. The controller 28 can be a higher-level controller. The consumer 40 has a positive terminal 42 and a negative terminal 44.

[0047] The negative terminal 14 of the voltage source 10, the negative terminal 26 of the power distributor 20 and the negative terminal 44 of the consumer 40 are each connected to earth / ground 50. The voltage source 10, the power distributor 20 and the consumer 40 thus have the same reference potential, in this case, for example, the earth / ground 50.

[0048] The voltage source 10 is connected via its positive terminal 12 to the positive terminal 22 on the input side of the power distributor 20. In addition or alternatively, the voltage source as a current source can be connected on the output side to the power distributor 10. The power distributor 20 is connected on the output side via its positive terminal 24 on the output side to the consumer 40. Although only one consumer 40 is shown as an example, it is possible in this way, for example, to connect several consumers via the positive terminal 24 of the power distributor 20 and the negative terminal 44 of the consumer 40 to the power distributor 20. The power distributor 20 can also be connected to other consumers via the negative terminal 26 of the power distributor 20 and the positive terminal 42 of the consumer 40. Figure 1The other positive terminal on the output side (not shown) outputs the multiple consumer 40 to the power distributor 20. Additionally or alternatively, one or more consumers can also be connected to the power distributor 20 at the input. The switching system 30 is configured to switch on and switch off the consumer 40. In the case of multiple consumers, the system is correspondingly configured to switch on and switch off each of the multiple consumers. If switching off is not possible, the switching system 30 provides a corresponding fault message to the controller 28. The power distribution system can be, in particular, a power distribution system with high requirements in terms of safety (and / or with high requirements in terms of reliability). In such a system, it is more important to be able to verify the operability of the switches used (for switching on and switching off the consumer 40).

[0049] If the voltage source as power source and the one or more consumers are arranged on both the input side and the output side, it is advantageous if the power distributor 20 is able to work bidirectionally.

[0050] Figure 2 An exemplary configuration of the power distributor 20 from Figure 1 is shown. The power distributor 20 has a positive terminal 22 on the input side. The power distributor 20 also has a positive terminal 24 on the output side. The power distributor also has a controller 28. For the sake of simplicity, Figure 1 The negative terminal of the power distributor in Figure 2 is not shown in Figure 2 In Figure 1 , an exemplary configuration of the switching system 30 from is shown. According to this example, the switching system 30 has a phase generator 32, a first semiconductor switch pair 34, a second semiconductor switch pair 36 and a determination unit 38 which can have, for example, two comparators. The first semiconductor switch pair 34 and the second semiconductor switch pair 36 are used to switch on and switch off the consumer 40. In particular, the reliability of the switching-off function is to be monitored. The first semiconductor switch pair 34 and the second semiconductor switch pair 36 are connected to one another in parallel.

[0051]

[0051] The phase generator 32 controls the first semiconductor switch pair 34 and the second semiconductor switch pair 36, for example, by means of the control signals generated, respectively. The first semiconductor switch pair 34 is controlled with a first control signal. The second semiconductor switch pair 36 is controlled with a second control signal. As will be explained in more detail hereinafter with regard to Figure 3a and 3b , a curve of a first voltage drop across a resistor connected to the first semiconductor switch pair 34 is determined. A curve of a second voltage drop across a resistor connected to the second semiconductor switch pair 36 is further determined.

[0052] Based on the curve of the first voltage drop across the resistor connected to the first semiconductor switch pair 34, the determining unit 38 can identify a fault in the switching of the first semiconductor switch pair 34. Based on the curve of the second voltage drop across the resistor connected to the second semiconductor switch pair 36, the determining unit 38 can identify a fault in the switching of the second semiconductor switch pair 36. For example, the acquired voltages can be compared in the determining unit 38 with reference voltage values, respectively. The determining unit 38 can generate an output signal from each voltage. From this output signal it can be concluded whether the first semiconductor switch pair 34 and / or the second semiconductor switch pair 36 actually switched as expected, in particular turned off as expected, or whether they can be turned off. If a fault in the switching, in particular in the turning off, is detected, the controller 28 is informed, for example. The controller 28 as a superior authority can take corresponding measures, for example, it can turn off the consumer 40 itself or disconnect it from the power distributor 20 or turn it into a safe state, for example.

[0053] Figure 3a A specific configuration of the switching system 30 is shown, more specifically a possible circuit as a hardware implementation. The switching system 30 has a phase generator 32. The phase generator 32 is configured to generate a first control signal V phase1 and a second control signal V phase2 from a clock signal. The first control signal V phase1 is input to a first gate driver 60a. The second control signal V phase2 is input to a second gate driver 60b. The first gate driver 60a is connected to gate terminals of a first semiconductor switch pair 34. The first semiconductor switch pair 34 has two semiconductor switches, namely a semiconductor switch 34a and a semiconductor switch 34b as an example of a semiconductor device, which are both configured as MOSFETs in the example, and are therefore referred to as MOSFET 34a and MOSFET 34b in the following. Thus, with regard to the first semiconductor switch pair 34, by way of example, the semiconductor switch pair 34 is referred to as first MOSFET pair 34a. Figure 3a The second gate driver 60b is connected to gate terminals of a second semiconductor switch pair 36. The second semiconductor switch pair 36 has two semiconductor switches, namely a semiconductor switch 36a and a semiconductor switch 36b as an example of a semiconductor device, which are both configured as MOSFETs in the example, and are therefore referred to as MOSFET 36a and MOSFET 36b in the following. Thus, with regard to the second semiconductor switch pair 36, by way of example, the semiconductor switch pair 36 is referred to as second MOSFET pair 36. Figure 3a Figure 3a Figure 3a

[0054] ​​​The drain terminal of the MOSFET 34a of the first MOSFET pair 34 is connected to a voltage source 10 which provides the current for the switching system 30. Alternatively, the drain terminal of the MOSFET 34a of the first MOSFET pair 34 can be connected to a load. Furthermore, in addition to the voltage source 10, a load can also be provided on the input side of the circuit, so that in this case the drain terminal of the MOSFET 34a of the first MOSFET pair 34 would be connected to the voltage source 10 and to the load.

[0055] The MOSFET 34b of the first MOSFET pair 34 is connected in anti- series to the MOSFET 34a of the first MOSFET pair 34. In this particular case of MOSFETs, anti-series means that although the two MOSFETs 34a, 34b are connected in series, the source terminals of the two MOSFETs 34a, 34b are connected together. The two MOSFETs 34a, 34b thus differ in their blocking direction, that is to say in the direction in which they block. Although not apparent from the figure, for technical reasons, the MOSFETs 34a, 34b can each intrinsically have / contain a so-called parasitic body diode in parallel with the switchable channel. This body diode prevents the MOSFET 34a, 34b in question from being able to block the forward direction of the body diode. The MOSFET pair 34 thus ensures blocking in both directions. In other words, the presence of the MOSFET pair 34 (with two anti-series MOSFETs 34a, 34b) makes it possible for blocking to occur in both directions, compared to just one MOSFET.

[0056] The source terminal of the MOSFET 34a of the first MOSFET pair 34 is connected accordingly to the source terminal of the MOSFET 34b of the first MOSFET pair 34. The drain terminal of the MOSFET 34b of the first MOSFET pair 34 is connected via a variable resistor to ground / earth as a reference potential, which shows Figure 3a a circuit from Figure 1 and thus also the load 40, which is denoted by the reference numeral 40. That is to say, in Figure 3a , the drain terminal of the MOSFET 34b of the first MOSFET pair 34 is connected to the load 40. Alternatively, the drain terminal of the MOSFET 34b of the first MOSFET pair 34 can be connected to a voltage source. Furthermore, in addition to the load 40, a voltage source can also be provided on the output side of the circuit, so that in this case the drain terminal of the MOSFET 34b of the first MOSFET pair 34 would be connected to the load 40 and to the voltage source. In particular in switching systems for automotive components, for redundancy reasons, a voltage source and a load are usually provided on both the input side and the output side, that is to say on both sides.

[0057] The drain terminal of the MOSFET 36a of the second MOSFET pair 36 is connected to the voltage source 10. Alternatively, the drain terminal of the MOSFET 36a of the second MOSFET pair 36 can be connected to a load. Furthermore, in addition to the voltage source 10, a load can also be provided on the input side of the circuit, so that in this case the drain terminal of the MOSFET 36a of the second MOSFET pair 36 would be connected to the voltage source 10 and to the load.

[0058] The MOSFET 36b of the second MOSFET pair 36 is connected in anti- series to the MOSFET 36a of the second MOSFET pair 36. Here, anti-series also means that, although the two MOSFETs 36a, 36b are connected in series, the source terminals of the two MOSFETs 36a, 36b thereof are connected together. Also in this case, the anti-series connection of the MOSFETs 36a, 36b forming the MOSFET pair 36 ensures blocking in both directions due to the respective parasitic diodes. In other words, the presence of the MOSFET pair 36 (with two anti-series MOSFETs 36a, 36b) makes it possible for blocking to occur in both directions compared to only one MOSFET.

[0059] The source terminal of the MOSFET 36a of the second MOSFET pair 36 is correspondingly connected to the source terminal of the MOSFET 36b of the second MOSFET pair 36. The drain terminal of the MOSFET 36b of the second MOSFET pair 36 is connected to ground / earth as a reference potential via the load 40 (also referred to as consumer 40). That is, in Figure 3a the drain terminal of the MOSFET 36b of the second MOSFET pair 36 is connected to the load 40. Alternatively, the drain terminal of the MOSFET 36a of the second MOSFET pair 36 can be connected to a voltage source. Furthermore, in addition to the load 40, a voltage source can also be provided on the output side of the circuit, so that in this case the drain terminal of the MOSFET 36b of the second MOSFET pair 36 can be connected to the load 40 and to the voltage source.

[0060] Figure 3a Three voltage divider circuits 62, 64, 66 are further shown in, which are referred to hereinafter simply as voltage dividers 62, 64, 66. The voltage divider 62 can also be referred to as a reference voltage divider 62, and in Figure 3a exactly two reference resistors 62a, 62b in the example of. In Figure 3aIn the example, voltage divider 64 has exactly two resistors 64a and 64b. One end of voltage divider 64 is connected between the two MOSFETs 34a and 34b of the first MOSFET pair 34, or in other words, connected to the connection of the source terminals of the MOSFETs 34a and 34b of the first MOSFET pair 34. The other end of voltage divider 64 is connected to ground, which serves as a reference potential. Figure 3a In the example, voltage divider 66 has exactly two resistors 66a and 66b. One end of voltage divider 66 is connected between the two MOSFETs 36a and 36b of the second MOSFET pair 36, or in other words, connected to the connection of the source terminals of the MOSFETs 36a and 36b of the second MOSFET pair 36. The other end of voltage divider 66 is connected to ground, which serves as a reference potential.

[0061] Voltage dividers 62, 64, and 66 can be considered as (e.g.) Figure 2 This is part of a specific embodiment of the determining unit 38. The voltage drop across the voltage divider 62 always has a value corresponding to the voltage U1 of the voltage source 10. Therefore, the voltage drop across the voltage divider 62 is known. The voltage drop across each of the resistors 62a and 62b can be known from the ratio of their resistance values. For example, if the resistance values ​​of resistors 62a and 62b are equal, then the voltage drop across each resistor 62a and 62b is equal, more precisely, half the voltage of the voltage source 10, respectively. Typically, the voltage drop across resistor 62b has the following known voltage divider formula:

[0062] U_wid62b=U1*R_wid62b / (R_wid62a+R_wid62b),

[0063] Where U_wid62b represents the voltage drop across resistor 62b, U1 represents the voltage of voltage source 10, R_wid62a represents the resistance value of resistor 62a, and R_wid62b represents the resistance value of resistor 62b.

[0064] The voltage drop across the voltage divider 64 is different depending on whether the MOSFETs 34a, 34b of the first MOSFET pair 34 are closed or open. If the MOSFETs 34a, 34b of the first MOSFET pair 34 are in a closed state, the voltage drop across the voltage divider 64 has a value corresponding to the voltage value of the voltage source 10. The voltage drop across each of the resistors 64a, 64b is given by the ratio of the resistance values of the resistors 64a, 64b. For example, if the resistance values of the resistors 64a, 64b are equal, the voltage drop across each of the resistors 64a, 64b is equal, more specifically, in the case of closed MOSFETs 34a, 34b of the first MOSFET pair 34, each half of the voltage U1 of the voltage source 10. If the MOSFETs 34a, 34b of the first MOSFET pair 34 are in an open state, the voltage drop across the MOSFET 34a of the first MOSFET pair 34 is relatively high, and thus, the voltage drop at the voltage divider 64 is significantly lower than in the case of closed MOSFETs 34a. In the case of open MOSFETs 34a, the voltage drop across the voltage divider 64 can even be close to or at 0 V. The voltage drop across each of the resistors 64a, 64b is given by the ratio of the resistance values of the resistors 64a, 64b, and then likewise very low or even at least almost 0 V. For example, if the resistance values of the resistors 64a, 64b are equal, the voltage drop across each of the resistors 64a, 64b is equal but very low, more specifically, in the case of open MOSFETs 34a, 34b of the first MOSFET pair 34, each has a very low voltage, for example at least almost 0 V.

[0065] The voltage drop across voltage divider 66 varies depending on whether MOSFETs 36a and 36b of the second MOSFET pair 36 are closed or open. If MOSFETs 36a and 36b of the second MOSFET pair 36 are closed, the voltage drop at voltage divider 66 has a value corresponding to the voltage of voltage source 10. The voltage drop across each of resistors 66a and 66b is given by the ratio of the resistance values ​​of resistors 66a and 66b. For example, if the resistance values ​​of resistors 66a and 66b are equal, the voltage drop across each of resistors 66a and 66b is equal, more specifically, in the case where MOSFETs 36a and 36b of the second MOSFET pair 36 are closed, it is half the voltage U1 of voltage source 10, respectively. If MOSFETs 36a and 36b of the second MOSFET pair 36 are open, the voltage drop across MOSFET 36a of the second MOSFET pair 36 is relatively high, and the voltage drop at voltage divider 66 is significantly lower than in the case where MOSFET 36a is closed. With the open-circuit MOSFET 36a, the voltage drop across the voltage divider 66 may even be close to 0V or 0V. The voltage drop across each of the resistors 66a and 66b is given by the ratio of the resistance values ​​of the resistors 66a and 66b, and is also very low or even at least almost 0V. For example, if the resistance values ​​of the resistors 66a and 66b are equal, the voltage drop across each resistor 66a and 66b is equal but very low, more specifically, in the case of the open-circuit MOSFETs 36a and 36b of the second switch pair MOSFET 36, there are very low voltages, for example, at least almost 0V.

[0066] The voltage drop across resistors 62b, 64b, and 66b connected to ground in the three voltage dividers 62, 64, and 66 is input to two comparators 70a and 70b. More specifically, the reference voltage V_ref across the reference resistor 62b is input to the negative (inverting) input of the first comparator 70a and the negative (inverting) input of the second comparator 70b. Furthermore, the voltage V_mos1 across resistor 64b in voltage divider 64 is input to the positive (non-inverting) input of the first comparator 70a. Additionally, the voltage V_mos2 across resistor 66b in voltage divider 66 is input to the positive (non-inverting) input of the second comparator 70b. Therefore, both the negative (inverting) input of the first comparator 70a and the negative (inverting) input of the second comparator 70b are fed the same reference voltage V_ref.

[0067] exist Figure 3a In the example shown, comparators 70a and 70b are configured as non-inverting comparators. In such a non-inverting comparator, the reference voltage, i.e., at... Figure 3athe case of a reference voltage V_ref connected to the inverting input of the comparator. The respective curves of the input signals, here the voltages V_mos1 across resistor 64b of the voltage divider 64 and V_mos2 across resistor 66b of the voltage divider 66, are connected to the non-inverting input of the comparator, respectively. In the non-inverting comparator, if the input voltage is smaller than the reference voltage, a digital 0 (low level) is output as output. Conversely, if the input voltage is equal to or larger than the reference voltage, a digital 1 (high level) is output. Alternatively, Figure 3a Inverted comparators can be provided in the comparator stage 70. The comparators 70a, 70b can each consist of one or more operational amplifiers and / or other components.

[0068] The output of the first comparator 70a is connected to a first XOR gate 72a. The first XOR gate 72a thus receives the output signal V_comp1 of the first comparator 70a as a first input variable. The output of the second comparator 70b is connected to a second XOR gate 72b. The second XOR gate 72b thus receives the output signal V_comp2 of the second comparator 70b as a first input variable. The first XOR gate 72a receives a first control signal V_phase1 as a second input variable. The second XOR gate 72b receives a second control signal V_phase2 as a second input variable. The first XOR gate 72a accordingly performs an XOR operation of the output (signal V_comp1) of the first comparator 70a and the first control signal V_phase1. The second XOR gate 72b accordingly performs an XOR operation of the output (signal V_comp2) of the second comparator 70b and the second control signal V_phase2.

[0069] The output (signal V_out1) of the first XOR gate 72a and the output (signal V_out2) of the second XOR gate 72b are input as input variables to an OR gate 74. The output of the OR gate 74 is thus the superposition of the outputs of the first and second XOR gates 72a, 72b. For example, a problem or a fault in the switching of the first MOSFET pair 34a and / or the second MOSFET pair 34b can be deduced from the output signal (signal V_out3) of the OR gate.

[0070] The identification of a fault in the switching can be improved by connecting a time delay element 76 downstream of the OR gate 74. This can be achieved by the so-called spikes (a spike can be understood as a short peak, i.e. a peak with a duration below a predetermined time threshold) being excluded by the time delay element 76. The time delay element 76 causes only anomalies with a duration above the predetermined time threshold to be identified as a fault. The signal output by the time delay element 76 can thus be referred to as a fault signal V_fehler. In other words, the time delay element 76 can be referred to as a turn-on delay, the result of which is that only fault signals or peaks of the fault signal above a certain length are evaluated as valid, that is to say actual / valid faults.

[0071] Reference is made to Figure 3a , Figure 2 The determining unit in Figure 3a may be implemented, for example, by the voltage dividers 62, 64, 66, the comparators 70a, 70b, the XOR gates 72a, 72b and the OR gate 74. Alternative embodiments are possible in which one or more of the above-mentioned components are omitted or replaced and / or other components are added. Thus, Figure 3a are merely to be regarded as examples of a hardware implementation of the switching system of Figure 2 .

[0072] Figure 3b Variations of the specific configuration of Figure 3a are shown, more specifically, as variations of possible circuits of a hardware implementation of the switching system of Figure 2 . Figure 3b The variations of Figure 3a differ from the configuration of Figure 3b in that the semiconductor diodes 34c, 36c are used instead of the MOSFET 34b of the first MOSFET pair 34 and instead of the MOSFET 36b of the second MOSFET pair 36, respectively. In the example of Figure 3b , the MOSFET 34b and the MOSFET 36b are each replaced by a semiconductor diode. Alternatively, the MOSFET 34a and the MOSFET 36a can each be replaced by a semiconductor diode 34c, 36c. Combinations are possible. In Figure 3b , thus, there are no MOSFET pairs as in Figure 3a , but semiconductor device pairs 34, 36. Figure 3b Each of the semiconductor device pairs 34, 36 of

[0073] The following applies to Figure 3b with respect to the voltage values V_ref, V_mos1, V_mos2 input to the comparators 70a, 70b.

[0074] The voltage drop across the voltage divider 62 always has a value corresponding to the value of the voltage U1 of the voltage source 10. Thus, the voltage drop across the voltage divider 62 is known. From the ratio of the resistance values of the resistors 62a, 62b, the voltage drop across each of the resistors 62a, 62b is known. For example, if the resistance values of the resistors 62a, 62b are equal, the voltage drop across each of the resistors 62a, 62b is equal, more specifically, half of the voltage of the voltage source 10, respectively.

[0075] The voltage drop across the voltage divider 64 is different depending on whether the MOSFET 34a of the first semiconductor device pair 34 is closed or open. If the MOSFET 34a of the first semiconductor device pair 34 is in a closed state, the voltage drop across the voltage divider 64 has a value corresponding to the value of the voltage Ul of the voltage source 10. The voltage drop across each resistor 64a, 64b is given by the ratio of the resistance values of the resistors 64a, 64b. For example, if the resistance values of the resistors 64a, 64b are equal, the voltage drop across each of the resistors 64a, 64b is equal, more specifically, in the case of a closed MOSFET 34a of the first semiconductor device pair 34, half of the voltage of the voltage source 10, respectively. If the MOSFET 34a of the first MOSFET pair 34 is in an open state, the voltage drop across the MOSFET 34a of the first MOSFET pair 34 is relatively high, and in consequence, the voltage drop at the voltage divider 64 is significantly lower than in the case of a closed MOSFET 34a.

[0076] In the case of an open MOSFET 34a, the voltage drop across the voltage divider 64 can even be close to or 0 V. However, the current in the direction of the voltage divider 64 will significantly change this value and thus cause falsification of the measurement result. Due to the high resistance of the open MOSFET 34a, the current will flow via the voltage divider 64 to a considerable extent, if not exclusively. Such a current can for example originate from the path with the closed MOSFET 36a. Additionally or alternatively, such a current can be a backflow from the load 40. Additionally or alternatively, such a current can originate from a voltage source connected on the output side instead of the load 40, or in addition to the load 40. If necessary, the semiconductor diode 34b ensures that no or at least almost no current flows into the voltage divider 64 in the blocking direction of the semiconductor diode 34c when the MOSFET 34a is open. The voltage drop across each of the resistors 64a, 64b is given by the ratio of the resistance values of the resistors 64a, 64b, and then likewise very low or even at least almost 0 V. For example, if the resistance values of the resistors 64a, 64b are equal, the voltage drop across the resistors 64a, 64b is equal but very low, more specifically, in the case of an open MOSFET 34a of the first semiconductor device pair 34, very low voltages of for example at least almost 0 V, respectively.

[0077] The voltage drop across the voltage divider 66 is different depending on whether the MOSFET 36a of the second semiconductor device pair 36 is closed or open. If the MOSFET 36a of the second semiconductor device pair 36 is in a closed state, the voltage drop across the voltage divider 66 has a value corresponding to the voltage U1 value of the voltage source 10. The voltage drop across each of the resistors 66a, 66b is given by the ratio of the resistance values of the resistors 66a, 66b. For example, if the resistance values of the resistors 66a, 66b are equal, the voltage drop across each of the resistors 66a, 66b is equal, more specifically, in the case of a closed MOSFET 36a of the second semiconductor device pair 36, half of the voltage of the voltage source 10, respectively.

[0078] If the MOSFET 36a of the second semiconductor device pair 36 is in an open state, the voltage drop across the MOSFET 36a of the second semiconductor device pair 36 is relatively high, and thus the voltage drop at the voltage divider 66 is significantly lower than in the case of a closed MOSFET 36a. In the case of an open MOSFET 36a, the voltage drop across the voltage divider 66 can even be close to or at 0 V. However, the current in the direction of the voltage divider 66 will significantly change this value and thus lead to falsification of the measurement result. Due to the high resistance of the open MOSFET 36a, the current will flow, if not exclusively, to a considerable extent via the voltage divider 66. Such a current can for example originate from the path with the closed MOSFET 34a. Additionally or alternatively, such a current can be a backflow from the load 40. Additionally or alternatively, such a current can originate from a voltage source connected on the output side instead of the load 40, or in addition to the load 40. If necessary, the semiconductor diode 36c ensures that no or at least almost no current flows in the blocking direction of the semiconductor diode 36c into the voltage divider 66 when the MOSFET 34a is open. The voltage drop across each of the resistors 66a, 66b is given by the ratio of the resistance values of the resistors 66a, 66b, and then likewise very low or even at least almost 0 V. For example, if the resistance values of the resistors 66a, 66b are equal, the voltage drop across each of the resistors 66a, 66b is equal but very low, more specifically, in the case of an open MOSFET 36a of the second semiconductor device pair 36, very low voltages of for example at least almost 0 V, respectively.

[0079] Figure 3b The remaining part of the circuit corresponds to the circuit of Figure 3a . Thus, in this respect reference is made to the above explanations regarding Figure 3a .

[0080] The operation of the circuit will now be described in more detail with reference to exemplary signal curves from Figure 4a and 4b . Figure 3aof the configuration. The explanations apply correspondingly to the variants with the differences described above with respect to Figure 3b the variants. Figure 3b

[0081] In Figure 4a and 4b the signal curves over time are shown. In each case, the ordinate shows the respective electrical variable, for example the current or the voltage, and the abscissa shows the time. The abscissa is divided into a plurality of regions, more specifically nine regions, which are referred to here as time windows Z1 to Z9.

[0082] In this example, the MOSFETs 34a, 34b, 36a, 36b are configured as self-locking n-channel MOSFETs. Thus, the MOSFETs 34a, 34b, 36a, 36b are in an open state and do not conduct current when the voltage between gate and source does not exceed a threshold value (self-locking; also referred to as enhancement mode). Furthermore, the MOSFETs 34a, 34b, 36a, 36b are in a closed state and conduct current when the voltage between gate and source exceeds the threshold value. In each case, the threshold value is lower than the voltage of the supply voltage Vsup. Figure 4a and 4b the maximum value of the output signal of the gate driver 60a, 60b assumed as an example in

[0083] The clock signal V_clock is input into the phase generator 32. An example of such a clock signal V_clock can be seen in Figure 4a The phase generator 32 can generate the control signals V_phase1, V_phase2 from the clock signal V_clock. The associated gate drivers 60a, 60b are controlled by the two control signals V_phase1, V_phase2, respectively. The two control signals V_phase1, V_phase2 essentially have the same curve, but are offset by an amount relative to one another. As with the Figure 4a and 4b ​The exemplary signal curves in Fig. 6a show that the two control signals V_phase1, V_phase2 start in the first time window Z1 with a value of approximately 5 V. This corresponds to a high level, also referred to as HIGH (digital 1). The gate drivers 60a, 60b convert the control signals into a reference potential for the MOSFETs 34a, 34b and the MOSFETs 36a, 36b. It can thus be assumed that, for example, the curve of the output signal of the gate driver 60a corresponds to the curve of the control signal V_phase1, wherein the level of the output signal matches the MOSFETs 34a, 34b, such as, for example, is reduced compared to the control signal V_phase1. It can also be assumed, by way of example, that the curve of the output signal of the gate driver 60b corresponds to the curve of the control signal V_phase2, wherein the level of the output signal matches the MOSFETs 36a, 36b, for example, is reduced compared to the control signal V_phase2. The MOSFETs 34a, 34b and the MOSFETs 36a, 36b are each switched on when the voltage between gate and source exceeds a certain threshold value / threshold voltage. By way of example only, 4 V can be mentioned here as the threshold value. Due to the high level of the control signals V_phase1, V_phase2 and the output signals of the gate drivers 60a, 60b, there is a voltage between the gate and the source of the two MOSFETs 34a, 34b of the first MOSFET pair 34 and between the gate and the source of the two MOSFETs 36a, 36b of the second MOSFET pair 36 which exceeds the threshold value of the above-mentioned MOSFETs 34a, 34b, 36a, 36b. Both the MOSFETs 34a, 34b of the first MOSFET pair 34 and the MOSFETs 36a, 36b of the second MOSFET pair 36 are thus in a closed state.

[0084] With regard to Figure 3a The exemplary configuration of Fig. 6a shows that, when the MOSFETs 34a, 34b of the first MOSFET pair 34 are closed and when the MOSFETs 36a, 36b of the second MOSFET pair 36 are closed, the voltage drop across all voltage dividers 62, 64, 66 corresponds to at least approximately the voltage U1 of the voltage source 10. This is because the voltage drop across a closed MOSFET is at least approximately 0 V. Based on the grid rule, it can be seen that the voltage drop across the reference voltage divider 62 and across the voltage dividers 64, 66 is at least approximately the voltage U1 of the voltage source 10, respectively. In Figure 3aIn the example case, the resistance values of the voltage dividers 62, 64, 66 are such that when the MOSFETs 34a, 34b of the first MOSFET pair 34 are closed / switched on and when the circuit of the MOSFETs 36a, 36b of the second MOSFET pair is closed / switched on, the voltage drop across the resistors 64b, 66b is (significantly) greater than the voltage drop V_ref across the reference resistor 62b. This can be achieved by, for example, the ratio of the resistance value 64b to the resistance value 64a being (significantly) greater than the ratio of the resistance value 62b to the resistance value 62a and by the ratio of the resistance value 66b to the resistance value 66a being (significantly) greater than the ratio of the resistance value 62b to the resistance value 62a. Based on the voltage divider rule, in this case, even though the voltage drop across the respective voltage dividers 62, 64, 66 is the same as the voltage U1 overall, the voltage drop across the resistors 64b, 66b is (significantly) greater than the reference voltage V_ref across the resistor 62b. That is, when the MOSFETs 34a, 34b, 36a, 36b are closed, the voltage V_mos1 is (significantly) greater than the reference voltage V_ref and the voltage V_mos2 is (significantly) greater than the reference voltage V_ref. The comparator 70a receives the values of V_mos1, V_ref and the comparator 70b receives the values of V_mos2, V_ref as input values.

[0085] After a certain time, the first control signal V phase1 is set to a voltage of approximately 0 V for a time period T low1 within a first time window Z1. This corresponds to a low level, also called LOW level (digital 0). In this case, the voltage present between the gate and the source of the two MOSFETs 34a, 34b of the first MOSFET pair 34, if any, is only very low and below the threshold value of the MOSFETs 34a, 34b. The MOSFETs 34a, 34b thus change to an open state. During the same time period T low1 of the first time window Z1, the second control signal V phase2 continues to be at a high level. The MOSFETs 36a, 36b of the second MOSFET pair 36 thus remain closed. Because the MOSFETs 34a, 34b of the first MOSFET pair 34 are open in the first time period T low1 of the first time window Z1 and the MOSFETs 36a, 36b of the second MOSFET pair 36 are closed in the first time period T low1 of the first time window Z1, a change in the voltage drop across the voltage dividers 64, 66 can occur. Because the MOSFETs 36a, 36b of the second MOSFET pair 36 remain closed, the voltage drop across the voltage divider 66 does not change, that is to say, the voltage drop across the voltage divider 66 still substantially corresponds to the voltage across the reference voltage divider 62 and thus to the voltage U1 of the voltage source 10. Thus, in the case of the selected resistance value ratio of the voltage dividers 62, 64, 66 outlined above, the voltage V mos2 at / cross the resistor 66b is (significantly) higher than the reference voltage V ref at / cross the resistor 62b.

[0086] Because the MOSFETs 34a, 34b of the first MOSFET pair 34 change to an open switch state, the voltage drop across the voltage divider 64 changes. If the MOSFET 34a is open, the voltage drop across the MOSFET 34a is relatively high. In contrast, the voltage drop across the voltage divider 64 is only significantly lower than the voltage U1 of the voltage source or even at least almost 0 V. Thus, the voltage V mos1 across the resistor 64b is significantly lower than the reference voltage V ref across the resistor 62b and is, for example, at least almost 0 V. The comparator 70a receives the values of V mos1, V ref and the comparator 70b receives the values of V mos2, V ref as input values.

[0087] If the voltage of the control signal V phase1 rises to the high level again, the MOSFETs 34a, 34b are closed again and the voltage drop across the voltage divider 64 again assumes the value of the voltage U1 of the voltage source 10. The comparator 70a receives the values of V mos1, V ref and the comparator 70b receives the values of V mos2, V ref as input values.

[0088] After a certain time, the second control signal V phase2 is set to a voltage of approximately 0 V in the second time window Z2 for a time period Tlow2. This corresponds to a low level, also referred to as LOW level (digital 0). In this case, the voltage present between the gate and the source of the two MOSFETs 36a, 36b of the second MOSFET pair 36, if any, is only very low and below the threshold value of the MOSFETs 36a, 36b. The MOSFETs 36a, 36b thus change to an open state. During the same time period Tlow2 of the second time window Z2, the first control signal V phase1 remains at a high level. The MOSFETs 34a, 34b of the first MOSFET pair 34 thus remain closed. Because the MOSFETs 36a, 36b of the second MOSFET pair 36 are open in the second time period Tlow2 of the second time window Z2 and the MOSFETs 34a, 34b of the first MOSFET pair 34 are closed in the second time period Tlow2 of the second time window Z2, the voltage drop across the voltage divider 64, 66 changes. Because the MOSFETs 34a, 34b of the first MOSFET pair 34 remain closed, the voltage drop across the voltage divider 64 does not change, that is to say, the voltage drop across the voltage divider 64 still substantially corresponds to the reference voltage across the voltage divider 64 and thus to the voltage U1 of the voltage source 10. Thus, due to the above-described selection of the resistance value ratio of the voltage dividers 62, 64, 66, the voltage V mos1 at / cross the resistor 64b is (significantly) higher than the reference voltage V ref at / cross the resistor 62b.

[0089] Because the MOSFETs 36a, 36b of the second MOSFET pair 36 change to an open switch state, the voltage drop across the voltage divider 66 changes. If the MOSFET 36a is open, the voltage drop across the MOSFET 36a is relatively high. In contrast, the voltage drop across the voltage divider 66 is only significantly lower than the voltage U1 of the voltage source or even at least almost 0 V. Thus, the voltage V mos2 across the resistor 66b is significantly lower than the reference voltage V ref across the resistor 62b and is, for example, at least almost 0 V. The comparator 70a receives the values of V mos1, V ref and the comparator 70b receives the values of V mos2, V ref as input values.

[0090] If the voltage of the control signal V phase2 and the voltage of the output signal of the gate driver 60b rise again to the high level, the MOSFETs 36a, 36b are closed again and the voltage drop across the voltage divider 66 again assumes the value of the voltage U1 of the voltage source 10. Thus, due to the above-mentioned selection of the ratio of the resistance values of the voltage dividers 62, 64, 66, the voltage V mos2 at / across the resistor 66b is again (significantly) higher than the reference voltage V ref at / across the resistor 62b. The comparator 70a receives the values of V mos1, V ref and the comparator 70b receives the values of V mos2, V ref as input values.

[0091] Thus, as Figure 4a The curves of the voltages V mos1, V mos2 across the resistors 64b, 66b of the voltage dividers 64, 66 thus vary depending on the curves of the control signals V phase1, V phase2. The comparators 70a, 70b thus receive different input values depending on the curves of the voltages V ref, V mos1, V mos2. It can be seen from the curve of the voltage V mos2 that, starting from the sixth time window Z6, the switching of the second MOSFET pair 36 is faulty.

[0092] If both the MOSFETs 34a, 34b of the first MOSFET pair 34 and the MOSFETs 36a, 36b of the second MOSFET pair 36 are in the closed state, the values of the voltages V mos1, V mos2 are, as mentioned above, (significantly) higher than the value of the reference voltage V ref. The comparator 70a thus receives at its non-inverting input a value which is (significantly) higher than the value received at its inverting input as the voltage V ref as the voltage V mos1. The comparator 70a thus determines that the variable V mos1 is at least equal to, in fact greater than, the reference value V ref and outputs a high level (1 ) accordingly (see signal V comp1 ). Furthermore, the comparator 70b receives at its non-inverting input a value which is (significantly) higher than the value received at its inverting input as the voltage V ref as the voltage V mos2. The comparator 70b thus determines that the variable V mos2 is at least equal to, in fact greater than, the reference value V ref and thus outputs a high level (1 ) (see signal V comp2).

[0093] If the MOSFETs 34a, 34b are in open circuit state and the MOSFETs 36a, 36b are in closed state (see e.g. the time period Tlowl in the first time window Zl, Z2, Z4, Z5, Z6, Z8, Z9), a voltage of at least almost 0 V is obtained as the voltage V_mosl across the resistor 64b, and a maximum value of at least V_ref as the voltage V_mos2 across the resistor 66b. The first comparator 70a thus determines that the value of its input variable V_mosl is lower than the value of its other input variable V_ref (reference variable) and outputs accordingly a low level (digital 0) (see signal V_compl). Furthermore, the second comparator 70b determines that the value of its input variable V_mos2 is not lower than the value of its other input variable V_ref (reference variable) (as the value V_mos2 is (significantly) greater than the value of the reference variable V_ref) and outputs accordingly a high level (1) (see signal V_comp2).

[0094] If the MOSFETs 34a, 34b of the first MOSFET pair 34 are in closed state and the MOSFETs 36a, 36b of the second MOSFET pair 36 are in open circuit state (see e.g. the time period Tlow2 in the second time window Z2, the third time window Z3 and the fourth time window Z4), a voltage of at least almost 0 V is obtained as the voltage V_mos2 across the resistor 66b, and a maximum value (significantly) higher than the reference value V_ref as the voltage V_mosl across the resistor 64b. The first comparator 70a thus determines that the value of its input variable V_mosl is not lower than the value of its other input variable V_ref (reference variable) (as the value V_mosl is (significantly) greater than the value of the reference variable V_ref) and outputs accordingly a high level (digital 1) (see signal V_compl). Furthermore, the second comparator 70b determines that the value of its input variable V_mos2 is lower than the value of its other input variable V_ref (reference variable) and outputs accordingly a low level (0) (see signal V_comp2).

[0095] Thus, when the MOSFETs 34a, 34b of the first MOSFET pair 34 are open, a low level is obtained in the output signal V_compl of the first comparator 70a at the level of the low level of the first control signal V_phase1 over approximately the time of the time period Tlowl of the first time window Zl, the second time window Z2, the fourth time window Z4, the fifth time window Z5, the sixth time window Z6, the eighth time window Z8 and the ninth time window Z9, i.e. at the level of the low level of the first control signal V_phase1 over approximately the time

[0096] Then, in the first XOR gate 72a, the output signal V_comp1 of the first comparator 70a and the first control signal V_phase1 are compared with each other. This is done without a transition time delay. In the ideal case of switching delay and / or transition time delay, due to the ideal correspondence between signals V_comp1 and V_phase 1, XOR gate 72a will not determine any difference and will always output a low level (digital 0). In the real, non-ideal case, the first XOR gate 72a will output a double peak due to the transition time delay and / or switching delay as the output variable V_out1 of the first XOR gate 72a. Because MOSFETs 34a and 34b have reliably switched in each time period Tlow1, such a double peak appears in the region of each time period Tlow1.

[0097] If the second MOSFET is open-circuited with MOSFETs 36a and 36b of 36, then approximately at the time level of the low level of the second control signal V_phase2, the output signal V_comp2 of the first comparator 70b will be low. For example, if we assume that at least one of MOSFETs 36a and 36b, such as MOSFET 36a, is correctly switched (disconnected) in time windows Z2, Z3, and Z4 but not correctly switched (disconnected) in time windows Z6, Z7, and Z8, then therefore at approximately the time level of the low level of the second control signal V_phase2 in time windows Z2, Z3, and Z4, the output signal V_comp2 of the first comparator 70b will be low, while the level will remain high in time windows Z6, Z7, and Z8, because at least one of MOSFETs 36a and 36b, such as MOSFET 36a, is not properly disconnected.

[0098] Then, in the second XOR gate 72b, the output signal V_comp2 of the second comparator 70b and the second control signal V_phase2 are compared with each other. In the ideal case where there is no transition time delay and / or switching delay, due to the ideal correspondence between signals V_comp2 and V_phase2, the XOR gate 72b will not determine any difference and will always output a low level (digit 0). In the actual, non-ideal case, the double peaks that appear due to the transition time delay and / or switching delay are output as the output variable V_out2 of the second XOR gate 72b. Because MOSFETs 36a and 36b have reliably switched during the time period Tlow2 of the time windows Z2, Z3, and Z4, this double peak appears in the region of the time period Tlow2 of the time windows Z2, Z3, and Z4.

[0099] If we now assume, through examples, such as Figure 4aAs shown in the middle, in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8, the one of the MOSFETs 36a, 36b, e.g. the MOSFET 36a, is correctly turned off even though the second control signal V_phase2 does not assume a low level in the time period Tlow2, then the MOSFET 36a remains in the closed state in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8. As explained, in this case, a voltage (significantly) higher than the value of the reference voltage V_ref across the resistor 62b drops across the resistor 66b as the voltage V_mos2. Both comparators 70a, 70b thus determine that the voltage values V_mos1, V_mos2 at least correspond, in fact significantly higher than the reference voltage value V_ref during Tlow2 in the time windows Z6, Z7, Z8. The first comparator 70a thus determines that the value of its input variable V_mos1 is not lower than the value of its other input variable V_ref (reference variable) (because the value V_mos1 is (significantly) greater than the value of the reference variable V_ref) and thus outputs a high level (digital 1) (see signal V_comp1). Furthermore, the second comparator 70b determines that the value of its input variable V_mos2 is not lower than the value of its other input variable V_ref (reference variable) (because the value V_mos2 is (significantly) greater than the value of the reference variable V_ref) and accordingly outputs a high level (digital 1) (see signal V_comp2). Both comparators 70a, 70b thus output a high level for the signals V_comp1, V_comp2 also during the time period Tlow2 in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8. The XOR operation of the output of the second comparator 70b with the second control signal V_phase2 thus results in a (single) high level approximately during the time period Tlow2 of the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8 (V_out2) instead of a double peak.

[0100] The outputs of the first XOR gate 72a and the second XOR gate 72b are input as input variables to an OR gate 74. The output of the OR gate 74 is thus the superposition of the outputs of the first XOR gate 72a and the second XOR gate 72b. The output signal V_out3 of the OR gate 74 thus shows a double peak in the first time window Z1 to the fifth time window Z5, which represents the turn-off of the first and second MOSFET pairs 34, 36 during Tlow1 and Tlow2, and likewise a double peak in the sixth time window Z6, the eighth time window Z8 and the ninth time window Z9, which represents the turn-off of the first MOSFET pair 34 during Tlow1.

[0101] The or operation of the outputs of the two XOR gates 72a, 72b further leads to a (single) peak (at least approximately at the level of the time period Tlow2 in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8), respectively, in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8. This peak in the output signal (V_out3) of the or gate 74, which is not a double peak caused by a transition time delay and / or a switching delay, each of which has a smaller width, thus represents a fault in the opening of one of the MOSFETs 36a, 36b of the second MOSFET pair 36, for example the MOSFET 36a.

[0102] The recognition of the fault can be improved by connecting a time delay downstream of the or gate 74, in the following section referred to as time delay element 76. The result of the time delay is that only peaks having a duration that exceeds a predetermined time threshold are recognized as a fault. The duration of the double peaks in the first time window Z1 to the fifth time window Z5 (and likewise in the sixth time window Z6, the eighth time window Z8 and the ninth time window Z9) is below the time threshold, respectively. The output of the time delay element 76 thus outputs a low level (see signal V_fehler). In contrast, the peak in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8 has a duration of the time period Tlow2 that is above the time threshold. The time delay element 76 thus outputs a high level in the sixth time window Z6, the seventh time window Z7 and the eighth time window Z8, which lasts for a duration that corresponds at least approximately to the specific duration of the time period Tlow2 (see signal V_fehler).

[0103] Depending on the specific implementation of the time delay, the time delay element 76 can be configured to switch on a time delay or to cause a switching-on time delay. In this case, the time delay element 76 may, for example, implement a time delay switching-on or a switchable time delay. The time delay can be present at least for a duration that corresponds to one of the pulses of the double pulses of the signals Vout_1, Vout_2, Vout_3 (from the point of view of time) or can be higher than this duration. As a result, the individual pulses of these double pulses are suppressed or blanked and only the longer pulse (i.e. a pulse having a width that is greater than the time delay or greater than the width of each of the peaks of the double peak) is output, in each case shortened by the duration of the time delay in the fault signal V_fehler. This is illustrated in the following table: Figure 4bIt can be seen that an effective fault signal V_fehler is shown therein. In the signal V_fehler, the rising edge of the fault pulse is shifted or shortened by the magnitude of the turn-on delay, respectively, with respect to the rising edge of the long peak in the signal Vout_3 (i.e. the width of at least one of the double pulses / double peaks is shortened). In contrast, the falling edge of the pulse of the fault signal V_fehler falls simultaneously with the corresponding pulse in the signal Vout_3, since it is only the turn-on delay and not the turn-off delay. This applies to all time windows in which a fault is present, i.e. Z6, Z7 and Z8. In contrast, the pulses of each double pulse are suppressed by the turn-on delay. These are not actual / effective fault pulses in the end.

[0104] As a result, if a fault is present in the switching of one of the MOSFETs 34a, 34b, 36a, 36b, the output signal V_fehler of the time delay element 76 shows only a peak. In contrast, the transition time delay is suppressed. The output of the time delay 76 can therefore be referred to as a fault signal V_fehler. By means of a recognition circuit, the peak in the fault signal V_fehler can be automatically recognized. On the basis of the peak and the control signal, the recognition circuit can immediately conclude which of the two MOSFET pairs 34, 36 has not switched correctly. In the case of a fault in the MOSFET pair 36, it is not possible for the circuit shown to determine precisely whether the MOSFET 36a, the MOSFET 36b or both MOSFETs 36a, 36b have not switched correctly, but this is not necessary for the desired application. This is because, if at least one of the MOSFETs 34a, 34b or the MOSFETs 36a, 36b have not switched, the MOSFET pair 34, 36 in question is replaced as a whole. It is therefore not only possible to recognize a fault in time, but also to replace the faulty component or take other countermeasures to eliminate the fault in time.

[0105] Figure 3a , 4a and 4b can be summarized as follows. In Figure 3aIn the circuit, a total of four MOSFETs 34a, 34b, 36a, 36b, for example, are configured as power semiconductors, and more specifically, each of the two MOSFET pairs 34, 36 is connected in parallel. The MOSFET pairs 34, 36 are each formed by two antiparallel-connected MOSFETs 34a, 34b, 36a, 36b. The two power semiconductor pairs 34, 36 are alternately switched off and on by means of a logic. In order to be able to ensure that the connected load 40 is supplied with power, at least one power semiconductor pair 34, 36 must always be on. In each case, the voltage at this point (path voltage divider) is measured via a voltage divider 64, 66 at the common source terminal of each power semiconductor pair 34, 36. The circuit also has a further voltage divider 62 on the voltage source 10 side (reference voltage divider). When both MOSFET pairs 34, 36 are on (closed), a significantly greater voltage is measured at the resistor 64b of the voltage divider 64 (path voltage divider) and at the resistor 66b of the voltage divider 66 (path voltage divider) than at the resistor 62b of the reference voltage divider 62. As soon as one of the two MOSFET pairs 34, 36, more specifically at least one of the MOSFETs 34a, 34b, 36a, 36b of the MOSFET pairs 34, 36, is switched off, the voltage at the voltage dividers 64, 66 in question drops to a value of 0 V (or at least significantly below the voltage at the reference voltage divider 62). By means of two comparators 70a, 70b (comparison device), the output signals of the two path voltage dividers 64, 66 are compared with the voltage value at the reference voltage divider 62 and converted into digital signals by the comparators 70a, 70b. The signal shape of the outputs of the comparators 70a, 70b thus corresponds approximately to the signal sequence used to control the respective MOSFET pair 34, 36. By means of an exclusive OR operation (XOR operation 72a, 72b) of the control signals of the MOSFET pairs 34, 36 with the output signals of the respective comparator 70a, 70b, it is possible to detect whether the MOSFETs 34a, 34b, 36a, 36b of the MOSFET pairs 34, 36 are actually switched off. The two XOR operation signals of the two MOSFET pairs 34, 36 are then combined into one signal by means of an OR operation 74 and filtered by means of an on-delay 76. The on-delay 76 is advantageous for suppressing false diagnoses triggered by signal transition times and / or switching delays. A pulse sequence is obtained as a fault signal V_fehler, which corresponds approximately (albeit shortened) to the control pulses of the defective MOSFET pair 34, 36. The output signal V_fehler of the on-delay 76 can then be read in and processed by a higher-level controller (not shown, but see Figure 2 controller 28 in Fig. 1). Alternatively, the pulse sequence can be converted into a static value by means of a storage element (not shown).

[0106] The above summary applies accordingly Figure 3b a variant, wherein one of the semiconductor switches is replaced by a semiconductor diode 34c, 36c, respectively. In Figure 3b a variant, if a single semiconductor switch is not switched, the semiconductor pair is not switched. The semiconductor diodes 34c, 36c allow to precisely identify a fault in the switching of the semiconductor switches.

[0107] Although the description of the exemplary embodiments of Figures 2 to 4b refers to identifying whether the first semiconductor switch pair 34 and / or the second semiconductor switch pair 36 is correctly switched from a closed state to an open state, it is possible to identify from the signal curves accordingly whether the first semiconductor switch pair 34 and / or the second semiconductor switch pair 36 is correctly switched from an open state to a closed state.

[0108] The identification of the not switched semiconductor switch of the first semiconductor switch pair 34 and / or the second semiconductor switch pair 36 allows to use simple and inexpensive components and to omit the series connection of the other semiconductor switch, respectively, for redundancy purposes. Furthermore, due to the formation of pairs, the circuit is able to shut down bidirectionally, that is, on the input side and on the output side. The circuit further operates without multiple current measurements and thus has low losses and high efficiency. In order to achieve the required safety goals, the circuit also does not need multiple series-connected MOSFETs for management.

[0109] Although in the description of the exemplary embodiments of Figures 2 to 4b reference is always made only to the first semiconductor switch pair 34 and the second semiconductor switch pair 36, these exemplary embodiments and the present application are in general not limited to exactly two parallel-connected semiconductor switch pairs 34, 36. It is equally possible to provide three or more than three semiconductor switch pairs. Thus, in summary, there can be at least two semiconductor switch pairs 34, 36, and at least one not switched semiconductor switch pair can be identified from the at least two parallel-connected semiconductor switch pairs 34, 36.

[0110] The advantages with regard to at least one third semiconductor switch pair being connected in parallel to the first semiconductor switch pair 34 and the second semiconductor switch pair 36 will now be described with reference to Figures 3a to 4b Figures 3a to 4b but the at least one third semiconductor switch pair is not shown in the figures.

[0111] As described above, in the first time window Z1, the first semiconductor switch pair 34 is open when the first control signal V_phase1 assumes a low level in the time period Tlow1. After the time period Tlow1 has elapsed, the first control signal V_phase1 assumes a high level again. In this case, the first semiconductor switch pair 34 will close again. However, if at least one of the semiconductors 34a, 34b of the first semiconductor switch pair 34 is defective, this at least one of the semiconductors 34a, 34b of the first semiconductor switch pair 34 remains open, that is, does not close again even though the first control signal V_phase1 has assumed a high level again. As described, the second semiconductor switch pair 36 will be open in the second time window Z2 during the time period Tlow2 because the second control signal assumes a low level during the time period Tlow2. Thus, during the time period Tlow2, the first semiconductor switch pair 34 is open (because at least one of the semiconductors 34a, 34b does not close again even though it should actually close) and the second semiconductor switch pair 36 is open (due to the low level of the second control signal V_phase2). Thus, during the time period Tlow2 (short) in the time window Z2, the load is completely disconnected from the power supply.

[0112] In contrast, if at least one third semiconductor switch pair is connected in parallel, this third semiconductor switch pair, if switched correctly, can allow an emergency operation. This is because the at least one third semiconductor switch pair will be in a closed state during the time period Tlow2 with the help of at least one third control signal, which assumes a high level during the time period Tlow2. Thus, the load is not disconnected from the system and the current source and thus not switched off.

Claims

1. A system for identifying a non-switched semiconductor switch, wherein, The system has: a first semiconductor switch controllable by means of a first control signal, and a first semiconductor device configured and arranged to prevent a current flow through the first semiconductor device in at least one direction; a second semiconductor switch controllable by means of a second control signal and connected in parallel with the first semiconductor switch, and a second semiconductor device configured and arranged to prevent a current flow through the second semiconductor device in at least one direction; a first resistor, wherein one end of the first resistor is connected between the first semiconductor switch and the first semiconductor device, and the other end of the first resistor is connected to a reference potential; a second resistor, wherein one end of the second resistor is connected between the second semiconductor switch and the second semiconductor device, and the other end of the second resistor is connected to the reference potential; and a determining unit configured to identify whether the first semiconductor switch is not switched based on a curve of a first voltage drop across the first resistor, and configured to identify whether the second semiconductor switch is not switched based on a curve of a second voltage drop across the second resistor, wherein the determining unit has: a first comparison component configured to determine a first comparison curve by comparing the curve of the first voltage drop with a curve of a reference voltage dropped across a reference resistor; and a second comparison component configured to determine a second comparison curve by comparing the curve of the second voltage drop with the curve of the reference voltage dropped across the reference resistor, wherein the determining unit has: a first logic component, wherein the first logic component is configured to determine a first logic signal by combining the first comparison curve with the first control signal; and / or a second logic component, wherein the second logic component is configured to determine a second logic signal by combining the second comparison curve with the second control signal.

2. The system of claim 1, wherein the first semiconductor device is configured as a first semiconductor diode, and the first semiconductor diode is arranged to form a path with the first resistor when the first semiconductor switch is in an open state, and the first semiconductor diode is configured to prevent a current flow through the path formed when the first semiconductor switch is in an open state; and / or the second semiconductor device is configured as a second semiconductor diode, and the second semiconductor diode is arranged to form a path with the second resistor when the second semiconductor switch is in an open state, and the second semiconductor diode is configured to prevent a current flow through the path formed when the second semiconductor switch is in an open state.

3. The system of claim 1, wherein the first semiconductor device is configured as a semiconductor switch connected anti-serial with the first semiconductor switch; and / or the second semiconductor device is configured as a semiconductor switch connected anti-serial with the second semiconductor switch. The system has:

4. The system of any one of claims 1 to 3, wherein, ​ a first voltage divider circuit having the first resistor and at least one additional resistor, wherein one end of the first voltage divider circuit is connected between the first semiconductor switch and the first semiconductor device, and the other end of the first voltage divider circuit is connected to the reference potential; and / or a second voltage divider circuit having a second resistor and at least one additional resistor, wherein one end of the second voltage divider circuit is connected between the second semiconductor switch and the second semiconductor device, and the other end of the second voltage divider circuit is connected to the reference potential.

5. The system of claim 1, wherein, The system has a reference voltage divider having the reference resistor and at least one additional resistor.

6. The system of claim 1, wherein, The determining unit has a third logic component, wherein the third logic component is configured to determine an output signal by combining the first logic signal with the second logic signal.

7. The system of any one of claims 1 to 3 or 5 to 6, wherein, The system further has a delay element configured to determine a fault signal by applying an on-delay.

8. A method for identifying a non-switched semiconductor switch, wherein, The method comprises: controlling a first semiconductor switch by means of a first control signal; controlling a second semiconductor switch connected in parallel with the first semiconductor switch by means of a second control signal; identifying whether the first semiconductor switch is not switched based on a curve of a first voltage drop across a first resistor, wherein one end of the first resistor is connected between the first semiconductor switch and a first semiconductor device, and the other end of the first resistor is connected to a reference potential, wherein the first semiconductor device is configured and arranged to prevent a current from flowing through the first semiconductor device in at least one direction; identifying whether the second semiconductor switch is not switched based on a curve of a second voltage drop across a second resistor, wherein one end of the second resistor is connected between the second semiconductor switch and a second semiconductor device, and the other end of the second resistor is connected to the reference potential, wherein the second semiconductor device is configured and arranged to prevent a current from flowing through the second semiconductor device in at least one direction; determining a first comparison curve by comparing the curve of the first voltage drop with a curve of a reference voltage falling across a reference resistor; determining a second comparison curve by comparing the curve of the second voltage drop with the curve of the reference voltage falling across the reference resistor; determining a first logic signal by combining the first comparison curve with the first control signal; and / or determining a second logic signal by combining the second comparison curve with the second control signal.

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