Voltage adjustment based on pending refresh operations

Abstract

This application relates to voltage adjustment based on pending refresh operations. A memory device may periodically perform refresh operations to refresh volatile memory cells and may sometimes postpone the execution of one or more refresh operations. The memory device may determine the number of pending (e.g., postponed) refresh operations, for example, by determining the number of refresh intervals that have elapsed without a refresh command being received or executed, and other methods. The memory device may pre-adjust (or cause to adjust) the supply voltage associated with the memory device or memory device components based on the number of pending refresh operations to prepare for the current demand associated with performing the one or more pending refresh operations. For example, the memory device may increase the supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

Description

[0001] Cross-referencing

[0002] This patent application is a national application of International Patent Application No. PCT / US21 / 16176, filed February 2, 2021, entitled "Voltage Adjustment Based on Pending Refresh Operations," filed by Hollis et al., which claims U.S. Patent Application No. 17 / 164,738, filed February 1, 2021, entitled "Voltage Adjustment Based on Pending Refresh Operations," and Hollis et al., filed February 5, 2020, entitled "Voltage Adjustment Based on Pending Refresh Operations." The assignee hereof priority of U.S. Provisional Patent Application No. 62 / 970,676, entitled “OPERATIONS”, and each of the U.S. Patent Application and the Provisional Patent Application is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to voltage regulation based on pending refresh operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Even without power, non-volatile memory such as FeRAM can maintain its stored logic state for a long time. For example, volatile memory devices such as DRAM may lose their stored state when disconnected from power. Summary of the Invention

[0006] A method is described. The method may include identifying a number of refresh intervals associated with memory cells of a refresh memory device; identifying a number of received refresh commands; determining a number of refresh operations by determining the difference between the number of refresh intervals and the number of received refresh commands; and adjusting a supply voltage associated with the memory device over a duration based at least in part on the number of refresh operations.

[0007] An apparatus is described. The apparatus may include a memory array and a power management component coupled to the memory array for providing a supply voltage to the memory array. The apparatus may be configured to count the number of refresh intervals associated with memory cells of the refresh memory device.

[0008] A method is described. The method may include determining the number of pending refresh operations via a memory device; adjusting a supply voltage associated with the memory device before performing at least some of the pending refresh operations and based at least in part on the number of pending refresh operations; and performing at least some of the pending refresh operations based at least in part on the adjustment of the supply voltage associated with the memory device. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports voltage adjustment based on pending refresh operations, as illustrated in the examples disclosed herein.

[0010] Figure 2 Examples of memory systems supporting voltage adjustment based on pending refresh operations, as disclosed herein, are presented.

[0011] Figure 3 Examples of refresh timing that support voltage adjustment based on pending refresh operations are shown, as disclosed in this document.

[0012] Figure 4A and 4BExamples of voltage adjustment based on pending refresh operations are shown, as disclosed in this document.

[0013] Figure 5 A block diagram is shown illustrating a device that supports voltage adjustment based on pending refresh operations, as illustrated in the examples disclosed herein.

[0014] Figure 6 and 7 The flowchart illustrates one or more methods supporting voltage adjustment based on pending refresh operations, as illustrated in the examples disclosed herein. Detailed Implementation

[0015] Some volatile memory cells may need to be refreshed (e.g., periodically refreshed) to maintain their state during operation. Such memory cells can be refreshed by reading and restoring the state of the memory cell (e.g., restoring it to a first stored level) to mitigate potential loss of state information due to, for example, charge leakage. The first stored level may be an instance of a voltage different from the voltage when the memory array is subsequently powered on or the level of a first value written to the memory cell. In such cases, the first stored level may be an instance of an initially stored level, a desired level, or an expected level. For example, a DRAM cell may contain a capacitor for storing the state of the memory cell, and such memory cells may need to be refreshed to compensate for charge leakage from the capacitor over time. The memory device may therefore retain certain time periods, sometimes referred to as refresh intervals, for performing one or more refresh operations. One or more refresh operations may be performed during the refresh interval in response to receiving a refresh command from, for example, a controller or host device.

[0016] In some cases, some or all of the memory array may be unavailable for one or more other memory access operations (e.g., one or more read operations or one or more write operations), for example, when the memory array is performing a refresh operation. This lack of availability can increase the latency associated with performing one or more operations, such as memory access operations, which may be undesirable for some latency-sensitive operations. To address this issue, some memory devices allow the host device to postpone one or more refresh operations by delaying the sending of one or more refresh commands until a convenient time. In this case, one or more refresh intervals may elapse if the memory device does not receive a refresh command and performs a refresh operation. However, postponed refresh commands can lead to an accumulation of pending refresh operations until the memory device receives the refresh command and can perform the corresponding refresh operation. In some cases, the memory device may receive multiple consecutive refresh commands, which allows the memory device to "supplement" the postponed refresh operations and ensure that the maximum duration between refresh operations is not exceeded. In this case, the memory device may perform multiple refresh operations within a relatively short time period, for example, by performing multiple refresh operations during a single refresh interval.

[0017] In some instances, the memory device may include or be coupled to a power management component, such as a power management integrated circuit (PMIC), which can be used to manage the power supplied to the memory device by controlling the voltages of one or more power rails. The power rails may be part of a power delivery network that provides various supply voltages to the memory device for its operation; and each may be associated with a nominal supply voltage that can be specified for the memory device. Each refresh operation may draw a relatively large current from one or more power rails. Therefore, performing multiple supplementary refresh operations (as may sometimes occur) over a relatively short period can strain the power delivery network of the memory device and can cause the voltages of the power rails to drop (e.g., decrease, diminish) below the nominal supply voltage. In some cases, such voltage drops can be sufficient to cause performance degradation or memory errors in the memory device.

[0018] In some instances, a memory device can determine (e.g., predict) this increased demand for power (e.g., current or voltage) from a power delivery network by determining the number of pending (e.g., deferred) refresh operations and other parameters or conditions. The memory device can indicate a target voltage for the power rail to the power management components based on the number of pending refresh operations. In some cases, a registered clock driver (RCD) can indicate a target voltage for the power rail to the power management components based on the number of pending refresh operations. The target voltage may differ from the nominal supply voltage. For example, if the memory device determines that multiple pending refresh operations exist, it can request a target voltage higher than the nominal supply voltage for the power rail to prepare in advance for performing multiple refresh operations in a "supplementary" scenario.

[0019] The memory device can determine the number of pending refresh operations by, for example, identifying (e.g., counting or otherwise determining) the number of refresh intervals that have elapsed without a refresh command being received, identifying (e.g., counting or otherwise determining) the number of refresh commands received, and determining (e.g., calculating) the difference between the two numbers.

[0020] Subsequently, the power management components can adjust (e.g., temporarily) the voltage of the power rails based on the target voltage indicated by the memory device, which may compensate for the increased demand on the power delivery network during supplemental refresh operations.

[0021] The following text is for reference only. Figure 1 The features of this disclosure are further described in the context of memory systems and dies. Reference is then made to... Figure 2 Features of this disclosure are described in the context of system and voltage signals, up to section 4. These and other features of this disclosure are further explained by the voltage adjustment involved in pending refresh operations. Figures 5 to 7 The equipment diagrams and flowcharts are described in the document and can be referenced in the descriptions.

[0022] Figure 1 This describes an example of a system 100 utilizing one or more memory devices, as disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include components of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system used to store data for one or more other components of system 100.

[0024] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or some other stationary or portable electronic device, and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0025] Memory device 110 may be a separate device or component that can provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 can be used to store data for components of host device 105. In some instances, memory device 110 can act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] The host device 105 may include one or more of the following components: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or, for example, one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0028] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0029] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 containing two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0031] Some memory arrays 170 may be or may contain arrays of volatile memory cells, such as DRAM memory cells. Some volatile memory cells may lose their state over time and may be periodically refreshed (e.g., read and restore) to maintain their state. In some cases, volatile memory cells may be characterized by a frequency term that may require refreshing to maintain their state, said frequency term may be referred to as refresh interval. The memory die 170 may periodically perform refresh operations on one or more rows of memory cells in the memory array 170 to maintain the state of the memory cells.

[0032] The memory die 160 may include a logic circuitry configured to periodically perform such refresh operations on the memory cells by reading and restoring (e.g., activating a sensing component to amplify the voltage on the memory cell back to the initially written voltage level) the state of the memory cells. In some cases, this logic circuitry may be part of the local memory controller 165 or may be a separate circuitry. In some cases, the memory die 160 may perform refresh operations on one or more rows of memory cells in the memory array 170 in response to receiving a refresh command from an external host device or based on internal timing that specifies the frequency of refreshable memory cells.

[0033] In some cases, memory die 160 may refresh one or more rows of memory array 170 in response to receiving a refresh command from an external device (e.g., a host device), which may be referred to as performing an automatic refresh operation. The external device may transmit the refresh command to the memory die based on, for example, timing information maintained at the external device.

[0034] In some cases, memory die 160 may refresh one or more rows of memory array 170 based on a refresh command received from the memory die's controller, the refresh command being based on internal (e.g., on-die) timing indicating the amount of time elapsed since the last read or refresh of a memory cell row. Such a refresh may be referred to as performing a self-refresh operation.

[0035] In some cases, performing a refresh operation on a row of memory cells in a memory array may involve performing a read and restore procedure, including performing an activation (Act) operation on the row to activate it and causing the memory cells to be read and restored (e.g., via a sense amplifier), and then performing a precharge (Pre) operation on the digital line to prepare it for the next access operation and returning the digital line to a precharged state for the next row activation. This type of sequence can be called an Act / Pre sequence.

[0036] In some cases, an activation operation can activate (e.g., assert) a word line associated with a row of memory cells, thereby selecting a memory cell coupled to that word line. The selected memory cell can share charge with the corresponding digital line, thus changing the voltage on the digital line based on the logic state stored in the memory cell. A sense amplifier coupled to the digital line can drive the digital line to one of two values ​​based on the voltage on the digital line, thereby restoring the memory cell to a full charge associated with the logic state (e.g., refresh). A precharge operation can bias the digital line to a precharge voltage to prepare the digital line for subsequent access operations.

[0037] During the Act / Pre sequence, some or all of the memory array 170 may be unavailable for other memory accesses, which can introduce latency into memory access operations. In some cases, one or more refresh commands can be postponed to enable continuous memory access to memory device 110. The postponed refresh operations can then be "compensated" during one or more subsequent refresh intervals. (See reference...) Figure 3 Additional details regarding the timing of the refresh operation are described in more detail.

[0038] In some instances, the memory die 160 may be coupled to a power management component that can be used to provide one or more supply voltages to the memory die 160. For example, the power management component may use power rails (e.g., conductive lines) to supply VDD voltage, VSS voltage, VDDQ voltage, etc. The power management component can be used to maintain a substantially constant supply voltage on the rails to provide power to the memory device 110 or the memory die 160 during operation. The power management component may include or be coupled to one or more voltage source components that can be used to generate an appropriate supply voltage. In some cases, the power management component may be referred to as a PMIC.

[0039] In some cases, the power management component may be used to receive an indication of a target voltage for a power rail from memory device 110 or memory die 160, and may adjust the supply voltage on said rail based on the indicated target voltage. The supply voltage may be adjusted for a limited duration (e.g., temporarily). Memory device 110 or memory die 160 may determine the target voltage based on, for example, the number of pending (e.g., deferred) refresh operations. Memory die 160 (or memory device 110) may include pins for providing a signal indicating the target voltage to the power management component, thereby enabling the power management component to adjust the supply voltage appropriately.

[0040] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are used to receive, transmit, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160. In some instances, the device memory controller 155 may include an RCD. The RCD may include registers for buffering memory control signals or commands.

[0041] A local memory controller 165 (e.g., local to memory die 160) can be used to control the operation of memory die 160. In some instances, the local memory controller 165 can be used to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 capable of performing the various functions described herein. Thus, the local memory controller 165 can be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signals, an encoder for encoding or modulating the signals to be transmitted, or various other circuitry or controllers operable to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

[0042] In some instances, the device memory controller 155 or the local memory controller 165 of the memory die 160 can be used to determine the number of pending refresh operations. The memory device 110 can be used to adjust the supply voltage associated with the memory device based on the number of pending refresh operations.

[0043] External memory controller 120 can be used to enable the communication of one or more of the following between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, or other components of system 100 or host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, external memory controller 120, or the functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0044] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may contain one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0045] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling may be conveyed via channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0046] Figure 2 This describes an example of a memory system 200 that supports voltage adjustment based on pending refresh operations. The memory system 200 may include a power management component 205, a memory device 210 including a memory array 215, and a signal path 230 and a supply path 225 between the power management component 205 and the memory device 210. In the example of the memory system 200, the signal path 230 and / or the supply path 225 may be examples of conductive lines coupling the power management component 205 to the memory device 210. The memory device 210 may be as described in reference... Figure 1 The described memory device 110 is an example, and may also include, for example, a device memory controller, RCD, and / or other components of the memory device 110. The memory array 215 may be a reference. Figure 1 An example of the described memory array 170.

[0047] The power management component 205 may include a supply interface 235, low dropout regulators (LDOs) 240, 245, power supplies (SWA, SWB) 250, 255 (e.g., switching regulators), and a multiple programmable memory (MTP) 260. The supply interface 235 can be used to receive power used to activate the power management component 205 and to be allocated by the power management component 205 to other components of the memory system (e.g., memory device 210).

[0048] Low-dropout regulators 240 and 245 can be used to output power (e.g., DC power) to a memory device in a memory system, including memory device 210. In some cases, low-dropout regulators 240 and 245 can be used to regulate an output voltage, such as a supply voltage. Power supplies 250 and 255 can be used to output power to a memory device in a memory system, including memory device 210. Power management component 205 may include any number of low-dropout regulators (e.g., one, two, three, four, five, six, seven, or eight), or any number of power supplies (e.g., one, two, three, four, five, six, seven, or eight), or any number of both.

[0049] The multiple programmable memory 260 can be any type of memory used by the power management component 205 to perform the functions described herein. In some cases, the multiple programmable memory 260 can be an example of electrically erasable programmable read-only memory (EEPROM) or other types of memory technology. The multiple programmable memory 260 can be used for protection circuitry, improving the reliability of power-on or power-off sequences, setting output voltage, setting output pull-down resistors, or other functions, or any combination thereof.

[0050] Supply path 225 may be a power rail (or may be coupled to a power rail) to enable, for example, the power management component 205 to provide a supply voltage to memory device 210. The supply voltage may be used by memory device 210 during operation of memory device 210 and may include, for example, VDD voltage, VSS voltage, or another supply voltage.

[0051] In some cases, the power management component 205 may be coupled to a sensing line (e.g., an analog sensing line) that provides feedback to the power management component 205 regarding the voltage of the power rail (e.g., the voltage of supply path 225). Such an analog sensing line can be used by the power management component 205 to attempt to maintain a nominal voltage on the power rail, such as maintaining VDD, VSS, or another voltage. The power management component 205 can compare the voltage of the sensing line with a reference voltage and can adjust the supply voltage based on the comparison.

[0052] The memory device 210 can be used to determine the number of pending refresh operations and, based on the number of pending refresh operations, to provide a target voltage for the power rail to the power management component 205. The target voltage may be different from or the same as the nominal supply voltage, depending on the number of pending refresh operations.

[0053] To determine the number of pending refresh operations, memory device 210 may include one or more counters 265 to count the number of pending refresh operations, the number of elapsed refresh intervals, the number of received refresh commands, or combinations thereof. In some instances, memory device 210 may include an oscillator tuned to the refresh interval time (which may be referred to as tREFI), and counter 265 may increment each time a refresh interval elapses without a received refresh command. In some cases, identifying the number of refresh intervals includes incrementing a refresh interval counter for each elapsed refresh interval, and identifying the number of refresh commands includes decrementing the refresh interval counter for each received refresh command. In some instances, counter 265 may be located on a device memory controller, RCD, or DRAM of memory device 210. In some instances, power management component 205 may include an RCD. In this case, counter 265 may be directly coupled to power management component 205.

[0054] In some cases, memory device 210 may be used to provide (e.g., transmit) a signal indicating a target voltage to power management component 205 so that power management component 205 adjusts the voltage of the power rail to a voltage different from the nominal supply voltage. This signal may be an analog or digital signal. When memory device 210 performs one or more supplemental refresh operations, the voltage adjustment may be performed for an extended period of time while receiving the signal indicating the target voltage from power management component 205.

[0055] For example, memory device 210 may transmit (e.g., generate, drive, provide) analog signals that adjust the voltage of the analog sensing line based on a determined number of pending refresh operations in order to indirectly provide a target voltage to power management component 205. For example, memory device 210 may decrease the voltage on the analog sensing line so that power management component 205 increases the supply voltage on the power rail, and vice versa. That is, memory device 210 may be configured to manipulate feedback received by power management component 205 on the sensing line to control the supply voltage provided by power management component 205.

[0056] As previously discussed, power management component 205 can compare the voltage of the sensing line with a reference voltage and adjust the supply voltage based on the comparison. In some instances, memory device 210 can transmit a signal that manipulates the reference voltage instead of the sensing line voltage to cause power management component 205 to adjust the supply voltage on the power rail. Signal path 230 can be coupled to a reference line providing the reference voltage, and memory device 210 can adjust the reference voltage by transmitting analog or digital signals on signal path 230.

[0057] If counter 265 is directly coupled to the power management component (e.g., if the RCD resides in the power management component 205), then the signal may include the output of counter 265, which the power management component 205 may then use to determine how to adjust the supply voltage.

[0058] Feedback signals transmitted from memory device 210 to power management component 205 can be generated by various components of memory device 210, such as memory array, device memory controller, RCD, or another component (e.g., originating from said component). For example, RCD can transmit feedback signals to power management component 205.

[0059] In some cases, memory device 210 may include pin 220 for providing a signal indicating a target voltage to power management component 205. Signal path 230 may couple pin 220 of memory device 210 to power management component 205, for example, to a sensing line, a reference line, or to another input of power management component 205. In some instances, memory device 210 may provide a digital or analog signal indicating a target voltage to power management component 205.

[0060] A pin can be, for example, a conductive terminal of an integrated circuit package that allows the integrated circuit to be connected to other components or circuit systems. Pin 220 may also be referred to as, for example, a pad, socket, connector, contact, or ball (of a ball grid array). In some cases, pin 220 may be a conductive point located inside or outside the integrated circuit package. In some cases, pin 220 may be associated with predefined functionality (e.g., a predefined type or format of a signal), which may be specified as, for example, a portion of a standardized interface that allows the integrated circuit to be connected to other circuit systems or components.

[0061] Signal path 230 may comprise any set of one or more lines that establish a communication link between memory device 210 and power management component 205. Signal path 230 may be directly coupled between memory device 210 and power management component 205, meaning that signal path 230 can establish a connection between the two components, which allows for the routing of signals between the components using conductive lines.

[0062] Memory system 200 or memory device 210 may refer to a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or another type of module or assembly. In some cases, the SIMM or DIMM may include a power management component (e.g., as depicted in memory system 200). In some cases, the power management component 205 may be located external to the SIMM or DIMM.

[0063] In some cases, memory system 200 may include a single DRAM integrated circuit (e.g., a single memory device 210). Memory system 200 including a single DRAM integrated circuit may include a first number of pins (e.g., 72 pins or another number of pins) which may be used, for example, to couple memory system 200 to power management components, a host processor, or other electronic components. In this case, each pin of memory system 200 may support 32-bit data transfer.

[0064] In some cases, memory system 200 may include a series of DRAM integrated circuits, such as a series of memory devices 210. Memory system 200 including a series of DRAM integrated circuits may include a second number of pins (e.g., 100, 144, 168, 172, 184, 204, 214, 240, or another number of pins) which may be used, for example, to couple memory system 200 to power management components, a host processor, or other electronic components. In this case, each pin of memory system 200 may support 64-bit data transfer.

[0065] In some cases, the aforementioned number of pins for the memory system 200 may include pins for providing feedback to the power management components. In some cases, additional pins may be added to the memory system 200 to provide this functionality, and thus the number of pins may increase by one relative to the aforementioned number of pins for the memory system 200.

[0066] This document provides techniques for a memory device 210 to provide signals to a power management component 205 so that the power management component 205 can pre-adjust a supply voltage in preparation for performing one or more supplementary refresh operations, such as previously postponed refresh operations. The supply voltage can be adjusted over a period extending until the memory device 210 performs one or more supplementary refresh operations. For example, the memory device 210 may determine the number of postponed refresh operations. The memory device 210 may determine a target voltage for the supply voltage based on the number of pending refresh operations. The memory device 210 may send a signal indicating the target voltage (e.g., using signal path 230) to the power management component 205. In some instances, an RCD may send a signal indicating the target voltage (e.g., using signal path 230) to the power management component 205. The signal may be received by the power management component 205 (and / or by another device, such as a host device) and may be used by the power management component 205 to regulate (e.g., maintain or adjust) the supply voltage or another operational aspect of the memory device 210.

[0067] Figure 3 This describes an instance of a refresh timeline 300 that supports voltage adjustments based on pending refresh operations. The refresh timeline 300 depicts two durations: the refresh interval 305 (tREFI) and the refresh cycle interval 310 (tRFC).

[0068] The refresh interval 305 may be a duration reserved (e.g., allocated) by the memory device for performing one or more refresh operations in response to receiving one or more refresh commands. The duration of the refresh interval may vary for different memory devices. For example, the refresh interval 305 may be 7.8 μs for some memory devices, and may be a different duration for others. In some cases, the refresh interval 305 may be specified as a processor cycle, such as the number of processor cycles of the host device or controller.

[0069] The refresh cycle interval 310 can be the duration during which the memory device uses or allocates resources to the memory device to perform a refresh operation. For example, the refresh cycle interval 310 can be the same as or shorter than the refresh interval 305. That is, the duration of a single refresh interval 305 can encompass the duration of one or more refresh cycles 310. For example, the refresh cycle 310 can be initiated in response to receiving a refresh command.

[0070] Some memory devices can specify that refresh operations may (or should) be issued to the memory device at each refresh interval 305. Some memory devices can allow the memory controller to postpone issuing one or more refresh commands to a later refresh interval 305. For example, a memory device can specify that eight refresh commands may (or should) be issued over a duration of 8×tREFI (or based on some other timing criterion) to meet a specified refresh frequency. This allows the memory controller to have flexibility in scheduling refresh operations to provide better overall performance of the memory device.

[0071] In the example of refresh timeline 300, nine refresh intervals 305 may pass between time t1 and time t2 if the memory device has not received a refresh command. After time t2, for example, eight pending refresh operations may exist.

[0072] At or before time t3, the memory device may receive eight refresh commands (e.g., corresponding to eight deferred refresh commands) and may perform eight corresponding refresh operations during the refresh interval 305 between time t3 and time t4. That is, the memory device may perform eight “supplementary” refresh operations within the refresh interval 305 between time t3 and time t4, each of which may be performed during the corresponding refresh cycle interval 310. Such closely spaced refresh operations can place high demands on the power delivery network by drawing relatively large currents, potentially causing a drop in the supply voltage.

[0073] To counteract this effect, the memory device can identify the number of refresh intervals 305 that have elapsed without a refresh command being received (in this example, nine refresh intervals) and determine the number of pending refresh operations.

[0074] The memory device can transmit a signal indicating a target voltage for the power rail used in the power delivery network to the power management component, where the target voltage is based on the number of pending refresh operations. That is, the memory device can track pending refresh operations and pre-request a higher supply voltage to prepare for supplementary execution of pending refresh operations. The power management component can receive the signal indicating the target voltage and can adjust the supply voltage based on the received target voltage. For example, the power management component can adjust the supply voltage to match (e.g., meet or approach) the target voltage.

[0075] Examples of the target voltage that can be transmitted from the memory device to the power management component and the resulting supply voltage that can be provided by the power management component in response are respectively in Figure 4A and 4B Described in the text.

[0076] Figure 4AAn example of a target voltage 405 indicated in a signal that supports voltage adjustment based on pending refresh operations is described. The target voltage 405 may be a target for the supply voltage, such as the voltage supplied by a power management component on a power rail. A memory device (e.g., memory devices 110, 210) may transmit a signal indicating the target voltage 405 to a power management component (e.g., power management component 205) so that the power management component can adjust the supply voltage based on the target voltage.

[0077] In some instances, the memory device may transmit a signal indicating a target voltage continuously or nearly continuously, and the value of the target voltage may be dynamically updated based on the number of pending refresh operations in progress. In some instances, the memory device may transmit the signal indicating the target voltage intermittently, for example, periodically or when the memory device changes the target voltage, or based on a combination of these or other factors. The memory device may avoid transmitting the signal at other times.

[0078] exist Figure 4A In some instances, the memory device may increase the target voltage whenever it determines that the number of pending refresh operations has increased, for example, whenever the memory device determines that a refresh interval has elapsed without receiving a refresh command. The memory device may increase the target voltage incrementally (e.g., by the same amount each time), or it may increase the target voltage in some other manner. In some instances, the memory device may increase the target voltage until it reaches a maximum target voltage, and may refrain from further increasing the target voltage in response to determining that the number of pending refresh operations has increased further.

[0079] although Figure 4A Not shown in the figure, but whenever the memory device determines that the number of pending refresh operations has decreased, for example whenever the memory device receives a refresh command, the memory device may also reduce the target voltage until the number of pending refresh operations reaches zero.

[0080] exist Figure 4A In this context, voltage V1 may correspond to the nominal supply voltage associated with the memory device, such as VDD voltage, VDDQ, VSS, or other fixed supply voltage. Before time t0, the memory device may determine that there are no pending refresh intervals and may therefore set the target voltage to voltage V1.

[0081] At time t0, the memory device can determine that a first refresh interval (e.g., refresh interval 305) has elapsed without the memory device receiving a refresh command. That is, the memory device can determine that there is a (1) pending refresh operation. In response to determining that there is a pending refresh operation, the memory device can increase the target voltage 405 from V1 to V2.

[0082] At time t1, the memory device can determine that the second refresh interval has elapsed without the memory device receiving a refresh command, and can therefore determine that there are now two (2) pending refresh operations. In response to determining that there are two pending refresh operations, the memory device can increase the target voltage 405 from V2 to V3.

[0083] At time t2, the memory device can determine that the third refresh interval has elapsed without the memory device receiving a refresh command, and can therefore determine that there are now three (3) pending refresh operations. In response to determining that there are three pending refresh operations, the memory device can increase the target voltage 405 from V3 to V4.

[0084] At time t3, the memory device may receive one or more refresh commands, which may correspond to pending refresh operations. The memory device may increase the number of received refresh commands based on the receipt of one or more refresh commands, and may adjust the number of pending refresh operations based on the increase in the number of received refresh commands. The memory device may begin executing at least some of the pending refresh operations in response to receiving a refresh command and may reduce the target voltage from V4 to V0. In some cases, the memory device may execute at least some of the pending refresh operations based on adjusting the supply voltage, for example, after adjusting the supply voltage.

[0085] In some cases, V0 can be a voltage lower than the nominal supply voltage, which can reduce or eliminate subsequent overshoot of the supply voltage provided by the power management components when they attempt to adjust the supply voltage back to the nominal supply voltage V1. In other cases, V0 can be equivalent to voltage V1.

[0086] At time t4, the memory device can determine that there are no pending refresh operations and can increase the target voltage from V0 to V1, assuming that V0 and V1 are different voltages.

[0087] Figure 4B This describes an example of a supply voltage 410 that supports voltage adjustment based on pending refresh operations. The supply voltage 410 can be adjusted in response to receiving an instruction. Figure 4A The target voltage signal shown is the voltage supplied by the power management component. That is, Figure 4A It can depict the target voltage generated by the memory device and transmitted to the power management components, and Figure 4B It can depict the corresponding response of the power management components.

[0088] Before time t0, the power management components can provide a supply voltage of V5, which can be the nominal supply voltage for the memory device. For example, voltage V5 can be close to or equal to voltage V1.

[0089] At time t0 (or shortly thereafter), the power management component may receive a signal from the memory device indicating the target voltage of V2, and may begin to increase the supply voltage toward V2 in response to receiving the signal.

[0090] At time t1 (or shortly thereafter), the power management component may receive a signal from the memory device indicating the target voltage of V3, and may begin to increase the supply voltage toward V3 in response to receiving the signal.

[0091] At time t2 (or shortly thereafter), the power management component may receive a signal from the memory device indicating a target voltage for V4, and may begin to increase the supply voltage toward V4 in response to receiving the signal. The supply voltage may reach voltage V6, which may be close to or equal to voltage V4.

[0092] At time t3 (or shortly thereafter), the power management component may receive a signal from the memory device indicating a target voltage for V0, and may begin to decrease the supply voltage toward V0 in response to receiving the signal. Therefore, the power management component may readjust the supply voltage based on the target voltage for V0, which in turn may be adjusted based on the amount of the received refresh command.

[0093] At time t4 (or shortly thereafter), the power management component may receive a signal from the memory device indicating a target voltage V1, and may begin increasing the supply voltage toward V1 in response to the received signal. The supply voltage may reach voltage V5, which may be close to or equal to voltage V1. In some cases, the supply voltage may overshoot voltage V5 before falling back to voltage V5; the overshoot may be reduced or eliminated if the memory device selects a target voltage V0 lower than the nominal supply voltage at time t3.

[0094] In some cases, instead of incrementally adjusting the target voltage (and correspondingly adjusting the supply voltage), whenever no such signal is received... Figure 4A and 4B In the case of the refresh command described herein, as the refresh interval elapses, the memory device can determine when the number of pending refresh intervals meets (e.g., meets or exceeds) a threshold, such as when there are three or more pending refresh intervals (or another predetermined number of pending refresh intervals). The memory device can adjust the supply voltage when the number of refresh operations meets the threshold, and can avoid adjusting the supply voltage when the number of pending refresh operations does not meet the threshold. The memory device can adjust the supply voltage based on two or more such thresholds.

[0095] In some instances, the memory device can determine the number of pending refresh operations based on the window duration. That is, the memory device can determine the number of pending refresh operations based on a rolling time window rather than on the cumulative amount of time.

[0096] Figure 5A block diagram 500 illustrates a memory device 505 supporting voltage adjustment based on pending refresh operations, according to an example disclosed herein. The memory device 505 may be as described in the references... Figure 1 and 2 Examples of various aspects of the described memory device. Memory device 505 may include a refresh interval identification component 510, a refresh command identification component 515, a refresh operation determination component 520, a voltage adjustment component 525, a command component 530, a signal transmission component 535, a windowing component 540, and a refresh execution component 545. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0097] The refresh interval identification component 510 can identify the number of refresh intervals associated with memory cells of the refresh memory device.

[0098] The refresh command identification component 515 can identify the number of received refresh commands. In some instances, the refresh command identification component 515 can increase the number of received refresh commands to be identified based on the receipt of the first refresh command.

[0099] The refresh operation determination component 520 can determine the number of refresh operations by determining the difference between the number of refresh intervals and the number of received refresh commands. In some cases, refresh operations are pending refresh operations. In some instances, the refresh operation determination component 520 can adjust the number of refresh operations based on increasing the number of received refresh commands identified.

[0100] In some instances, the refresh operation determining component 520 can determine that the number of refresh operations meets a threshold, wherein adjusting the supply voltage includes adjusting the supply voltage based on determining that the number of refresh operations meets the threshold.

[0101] In some instances, the refresh operation determining component 520 may determine the second number of refresh operations by determining a second difference between a second number of refresh intervals and a second number of received refresh commands after adjusting the supply voltage. In some instances, the refresh operation determining component 520 may determine that the second number of refresh operations satisfies a second threshold.

[0102] Voltage adjustment component 525 can adjust the supply voltage associated with the memory device based on the number of refresh operations. In some instances, voltage adjustment component 525 can adjust the supply voltage associated with the memory device based on the number of pending refresh operations before at least some of the pending refresh operations are performed. In some instances, adjusting the supply voltage includes increasing the supply voltage from a first voltage to a second voltage based on the number of refresh operations.

[0103] In some instances, the voltage adjustment component 525 can readjust the supply voltage based on the adjustment amount of the received refresh command.

[0104] In some instances, the voltage adjustment component 525 may increase the target voltage from a first target voltage to a second target voltage based on the identification of a first refresh interval.

[0105] In some instances, the voltage adjustment component 525 may increase the target voltage from a second target voltage to a third target voltage, at least in part, based on the identification of a second refresh interval.

[0106] In some instances, the voltage adjustment component 525 can reduce the target voltage from a second target voltage to a third target voltage based on a received refresh command.

[0107] In some instances, the voltage adjustment component 525 may readjust the supply voltage based on determining that a second number of refresh operations meet a second threshold.

[0108] In some instances, adjusting the supply voltage involves increasing the supply voltage from a first voltage to a second voltage based on the number of pending refresh operations. In some cases, the value of the second voltage is based on the number of refresh operations.

[0109] The refresh execution component 545 can perform at least some of the pending refresh operations based on adjusting the supply voltage associated with the memory device.

[0110] Command component 530 may receive a first refresh command after adjusting the supply voltage. In some instances, command component 530 may receive a refresh command after increasing the target voltage from a first target voltage to a second target voltage.

[0111] The signal transmission component 535 can transmit a signal indicating a target voltage to the power management component based on the number of refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage based on the target voltage by the power management component.

[0112] The window opening component 540 can identify the window duration, wherein identifying the refresh interval and refresh command is included during the window duration.

[0113] Figure 6 The flowchart illustrates one or more methods 600 supporting voltage adjustment based on pending refresh operations, according to examples disclosed herein. The operation of method 600 may be implemented by a memory array or its components as described herein. For example, the operation of method 600 may be implemented by reference to... Figure 5The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0114] At position 605, the memory array can identify the number of refresh intervals associated with memory cells of the refresh memory device. (Refer to reference...) Figure 1 The method described in section 4 performs the operation of 605. In some instances, aspects of the operation of 605 may be derived from, as referenced... Figure 5 The refresh interval identification component described is executed.

[0115] At position 610, the memory array can identify the number of refresh commands received. This can be based on... Figure 1 The method described in section 4 performs the operation of 610. In some instances, aspects of the operation of 610 may be derived from, as referenced... Figure 5 The refresh command described is executed by the identification component.

[0116] At position 615, the memory array can determine the number of refresh operations by determining the difference between the number of refresh intervals and the number of received refresh commands. This can be based on... Figure 1 The method described in section 4 performs the operation of 615. In some instances, aspects of the operation of 615 may be derived from, as referenced... Figure 5 The described refresh operation determines the component to execute.

[0117] At 620, the memory array can adjust the supply voltage associated with the memory device based on the number of refresh operations. See reference... Figure 1 The method described in section 4 performs the operation of 620. In some instances, aspects of the operation of 620 may be derived from, as referenced... Figure 5 The described voltage regulation component is executed.

[0118] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following operations: identifying a number of refresh intervals associated with memory cells of the refresh memory device; identifying a number of received refresh commands; determining a number of refresh operations by determining the difference between the number of refresh intervals and the number of received refresh commands; and adjusting the supply voltage associated with the memory device based on the number of refresh operations.

[0119] In some instances of the method 600 and device described herein, the refresh operation may be a pending refresh operation.

[0120] In some instances of the method 600 and apparatus described herein, adjusting the supply voltage may include operations, features, means, or instructions for increasing the supply voltage from a first voltage to a second voltage based on the number of refresh operations. In some instances of the method 600 and apparatus described herein, the value of the second voltage may be based on the number of refresh operations.

[0121] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: receiving a first refresh command after adjusting the supply voltage; increasing the number of identified refresh commands based on the receipt of the first refresh command; and adjusting the number of refresh operations based on the increased number of identified refresh commands. Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: readjusting the supply voltage based on the adjusted number of received refresh commands.

[0122] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: transmitting a signal indicating a target voltage to a power management component based on the number of refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage based on the target voltage via the power management component.

[0123] In some instances of the method 600 and apparatus described herein, identifying the number of refresh intervals may include operations, features, means, or instructions for increasing the target voltage from a first target voltage to a second target voltage based on identifying the first refresh interval.

[0124] In some instances of the method 600 and apparatus described herein, identifying the number of refresh intervals may include operations, features, means, or instructions for increasing the target voltage from a second target voltage to a third target voltage, at least in part based on identifying a second refresh interval.

[0125] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: receiving a refresh command after increasing a target voltage from a first target voltage to a second target voltage, and decreasing the target voltage from the second target voltage to a third target voltage based on receiving the refresh command.

[0126] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: determining that the number of refresh operations meets a threshold, wherein adjusting the supply voltage includes adjusting the supply voltage based on determining that the number of refresh operations meets the threshold.

[0127] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for performing the following: determining a second number of refresh operations by determining a second difference between a second number of refresh intervals and a second number of received refresh commands after adjusting the supply voltage; determining that the second number of refresh operations satisfies a second threshold; and readjusting the supply voltage based on determining that the second number of refresh operations satisfies the second threshold.

[0128] Some instances of the method 600 and device described herein may further include operations, features, means, or instructions for performing the following: identifying window duration, wherein identifying refresh intervals and refresh commands includes identifying refresh intervals and refresh commands during the window duration.

[0129] Figure 7 The flowchart illustrates one or more methods 700 supporting voltage adjustment based on pending refresh operations, according to examples disclosed herein. The operation of method 700 may be implemented by a memory array or its components as described herein. For example, the operation of method 700 may be implemented by reference to... Figure 5 The described memory array performs the functions described. In some instances, the memory array may execute a set of instructions to control the functional elements of the memory array to perform the described functions. Alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0130] At point 705, the memory array can determine the number of pending refresh operations via the memory devices. (Refer to reference...) Figure 1 The method described in section 4 performs the operation of 705. In some instances, aspects of the operation of 705 may be derived from, as referenced... Figure 5 The described refresh operation determines the component to execute.

[0131] At 710, the memory array can adjust the supply voltage associated with the memory device based on the number of pending refresh operations before performing at least some of them. (Refer to reference...) Figure 1 The method described in section 4 performs the operation of 710. In some instances, aspects of the operation of 710 may be derived from, as referenced... Figure 5 The described voltage regulation component is executed.

[0132] At 715, the memory array can perform at least some of the pending refresh operations based on adjusting the supply voltage associated with the memory device. (See reference...) Figure 1 The method described in section 4 performs the operation of 715. In some instances, aspects of the operation of 715 may be derived from, as referenced... Figure 5 The refresh execution component is described.

[0133] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing: determining the number of pending refresh operations via a memory device; adjusting a supply voltage associated with the memory device based on the number of pending refresh operations before performing at least some of the pending refresh operations; and performing at least some of the pending refresh operations based on the adjusted supply voltage associated with the memory device.

[0134] In some instances of the method 700 and apparatus described herein, adjusting the supply voltage may include operations, features, means, or instructions for increasing the supply voltage from a first voltage to a second voltage based on the number of pending refresh operations.

[0135] Some examples of the method 700 and apparatus described herein may further include operations, features, means, or instructions for performing the following: transmitting a signal indicating a target voltage of the supply voltage to a power management component based on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage based on the target voltage via the power management component.

[0136] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0137] Describe an apparatus. The apparatus may include a memory array; a power management component coupled to the memory array and configured to provide a supply voltage to the memory array, the apparatus being configured to count the number of refresh intervals, count the number of received refresh commands, determine the number of refresh operations by determining the difference between the number of refresh intervals and the number of received refresh commands, and adjust the supply voltage based on the number of refresh operations using the power management component.

[0138] Some instances of the device may include a counter for counting the number of refresh intervals.

[0139] In some instances, the device may be configured to adjust the supply voltage by increasing the supply voltage from a first voltage to a second voltage based on the number of refresh operations.

[0140] In some instances, the value of the second voltage can be based on the number of refresh operations.

[0141] Some instances may further include a signal indicating a target voltage of the supply voltage transmitted from the memory array to a power management component based on the number of refresh operations, wherein the power management component may be configured to adjust the supply voltage based on the target voltage.

[0142] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0143] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0144] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via conductive paths, while in a closed-circuit relationship, signals can travel between components via conductive paths. When a component, such as a controller, couples other components together, it initiates a change in the flow of signals between those components via conductive paths that were previously not permitted.

[0145] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0146] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0147] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated via a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority of charge carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0148] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0149] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0150] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0151] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0152] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of” or “one or more of”) indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0153] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0154] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Identify the number of refresh intervals associated with memory cells of a refresh memory device, wherein the refresh interval in the number of refresh intervals is the duration for performing one or more refresh operations; Identify the number of refresh commands received; The number of pending refresh operations is determined by determining the difference between the number of refresh intervals and the number of received refresh commands; and The supply voltage associated with the memory device is adjusted over a duration based at least in part on the number of pending refresh operations, wherein adjusting the supply voltage associated with the memory device over the duration includes increasing the supply voltage from a first voltage to a second voltage based at least in part on the number of pending refresh operations.

2. The method of claim 1, wherein the value of the second voltage is based at least in part on the number of pending refresh operations.

3. The method according to claim 1, further comprising: After adjusting the supply voltage, a first refresh command is received; The number of refresh commands identified is increased, at least in part, based on the receipt of the first refresh command; as well as The number of pending refresh operations is adjusted, at least in part, based on increasing the number of identified refresh commands received.

4. The method of claim 3, further comprising: The supply voltage is readjusted at least in part based on the number of adjustments received from refresh commands.

5. The method of claim 1, further comprising: A signal indicating a target voltage is transmitted from a registered clock driver (RCD) to a power management component, at least in part based on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage by the power management component at least in part based on the target voltage.

6. The method of claim 1, further comprising: A signal indicating a target voltage is transmitted from the memory device to a power management component, at least in part based on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage by the power management component at least in part based on the target voltage.

7. The method of claim 6, wherein identifying the number of refresh intervals includes a first refresh interval for identifying the number of refresh intervals, the method further comprising: The target voltage is increased from a first target voltage to a second target voltage, at least in part, based on the identification of the first refresh interval.

8. The method of claim 7, wherein identifying the number of refresh intervals includes identifying a second refresh interval after identifying the first refresh interval, the method further comprising: The target voltage is increased from the second target voltage to the third target voltage, at least in part, based on the identification of the second refresh interval.

9. The method of claim 7, further comprising: After increasing the target voltage from the first target voltage to the second target voltage, a refresh command is received. and The target voltage is reduced from the second target voltage to the third target voltage, at least in part, based on receiving the refresh command.

10. The method of claim 1, further comprising: Identifying the window duration, wherein identifying the refresh interval and the refresh command includes identifying the refresh interval and the refresh command during the window duration.

11. The method of claim 1, wherein identifying the refresh interval includes incrementing a refresh interval counter for each elapsed refresh interval, and wherein identifying the refresh command includes decrementing the refresh interval counter for each received refresh command.

12. A method comprising: Identify the number of refresh intervals associated with memory cells of a refresh memory device, wherein the refresh interval in the number of refresh intervals is the duration for performing one or more refresh operations; Identify the number of refresh commands received; The number of pending refresh operations is determined by the difference between the number of refresh intervals and the number of refresh commands received. The number of pending refresh operations is determined to meet a threshold; and The supply voltage associated with the memory device is adjusted over a period of time, at least in part based on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage at least in part based on determining that the number of pending refresh operations meets the threshold.

13. The method of claim 12, further comprising: After adjusting the supply voltage, the second number of pending refresh operations is determined by determining the second difference between the second number of refresh intervals and the second number of received refresh commands; The second number of pending refresh operations is determined to satisfy the second threshold. as well as The supply voltage is readjusted at least in part based on the second number of pending refresh operations satisfying the second threshold.

14. An apparatus comprising: Memory array; and A power management component coupled to the memory array and configured to provide a supply voltage to the memory array, the device being configured to: The number of refresh intervals associated with memory cells of the refresh memory device is counted, wherein the refresh interval in the number of refresh intervals is the duration for performing one or more refresh operations. as well as The supply voltage is adjusted by increasing the supply voltage from a first voltage to a second voltage, at least in part based on the number of refresh intervals.

15. The device according to claim 14, further comprising: A counter used to count the number of refresh intervals.

16. The device of claim 14, wherein the value of the second voltage is based at least in part on the number of refresh intervals.

17. An apparatus comprising: Memory array; and A power management component coupled to the memory array and configured to provide a supply voltage to the memory array, the device being configured to: The number of refresh intervals associated with memory cells of the refresh memory device is counted, wherein the refresh interval in the number of refresh intervals is the duration for performing one or more refresh operations. as well as A signal indicating a target voltage of the supply voltage is transmitted from the memory array to the power management component, at least in part based on the number of refresh intervals, wherein the power management component is configured to adjust the supply voltage at least in part based on the target voltage.

18. A method comprising: The number of pending refresh operations is determined by the memory device; Before performing at least some of the pending refresh operations and based at least in part on the number of pending refresh operations, the supply voltage associated with the memory device is adjusted, wherein adjusting the supply voltage includes increasing the supply voltage from a first voltage to a second voltage based at least in part on the number of pending refresh operations; and At least some of the pending refresh operations are performed, at least in part, based on adjusting the supply voltage associated with the memory device.

19. The method of claim 18, further comprising: A signal indicating a target voltage for the supply voltage is transmitted from a registered clock driver (RCD) to a power management component, based at least in part on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage by the power management component based at least in part on the target voltage.

20. The method of claim 18, further comprising: A signal indicating a target voltage for the supply voltage is transmitted from the memory device to a power management component, at least in part based on the number of pending refresh operations, wherein adjusting the supply voltage includes adjusting the supply voltage by the power management component at least in part based on the target voltage.

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