Method for controlling a multi-level inverter with isolated dc link

Abstract

To improve the voltage balance at the DC link capacitor voltage of a multilevel inverter with a split DC link, a modulation signal (MS) with a modulation signal amplitude (A MS ) of even harmonic signals of the output voltage (U AC ) or the output current (i AC ) of the inverter (1) is calculated from the actual electrical power difference (P diff,act ) of the actual electrical power at the DC link capacitor (C DC1 , C DC2 ) and the setpoint (SP) for setting the output voltage (u AC ) or the output current (i AC ) of the inverter (1) is superimposed with the modulation signal (MS).

Description

[0001] This invention relates to a method for controlling a multilevel inverter with a DC link having at least two DC link capacitors connected to a switching stage having semiconductor switches for setting the output voltage or output current of the inverter according to a given setpoint value. The invention also relates to such a multilevel inverter with inverter control.

[0002] An inverter is a voltage converter that transforms DC voltage (direct current voltage) from a DC power source into AC voltage (alternating current voltage). An inverter uses a switching stage to convert the DC voltage at the input to the AC voltage at the output. The DC voltage at the input is often provided by a DC link connected to a DC power source. This DC power source can be, for example, a photovoltaic module, a battery energy storage device, or the output of an AC / DC or DC / DC converter.

[0003] Bidirectional inverters that enable energy to flow in both directions (i.e., from the input to the output and vice versa) are also known.

[0004] Inverters come in many different well-known topologies, such as multiphase or multistage topologies. Multiphase inverters provide multiphase output voltages, such as three-phase output voltages. A multiphase inverter has at least one switching branch in the switching stage for each phase. The switching branch typically includes series-connected switching elements, such as semiconductor switches like IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), or GaN (Gallium Nitride), and an AC terminal between the high-side and low-side switching elements.

[0005] In a simple implementation, the switching branch contains two switching elements that allow for two voltage levels at the AC terminal. In a more complex implementation, the switching branch contains more than two switching elements connected in series that allow for more than two voltage levels at the AC terminal (multi-level).

[0006] The DC link may include a single capacitor, but especially for multilevel inverters, it may also include multiple capacitors connected in series (separate DC links), such as two capacitors connected in series. The DC terminal between the capacitors can serve as a neutral point and can be clamped into a switching branch in a multilevel inverter via semiconductor switches (such as diodes in passive neutral-point clamped inverters) or transistors (such as IGBTs or MOSFETs in active neutral-point clamped inverters) Uneven DC link capacitor voltages induce unequal stresses on the inverter's electrical components, potentially leading to component and / or inverter failures, and also causing degradation of output waveform quality, which can result in a detrimental increase in total harmonic distortion (THD) of the output voltage. Therefore, voltage imbalance between DC voltages at the disconnected DC link capacitors is undesirable. Various strategies have been proposed to mitigate voltage imbalances in disconnected DC links.

[0007] One known strategy is based on additional hardware at the discrete DC link for voltage balancing. However, this increases the cost and losses of the inverter. Other strategies are based on injection techniques, such as those described, for example, in K. Kang et al., “A Harmonic Voltage Injection Based DC-Link Imbalance Compensation Technique for Single-Phase Three-Level Neutral-Point-Clamped (NPC) Inverters” (MDPI Energies 2018, 11, 1886). In this method, an even-order harmonic signal (e.g., a second-order harmonic signal) is added to a reference signal generated by the inverter's current controller. The switching controller then uses the reference signal with the even-order harmonic to control the switching of semiconductor switches in the inverter's switching branch. The even-order harmonic signal is intended to balance the DC link capacitors, where harmonics cause voltage differences between the DC link capacitors to reduce voltage imbalance between them. The even-order harmonic signal is chosen to be proportional to the difference between the DC capacitor voltages, i.e., proportional to the voltage imbalance. However, with such a proportional gain, the voltage balance control exhibits poor control behavior (e.g., residual offset error, poor transient behavior).

[0008] EP 2 876 793A1 proposes a similar method using a third harmonic to modify the inverter's reference signal. However, instead of modifying the reference signal to balance the DC link voltage, it is modified to minimize the current stress on the DC link capacitors in order to extend their lifespan. A third harmonic signal is added to adjust the amplitude and / or phase difference, thereby minimizing the current stress on the two DC link capacitors.

[0009] The purpose of this invention is to improve the voltage balance of multilevel inverters with discrete DC links.

[0010] This is achieved by calculating a modulated signal with the amplitude of the modulated signal as an even harmonic signal of the inverter's output voltage or output current. The modulated signal is calculated using the actual power difference at at least two DC link capacitors and by superimposing the modulated signal onto a setpoint value used to generate an adjustment reference signal that controls the switching of semiconductor devices to balance the DC link capacitor voltages. This method allows the modulated signal to be controlled so that the actual power difference of the DC link capacitors is compensated, thus balancing the DC link capacitor voltages. Therefore, the modulated signal is always adjusted to the current power difference, which improves the balance of the DC link capacitor voltages. Furthermore, using the power difference to calculate the modulated signal allows for a reaction even before the DC link voltage of the DC link capacitors changes due to the power difference. By using the power difference, it is known how the DC link voltage will change, allowing for influence on it before the voltage changes. Therefore, the transient behavior of voltage balance control can be improved, and control errors can be reduced. Finally, and equally importantly, by using power instead of voltage for balance control, linear control theory can be applied because power has a linear effect on the change of electrical energy in the DC link capacitors over time (which ultimately leads to a voltage change).

[0011] Preferably, the actual power difference is calculated as the AC power difference of the AC power supplied by the DC link capacitor, and optionally as the sum of the AC power difference and the DC power difference of the DC link capacitor. Accordingly, the actual power supplied and consumed by the DC link capacitor is considered when calculating the modulated signal.

[0012] Particularly advantageous is the provision of a setpoint power difference and the calculation of the modulation signal amplitude based on the power difference error, where the power difference error is in the form of the difference between the setpoint power difference and the sum of the actual power difference and the power difference at the DC link capacitor caused by the modulation signal. This allows for control of the power difference based on a given setpoint power difference, and thereby also controls the balance.

[0013] Refer to Figure 1 to... Figure 7 The invention will be described in more detail in Figures 1 to 12. Figure 7Exemplary, illustrative, and non-limiting advantageous embodiments of the invention are shown. The figures illustrate...

[0014] Figure 1 shows a known topology for an inverter with a discrete DC link.

[0015] Figure 2 shows an example of a three-phase multilevel inverter.

[0016] Figure 3 shows an example of a single-phase multilevel inverter.

[0017] Figure 4 It is a control scheme for inverters with balanced control.

[0018] Figure 5 It is a modulated signal calculation based on the actual power difference.

[0019] Figure 6 It involves the calculation of the setpoint power difference, and

[0020] Figure 7 This is an example of a second-order even-harmonic modulation signal.

[0021] Figure 1 illustrates an exemplary design of inverter 1, which is used to convert, for example, a DC voltage U supplied to the input terminal. DC DC voltage U of DC power supply 2 DC Converted to AC voltage at the output terminal u AC In the embodiment shown in Figure 1, the output voltage u AC It has a phase voltage u AC1 u AC2 u AC3 The three-phase output voltage u AC AC output voltage u AC It is supplied to electrical load 3, for example, the power grid. In the case of a balanced load, the output voltage u can be assumed. AC (For example, phase voltage u) AC1 u AC2 u AC3 The phase voltages of the inverter 1 are equal (except for phase shift). The DC power supply 2 can be any DC source as shown in Figure 1 (e.g., a photovoltaic module PV) or a battery storage device, DC / DC converter, AC / DC converter, etc. Although a three-phase inverter is shown in Figure 1, the inverter 1 can have any number of phases, including those with only one phase. The inverter 1 can also be bidirectional, where electrical energy can be transferred from the input to the output and vice versa; that is, the input and output can be switched.

[0022] Inverter 1 includes a DC link 4 at its input side, a switching stage 5, and an optional AC filter 6 at its output side. A device for boosting the DC link voltage U can also be configured at the input of inverter 1. DCLA DC input filter (e.g., an EMC (battery compatibility) filter) and / or a DC / DC converter. An optional AC filter 6 is used to convert the AC output voltage u of inverter 1. AC and AC output current i AC The system is smooth and may also include an EMC filter. An AC relay 7, which allows the inverter 1 to disconnect from the load 3, may optionally be arranged between the inverter 1 and the load 3. When the AC relay 7 is present, it may also be integrated into the inverter 1.

[0023] DC link 4 is implemented as having at least two DC link capacitors C connected in series. DC1 C DC2 Separate DC links. Capacitor C in both DC links. DC1 C DC2 A neutral point N is set between these points. The neutral point N can be connected to the neutral line of the electrical load 3, for example, the neutral line of the power grid (indicated by the dashed line in Figure 1), and / or can be clamped to the switching branch of the switching stage 5 by a semiconductor switch (e.g., a diode in Figure 2 or a transistor in Figure 3) in a multilevel inverter.

[0024] DC link voltage U DCL At DC link 4, it is divided into high-side capacitor C. DC1 The first DC link voltage U at the location DC1 and on the low-side capacitor C DC2 The second DC link voltage U at the location DC2 The neutral point N is located on the high-side capacitor C. DC1 and low-side capacitor C DC2 Between. During the operation of inverter 1, the first DC link voltage U DC1 Second DC link voltage U DC2 It may become unbalanced, that is, U DC1 ≠U DC2 To avoid this, balance control is implemented as described below.

[0025] Switching stage 5 includes n switching branches SLn, where n ≥ 1. Each phase has at least one switching branch SLn, and each switching branch SLn is connected in parallel with DC link 4, i.e., connected in parallel with DC link voltage U. DCL Parallel connection. In each of the n switching branches SLn, at least two semiconductor switches Snm are connected in series, m≥2. An AC terminal ACPn is formed between the semiconductor switches Snm in the switching branch SLn, where the output AC current i of the switching branch SLn is provided. Ln and voltage u LnThe AC terminal ACPn is located between the high-side and low-side switching elements Snm. The AC terminals ACPn of multiple switching branches SLn in switching stage 5 can also be connected together to form the output voltage u. AC One phase. In a multilevel inverter, the switching branch SLn includes a plurality of semiconductor switches Snm connected in series on the high side and the low side. Figures 2 and 3 illustrate exemplary embodiments of a multilevel inverter.

[0026] In the example shown in Figure 2, a passive neutral-clamped three-phase multilevel inverter with a separate DC link 4 and a switching branch 5 is illustrated. The switching branch 5 has three switching branches SL1, SL2, and SL3 (one per phase). In each switching branch SL1, SL2, and SL3, two high-side semiconductor switches S11, S12, S21, S22, S31, and S32 and two low-side semiconductor switches S13, S14, S23, S24, S33, and S34 are connected in series. AC terminals ACP1, ACP2, and ACP3 are formed between the high-side and low-side semiconductor switches Snn. The high-side semiconductor switches Sn1 and Sn2 and the low-side semiconductor switches Sn3 and Sn4 in each switching branch SLn are clamped to the neutral point N of the separate DC link 4 by diodes; that is, the neutral point N is connected between the high-side and low-side semiconductor switches via diodes.

[0027] AC voltage u at AC pole ACPn of the multilevel inverter Ln It can have more than two voltage levels; for example, in the embodiment of Figure 2, it has three voltage levels (U). DC+ , 0, U DC- The AC branch current i supplied at the AC terminal ACPn of the switching branch SLn. Ln In AC filters, a series-connected choke coil (inductor) is often used for filtering to remove high-frequency components of the AC waveform. After the choke coil L, a star-connected filter capacitor C can be installed. F and the filter inductor L connected in series F Star-connected filter capacitor C F The star point of the DC link 4 can also be connected to the neutral point N of the DC link 4 (as indicated by the dashed line in Figure 2). However, the AC filter 6 can also include additional or different filter stages. The neutral point N of the separate DC link 4 can also be connected to the neutral line of the electrical load 3 (as indicated by the dashed line in Figure 2).

[0028] Figure 3 exemplarily illustrates an active neutral-point clamped single-phase multilevel inverter 1. The switching branch SL1 includes four semiconductor switches S11, S12, S13, and S14 connected in series. High-side semiconductor switches S11 and S12 provide a positive AC waveform, and low-side semiconductor switches S13 and S14 provide a negative AC waveform. An AC terminal ACP1 is positioned between the high-side semiconductor switches S11 and S12 and the low-side semiconductor switches S13 and S14. The high-side semiconductor switches S11 and S12 and the low-side semiconductor switches S13 and S14 are clamped to the neutral point N of the DC link 4 via semiconductor switches (e.g., transistors T1 and T2). The neutral point N of the DC link 4 is connected to the neutral line of the electrical load 3 in this configuration.

[0029] The switching branch SLn of the multilevel inverter 1 may also have more than two semiconductor switches on the high and low sides for providing AC voltage u. Ln And multiple voltage levels of the AC terminal ACPn. In this case, DC link 4 can also have more than two DC link capacitors connected in series.

[0030] Inverter controller 10 is used to operate inverter 1 (Figure 1). Different measured values ​​M of inverter 1 (e.g., measured voltage and / or current) can be used to control inverter 1, such as DC voltage U. DC DC link capacitor voltage U CD1 U CD2 Output voltage u AC Output current i AC Or the AC branch current i at AC pole ACPn LN As indicated in Figure 1. The voltage and current sensors used to measure the desired measured value M are well known and are not shown in Figure 1 for simplicity.

[0031] A switching controller 11 is implemented in the inverter controller 10. The switching controller 11 generates switching of the semiconductor switches Snm in the switching stage 5 at a given switching frequency and / or in a given order to produce the desired output voltage u of the inverter 1. AC and / or output current i AC The control signal SCnm (as indicated in Figure 1) is typically provided to a well-known gate driver (not shown) for each semiconductor switch Sn, which is used to implement the switching of the semiconductor switch Sn. The gate driver may also be integrated into the switch controller 11.

[0032] The inverter controller 10 can be implemented on microprocessor-based hardware (such as a computer, microcontroller, digital signal processor, programmable logic controller (PLC), etc.) programmed with control software that operates the inverter 1. The control software is stored in the memory of the inverter controller 10. Alternatively, it can be implemented using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The inverter controller 10 can also be implemented as an analog circuit, an analog computer, or other analog instrument.

[0033] The switching controller 11 and other functions of the inverter controller 10 can be implemented as software running on the inverter controller 10. The inverter controller 10 and the switching controller 11 can also be implemented as separate hardware. In this case, the switching controller 11 can be microprocessor-based hardware such as a microcontroller, computer, digital signal processor, programmable logic controller (PLC), or application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA), and has software. The switching controller 11 can also be implemented as an analog circuit, analog computer, or other analog instrument.

[0034] The switching controller 11 is often implemented as a voltage modulation scheme, such as PWM (Pulse Width Modulation) or a multi-level PWM scheme, which controls the AC branch voltage u at the AC terminal ACPn of the switching branch SLn. Ln The pulse width (duty cycle) and / or the AC branch voltage u at the AC terminal. Ln The voltage level. The AC branch voltage u at AC terminal ACPn. Ln and / or branch current i Ln The average value over time forms the output voltage u of the multilevel inverter 1. AC and / or output current i AC However, the switch controller 11 can also be implemented differently.

[0035] The goal of inverter controller 10 is often to output voltage u AC and / or output current i AC The corresponding setting reference output signal (setting value SP) for inverter 1, for example, the output voltage u ACS Or output current i ACS For example, when the power grid is used as electrical load 3, the reference output voltage u ACS Typically, this is a sinusoidal voltage with a certain amplitude and mains frequency (e.g., 50Hz). The reference output signal is, for example, the output voltage u. ACS (Also having multiple phase voltages and phase angles) can be used as the setpoint value SP for the control of inverter 1 (Figure 1, Figure 4 It is provided to inverter controller 10 and / or switch controller 11.

[0036] like Figure 4 As shown, the balance controller 12 (e.g., software on the inverter controller 10 or switch controller 11 hardware) determines the modulation signal MS superimposed on the setpoint value SP to generate the adjustment reference signal RS for the switch controller 11. The balance controller 12 can also be implemented separately from the inverter controller 10 on, for example, on a separate piece of hardware (microprocessor-based hardware, ASIC, FPGA, etc.) that can be programmed using the balance controller software. The balance controller 12 can also be implemented as an analog circuit, an analog computer, or other analog instrument.

[0037] The control objective of the balance controller 12 is to modulate the setpoint value SP with the modulation signal MS, so that the DC link capacitor voltage U DC1 U DC2 Any voltage difference between (U) DC1 -U DC2 The DC link capacitor voltage U decreases. DC1 U DC2 The voltage difference between them is generated during the operation of inverter 1 over time.

[0038] For the following description, assume that the DC link capacitor C DC1 C DC2 Same, that is, C DC1 =C DC2 =C DC Although the following formula can be easily generalized to different DC link capacitors C DC1 C DC2 The following also assumes that only two DC link capacitors C exist in the separated DC link 4. DC1 C DC2 However, the following formula can be easily generalized to more than two DC link capacitors C. DC1 C DC2 .

[0039] This invention is based on voltage difference (U DC1 -U DC2 ) is composed of DC link capacitor C DC1 C DC2 Consideration should be given to the power difference at the point of connection. DC link capacitor C DC1 C DC2 The different power P at each point causes the DC link capacitor C to... DC1 C DC2 The electrical energy W in the middle changes with time, such as The purpose of the balance controller 12 of the present invention is to compensate for the DC link capacitor C by appropriately controlling the modulation signal MS. DC1 C DC2The power difference at the point is used to balance the DC link capacitor voltage U. DC1 U DC2 The effect.

[0040] First, calculate the DC link capacitor C. DC1 C DC2 Power difference P at the point diff,act The actual value. During inverter 1 operation, there is capacitor C flowing into DC link 4. DC1 C DC2 DC power and capacitor C flowing out of DC link 4 DC1 C DC2 AC power. Actual power difference P diff,act It is the DC power difference P diff,DC The difference between AC power P diff,AC The sum, that is, P diff,act =P diff,DC +P diff,AC Therefore, the actual power difference P diff,act It is the DC link capacitor C DC1 C DC2 The current value of the power difference at that point. However, the DC power difference P can be ignored. diff,DC In this case, the actual power difference P diff,act This will equal the AC power difference P diff,AC .

[0041] Flow into capacitor C DC1 C DC2 DC power P diff,DC The difference can be calculated as P. diff,DC =I DC (U DC1 -U DC2 ), where the DC link current I DC (This can be provided as a measured value M) is the current flowing through the DC link capacitor C. DC1 C DC2 DC current. DC link current I DC It flows only on the DC side of inverter 1.

[0042] Capacitor C from DC link DC1 C DC2 AC power difference P diff,AC It is composed of high-side capacitor C DC1 and low-side capacitor C DC2 The difference between the supplied AC power. After the operation of inverter 1, the high-side capacitor C DC1 Provide output voltage u AC and output current i ACThe first (e.g., positive) half-wave, and the low-side capacitor C DC1 Provide output voltage u AC and output current i AC The second (e.g., negative) half-wave.

[0043] Given AC voltage u AC and AC current i AC The AC power is usually given as The AC signal has a known frequency f. N This is under AC voltage u AC and AC current i AC 1 / f of the period N Calculate the average power over the time period.

[0044] At the active voltage amplitude U A and phase angle Under these conditions, the AC output voltage u AC The AC output voltage u of the p-phase ACp It can be modeled as In the same way, at current amplitude I A In the case of active AC output current i AC The AC output current of the p-phase can be modeled as Optionally (indicated by the box), a blind component (with blind voltage amplitude U) may also be considered. B and blind current amplitude I B ).

[0045] For three-phase voltage and current, the phase angle of the three phases It can be set to Caused output voltage and output current

[0046] Voltage amplitude U A U B and / or current amplitude I A I B It is either known or can be provided as a measurement value M.

[0047] Then through the first half-wave and second half-wave AC voltage u AC and AC current i AC The power difference gives the AC power difference P of phase p of inverter 1. diff,AC For phase angle The p phase can be obtained through Calculate the power difference. For the phase angle... For phase p, the integration boundary needs to be determined based on the phase angle. Shift (e.g., shift 1 / 3f for a three-phase inverter 1)N This allows the half-wave to be correctly integrated. Since all phase p is connected to the DC link capacitor C... DC1 C DC2 If power is drawn, then the AC power difference P diff,AC It is the sum of the single-phase AC power differences, that is,

[0048] For the three-phase inverter 1 shown in Figure 2, P diff,AC It can be calculated as, for example

[0049] Using AC voltage u AC and AC current i AC The advantage of the average power over the period is that the integral can be solved analytically, and can be expressed using AC voltage u. AC and AC current i AC The current value or its magnitude I A U A Simply calculate the AC power difference P diff,AC .

[0050] However, it will also be possible to determine the outcome based on P. AC =u AC (t)·i AC (t) gives the instantaneous power to calculate the AC power difference P. diff,AC .

[0051] In addition, under these circumstances, the AC power difference P diff,AC By capacitor C through DC link DC1 C DC2 The difference in AC power absorbed is defined as, P diff,AC =P AC,C1 -P AC,C2 If from DC link capacitor C DC1 Power is drawn without being drawn from the DC link capacitor C DC2 If power is drawn, then P diff,AC =P AC,C1 -0 = P AC,C1 Conversely, if the capacitor C in the DC link... DC2 Power is drawn without being drawn from the DC link capacitor C DC1 If power is drawn, then P diff,AC =0-P AC,C2 =-P AC,C2 If from DC link capacitor C DC1 C DC2 The power absorbed by both is P, therefore the power difference between AC and P is P. diff,AC Including DC link capacitor C DC1 C DC2 The power components of both.

[0052] However, this will require more computation time and computing power because the product of voltage and current will have to be calculated at every required point in time (e.g., every millisecond).

[0053] DC link capacitor C DC1 C DC2 The overall actual power difference P between them diff,act Follow DC power difference P diff,DC The difference between AC power P diff,AC The sum. This, of course, represents the instantaneous value of the power difference that can be calculated at a given time step (e.g., per millisecond). For the voltage balance of the present invention, the DC power difference P can optionally be considered. diff,DC This led to P diff,act =P diff,AC [+P diff,DC The actual power difference P diff,act It will be compensated to balance the DC link capacitor voltage U DC1 U DC2 .

[0054] The allowable compensation power difference P needs to be selected. diff.act The appropriate modulation signal MS. The output voltage u of one phase of inverter 1, which serves as the output signal. ACp Typically, the frequency is f. N And the amplitude is U A A sinusoidal (or sinusoidal) signal, that is, Time is t (e.g., Figure 7 As shown in the diagram). With such an output voltage u ACp Its phase is related to the output phase voltage u ACp Synchronous even-harmonic complementary triangular signals (i.e., cosine signals in the case of sinusoidal output signals or sinusoidal signals in the case of cosine output signals) are the modulating signal MS ( Figure 7 This is a good choice because such even harmonics increase the power of the first half-wave of the output signal and decrease the power of the second half-wave. Similarly, shifting the corresponding triangular signal after phase shifting (i.e., a sine signal in the case of a sinusoidal output signal or a cosine signal in the case of a cosine output signal), for example, by -π / 4 to obtain a second-order even harmonic, can certainly accomplish this task. The DC link capacitor C introduced by the modulation signal MS... DC1 C DC2 The power difference at that point is used to compensate for the DC link capacitor C. DC1 C DC2 The power difference at that point is also used to balance the DC link capacitor voltage U. DC1 U DC2 The voltage difference.

[0055] For those with phase angle p-phase n-order even harmonic current i hp For example, selected as Where n is even and I nh It is the amplitude of the modulated signal A MS Alternatively, as indicated in the block diagram, even harmonic components may also be considered, where m is a non-even integer. The even harmonics can be used to reduce the DC link voltage required to generate the modulated signal MS.

[0056] For a three-phase inverter 1, the nth even-order harmonic current i h Will follow, for example

[0057]

[0058] If non-even harmonic components are introduced along with the modulation signal MS, these harmonics will also appear in the output voltage, which will lead to

[0059]

[0060] For the nth even harmonic current i of inverter 1 h and output voltage u AC As mentioned above, this applies to P. diff,AC The calculation described is based on the nth even harmonic current i of the modulating signal MS. h The resulting DC link capacitor C DC1 C DC2 Power difference P at the point diff,h Therefore, due to the even-order harmonic current i h The resulting power difference P diff,h Similarly, it is calculated as the sum of the power differences between the positive and negative half-waves of the p phases as described above.

[0061] For the second harmonic current i h (n=2), for example, the power difference P of the three-phase inverter 1 in Figure 2. diff,h It can be calculated as

[0062] In order to control the DC link capacitor C DC1 C DC2 Instantaneous power difference (P) at point diff,h act+P diff,h ), requires a setpoint power difference P diff,set ,like Figure 5 As shown in the diagram. Then, the control objective will be to compensate for the power difference error [P]. diff,set -(P diff,act +P diff,h That is, the control target will be [P] diff,set -(P diff,act +Pdiff,h The amplitude of the modulated signal A is 0. Using the above formula, the amplitude of the modulated signal A is... MS (For example, the nth even harmonic current i, which is the modulation signal MS) h Current amplitude I nh ) can be calculated as, for example

[0063] It should be mentioned that, similarly, those with voltage amplitude U nh Even harmonic voltage signal u h Non-even harmonic current i h It can also be used as a modulation signal MS.

[0064] In each time step of the balance controller 12, the modulated signal MS(I) can be calculated. nh or U nh The amplitude of the modulation signal MS is determined by superimposing the modulation signal MS onto the setpoint value SP of the inverter controller, and the resulting modulation signal MS is injected to generate the adjustment reference signal RS for the switching controller 11. Figure 4 ).

[0065] The time step of the balance controller 12 often does not correspond to the sampling time of the switch controller 11. Typically, the sampling time of the switch controller 11 is much shorter than the time step of the balance controller 12. Preferably, the amplitude of the modulated signal MS is calculated periodically (e.g., every 1 ms).

[0066] The superposition of the setpoint value SP and the modulated signal MS can be performed in different ways. A complete cycle (frequency f) can be added. N The signal is received by the switch controller 11, which can sample the received signal at its switching frequency. A setpoint value SP can also be provided at the switching frequency of the switch controller 11, and the even-order harmonic modulation signal MS can be sampled at the switching frequency to provide a corresponding sampling rate for the modulation signal MS.

[0067] For multiphase inverter 1, the setpoint value SP can of course be a vector with p phase vector elements (i.e., the setpoint value for each phase p). Then, the modulation signal MS will be at the correct phase angle. It is superimposed on the setpoint value of each phase.

[0068] Because it is necessary to compensate for the DC link capacitor voltage U DC1 U DC2 The difference, therefore, is taken as the DC link capacitor voltage U. DC1 U DC2 The function selects the setpoint power difference P diff,set That is, P diff,set =f(U DC1 U DC2 ).

[0069] refer to Figure 6 This shows the calculation of the setpoint power difference P. diff,set This is an advantageous approach.

[0070] DC link capacitor C DC1 C DC2 The actual energy difference W between them diff It can be calculated as DC link capacitor voltage U DC1 U DC2 This can be provided as a measured value M. Additionally, the voltage difference U between the setpoint DC link capacitors can be used. diff,set and DC link capacitor voltage U DC1 U DC2 The actual and setpoint energy difference W diff,set Calculated as Typically, the target of balance control is U diff,set =0, therefore W diff,set =0. Using the actual energy difference W diff Energy difference W from the set point diff,set The error between them and the time constant τ of the selected or given balance control. bal To calculate the power difference, that is, It is used as the setpoint power difference P diff,set This gives the balanced controller 12 PI (proportional-integral) controller characteristics, although different control characteristics can also be achieved. Time constant τ bal The control parameters of the balance controller 12 can be considered as being appropriately set to obtain the desired control behavior and control stability of the balance controller 12. In this way, the balance controller 12 will be implemented as a cascaded control, such as... Figure 6 As shown in the image.

[0071] The setpoint power difference P can be repeated within a given time step of the balance controller 12. diff,set The modulation signal MS is calculated. Before the next calculation, the calculated modulation signal MS is superimposed on the setpoint value SP of the inverter controller 10.

Claims

1. A method for controlling a multilevel inverter (1) having a DC link (4), said DC link (4) having at least two DC link capacitors (C DC1 C DC2 ), connected to the switching stage (5), the switching stage (5) having a function for setting the output voltage (u) of the inverter (1) according to a given setpoint value (SP). AC ) or output current (i AC The method comprises the following steps: (1) Semiconductor switch (Snm) - Calculate the output voltage (u) of the inverter (1). AC ) or the output current (i AC The even harmonic signal of the modulating signal has an amplitude (A) MS The modulated signal (MS) of the at least two DC link capacitors (C) DC1 C DC2 The actual power difference (P) at the actual electrical power at point ) diff,act ) calculate the modulated signal (MS), and - The modulation signal (MS) is superimposed on the setpoint value (SP) to generate an adjustment reference signal (RS), which is used to control the switching of the semiconductor switch (Snm) to balance the DC link capacitor (C). DC1 C DC2 DC link capacitor voltage (U) at ) DC1 U DC2 ).

2. The method according to claim 1, characterized in that, The actual power difference (P) diff,act ) is calculated as being caused by the DC link capacitor (C) DC1 C DC2 The AC power difference (P) provided by the AC power diff,AC ).

3. The method according to claim 2, characterized in that, The AC power difference (P) diff,AC The output voltage (u) is calculated as the output voltage. AC ) and the output current (i AC The first half-wave of the output voltage (u) AC ) and the output current (i AC The power difference of the second half-wave.

4. The method according to claim 2 or 3, characterized in that, For a multiphase inverter (1) with p phases, the AC power difference (P) diff,AC The difference is calculated as p single-phase AC power differences (P). diff,ACp ) and.

5. The method according to claim 2 or 3, characterized in that, The actual power difference (P) diff,act ) is calculated as the DC link capacitor (C DC1 C DC2 The AC power difference (P) diff,AC ) and DC power difference (P diff,DC ) and.

6. The method according to claim 2 or 3, characterized in that, Using the output voltage (u) AC ) and the output current (i AC The AC power difference (P) is calculated based on the average electrical power over one cycle. diff,AC Or the AC power difference (P) diff,AC The output voltage (u) is calculated as follows. AC ) and the output current (i AC The instantaneous power of ).

7. The method according to claim 6, characterized in that, The AC power difference (P) of phase p of the inverter (1) diff,AC ) was calculated as .

8. The method according to claim 5, characterized in that, The DC power difference (P) diff,DC ) was calculated as Among them, DC link current (I DC ) flows through the DC link capacitor (C) DC1 C DC2 ).

9. The method according to any one of claims 1 to 3, characterized in that, Provide setpoint power difference (P) diff,set ), and calculate the amplitude of the modulated signal (A) using the power difference error. MS ), where the power difference error is the power difference at the set point (P) diff,set The difference between the actual power (P) and the actual power (P) diff,act The DC link capacitor (C) caused by the modulation signal (MS) and the modulation signal (MS) DC1 C DC2 The power difference (P) at point ) diff,h The difference between the sums of ( ) is in the form of a denominator.

10. The method according to claim 9, characterized in that, The setpoint power difference (P) diff,set ) is selected as the DC link capacitor voltage (U DC1 U DC2 The function of ).

11. The method according to claim 9, characterized in that, Calculate the DC link capacitor (C) DC1 C DC2 The actual energy difference (W) between them diff ), and at a given setpoint, the DC link capacitor voltage difference (U diff,set Calculate the setpoint energy difference (W) under the condition of diff,set ), and using the actual energy difference (W) diff The energy difference between the set point and the energy difference (W) diff,set The energy error between the setpoint power difference (P) is calculated. diff,set ).

12. The method according to claim 11, characterized in that, The DC link capacitor (C) DC1 C DC2 The actual energy difference (W) between them diff ) was calculated as .

13. The method according to claim 11, characterized in that, The setpoint energy difference (W) diff,set ) was calculated as .

14. The method according to claim 11, characterized in that, The energy error is used to calculate the setpoint power difference (P). diff,set ) calculated as The time constant of the balance controller is known. .

15. A multilevel inverter having a DC link (4) and a switching stage (5), said DC link (4) having at least two DC link capacitors (C DC1 C DC2 The switching stage (5) has a semiconductor switch (Snm) connected to the DC link (4) and a method for setting the output voltage (u) of the inverter (1) according to a given setpoint value (SP). AC ) or output current (i AC The inverter controller (10) of the inverter is characterized in that, A balance controller (12) is configured to calculate the output voltage (u) of the inverter (1). AC ) or the output current (i AC The even harmonic signal of the modulating signal has an amplitude (A) MS The modulated signal (MS) of the balanced controller (12) is used by the at least two DC link capacitors (C). DC1 C DC2 The actual power difference (P) at the actual electrical power at point ) diff,act The method calculates the modulation signal (MS) and is characterized by providing a switch controller (11) that receives an adjustment reference signal (RS) for controlling the switching of the semiconductor switch (Snm), the adjustment reference signal (RS) being generated by superimposing the modulation signal (MS) onto the setpoint value (SP) so that the DC link capacitor (C) DC1 C DC2 DC link capacitor voltage (U) at ) DC1 U DC2 )balance.

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