Toner cartridge chip, toner cartridge and printer

Abstract

The application provides a selenium drum chip, a selenium drum and a printer. The selenium drum chip comprises a printer interface, a selenium drum chip controller and a toner cartridge interface. The printer interface comprises a first test terminal, a first I / O terminal and a first ground terminal. The selenium drum chip controller comprises a power supply pin, an I / O pin and a ground pin. The toner cartridge interface comprises a second test terminal, a second I / O terminal and a second ground terminal. The first test terminal and the second test terminal are electrically connected. The first I / O terminal, the I / O pin and the second I / O terminal are electrically connected with each other. The first ground terminal, the ground pin and the second ground terminal are electrically connected with each other. The selenium drum chip further comprises a direct power supply circuit for obtaining power from the first power supply terminal of the printer interface or an auxiliary power supply circuit for obtaining power from the first test terminal. The direct power supply circuit or the auxiliary power supply circuit supplies power to the power supply pin and / or the first I / O terminal. The selenium drum chip of the application can improve the stability of I / O terminal power supply.

Description

Technical Field

[0001] This invention relates to the field of printer technology, specifically to a toner cartridge chip, a toner cartridge using the toner cartridge chip, and a printer using the toner cartridge. Background Technology

[0002] Currently, after a certain amount of toner is consumed in a printer drum, it needs to be refilled by connecting a toner cartridge so that the drum can be reused. To facilitate monitoring of the refilling process, one type of printer uses three contacts to electrically connect to the drum chip and the toner cartridge chip, thereby enabling information exchange between the printer control circuit and these chips. The three contact pins are defined as I / O, GND, and Test. The I / O pin provides power to the drum chip and toner cartridge chip while simultaneously exchanging data with the printer. For example... Figure 1 This diagram illustrates a circuit schematic of a toner cartridge chip and a toner cartridge chip during toner filling. The toner cartridge chip 2 includes a printer interface 21, a toner cartridge chip controller 22, and a toner cartridge interface 23. The toner cartridge chip 2 is electrically connected to the printer control circuit 1 via the printer interface 21, and the toner cartridge chip 3 is electrically connected to the toner cartridge chip 2 via the toner cartridge interface 23. The Test pin and resistors R2, R3, R4, S1, and S2 connected to the Test pin are used to allow the printer to detect whether each step of the toner filling process is correct. The specific detection steps are techniques known to those skilled in the art, such as those described in Chinese patent application CN110989312A. Since the I / O pins of the printer control circuit 1 also provide power to the toner cartridge chip controller 22 and the toner cartridge chip controller 31 while exchanging data, the total power consumption of the chips is subject to strict requirements. If the total power consumption of the toner cartridge chip controller 22 and the toner cartridge chip controller 31 is too high, it will pull down the data level on the I / O pins, leading to data errors in the toner cartridge chip controller 22 and / or the toner cartridge chip controller 31, resulting in the printer not recognizing the device. Summary of the Invention

[0003] The primary objective of this invention is to provide a toner cartridge chip that improves the power supply stability of I / O terminals.

[0004] A second objective of this invention is to provide a toner cartridge that improves the power supply stability of I / O terminals.

[0005] A third objective of this invention is to provide a printer that improves the power supply stability of the I / O terminals.

[0006] To achieve the aforementioned first objective, the toner cartridge chip provided by the present invention includes a printer interface, a toner cartridge chip controller, and a toner cartridge interface. The printer interface includes a first test terminal, a first I / O terminal, and a first ground terminal. The toner cartridge chip controller includes a power pin, an I / O pin, and a ground pin. The toner cartridge interface includes a second test terminal, a second I / O terminal, and a second ground terminal. The first test terminal and the second test terminal are electrically connected. The first I / O terminal, the I / O pin, and the second I / O terminal are electrically connected to each other. The first ground terminal, the ground pin, and the second ground terminal are electrically connected to each other. The toner cartridge chip also includes a direct power supply circuit for obtaining power from the first power terminal of the printer interface or an auxiliary power supply circuit for obtaining power from the first test terminal. The direct power supply circuit or the auxiliary power supply circuit supplies power to the power pin and / or the first I / O terminal.

[0007] As can be seen from the above scheme, the toner cartridge chip of the present invention, by setting up a direct power supply circuit for obtaining power from the first power terminal of the printer interface and an auxiliary power supply circuit for obtaining power from the first test terminal, and delivering power to the power pin and / or the first I / O terminal, ensures that only the toner cartridge chip obtains power from the first I / O terminal when power is delivered to the power pin. Therefore, the requirements for the printer's I / O driving capability are reduced, improving the stability of the I / O terminal power supply. When power is delivered to the first I / O terminal, it increases the driving capability of the first I / O terminal. Thus, even if the toner cartridge chip and the toner cartridge chip simultaneously obtain power from the first I / O terminal, it is difficult to lower the data level on the first I / O terminal, thereby improving the stability of the I / O terminal power supply. Furthermore, the toner cartridge chip and / or the toner cartridge chip can use processors with slightly higher power consumption, allowing for a wider range of selectable devices.

[0008] In a further embodiment, the direct power supply circuit includes a first current-limiting resistor, the first end of which is electrically connected to a first power supply terminal, and the second end of which is electrically connected to a power supply pin.

[0009] Therefore, the function of setting the first current-limiting resistor in the direct power supply circuit is to limit the current and pull it up, so as to ensure the stability of the power supply to the power pin.

[0010] In a further embodiment, the direct power supply circuit includes a first NMOS transistor, a first PMOS transistor, a first voltage divider resistor, a second voltage divider resistor, and a second current-limiting resistor. The first end of the second current-limiting resistor is electrically connected to the first power supply terminal, and the second end of the second current-limiting resistor is electrically connected to the power supply pin. The gate of the first NMOS transistor is electrically connected to the first I / O terminal, the drain of the first NMOS transistor is electrically connected to the second end of the second current-limiting resistor, the source of the first NMOS transistor is electrically connected to the first end of the first voltage divider resistor, the second end of the first voltage divider resistor is electrically connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is electrically connected to the ground pin, the gate of the first PMOS transistor is electrically connected to the second end of the first voltage divider resistor, the drain of the first PMOS transistor is electrically connected to the second end of the second current-limiting resistor, and the source of the first PMOS transistor is electrically connected to the I / O pin.

[0011] Therefore, the direct power supply circuit consists of a first NMOS transistor, a first PMOS transistor, a first voltage divider resistor, a second voltage divider resistor, and a second current-limiting resistor. When the first I / O terminal outputs a high level, the first NMOS transistor is turned on. The voltage at the first power supply terminal is divided by the first and second voltage divider resistors. If the voltage difference between the divided voltage and the voltage at the first I / O terminal when it is high is greater than the turn-on voltage VGS, then the first PMOS transistor is turned on, and the first power supply terminal supplies power to the I / O pin, thereby pulling the high level on the I / O pin up to approximately equal to the voltage output by the first power supply terminal. When the first I / O terminal outputs a low level, the first NMOS transistor is turned off. Since the gate and source of the first PMOS transistor are both at low levels, it will not be turned on, and the voltage at the first power supply terminal will not affect the voltage on the I / O pin.

[0012] In a further embodiment, the resistance values ​​of the first voltage divider resistor and the second voltage divider resistor are equal.

[0013] In a further embodiment, the direct power supply circuit includes a third current-limiting resistor, the first end of which is electrically connected to the first power supply terminal, and the second end of which is electrically connected to the first I / O terminal.

[0014] Therefore, the purpose of setting the third current-limiting resistor in the direct power supply circuit is to limit the current and pull it up, so as to ensure the stability of the power supply to the I / O terminals.

[0015] In a further embodiment, the auxiliary power supply circuit includes a fourth current-limiting resistor, the first end of which is electrically connected to the first test terminal, and the second end of which is electrically connected to the first I / O terminal.

[0016] Therefore, it can be seen that the function of the fourth current-limiting resistor in the auxiliary power supply circuit is to limit current and pull up, so as to ensure the stability of power supply to the I / O terminals.

[0017] In a further embodiment, the auxiliary power supply circuit includes a second NMOS transistor, a second PMOS transistor, a third voltage divider resistor, a fourth voltage divider resistor, and a fifth current-limiting resistor. The first end of the fifth current-limiting resistor is electrically connected to the first test terminal. The gate of the second NMOS transistor is electrically connected to the first I / O terminal. The drain of the second NMOS transistor is electrically connected to the second end of the fifth current-limiting resistor. The source of the second NMOS transistor is electrically connected to the first end of the third voltage divider resistor. The second end of the third voltage divider resistor is electrically connected to the first end of the fourth voltage divider resistor. The second end of the fourth voltage divider resistor is electrically connected to the ground pin. The gate of the second PMOS transistor is electrically connected to the second end of the third voltage divider resistor. The drain of the second PMOS transistor is electrically connected to the second end of the fifth current-limiting resistor. The source of the second PMOS transistor is electrically connected to the I / O pin.

[0018] Therefore, by setting up a second NMOS transistor, a second PMOS transistor, a third voltage divider resistor, and a fourth voltage divider resistor, when the first I / O terminal outputs a high level, the second NMOS transistor is turned on. The voltage at the first test terminal is divided by the third and fourth voltage divider resistors. If the voltage difference between the divided voltage and the voltage at the first I / O terminal when it is high is greater than the turn-on voltage VGS, then the second PMOS transistor is turned on, and the first test terminal supplies power to the I / O pin, thereby pulling the high level on the I / O pin up to approximately equal to the voltage output by the first test terminal. When the first I / O terminal outputs a low level, the second NMOS transistor is turned off. Since the gate and source of the second PMOS transistor are both at low levels, it will not be turned on, and the voltage at the first test terminal will not affect the voltage on the I / O terminal.

[0019] In a further design, the resistance values ​​of the third and fourth voltage divider resistors are equal.

[0020] To achieve the second objective mentioned above, the toner cartridge provided by the present invention is provided with a toner cartridge chip, and the toner cartridge chip uses the aforementioned toner cartridge chip.

[0021] To achieve the third objective mentioned above, the printer provided by the present invention includes a printer control circuit and a toner cartridge, wherein the toner cartridge chip is the aforementioned toner cartridge chip; the printer control circuit is electrically connected to the printer interface. Attached Figure Description

[0022] Figure 1 This is a circuit diagram of the existing toner cartridge chip and toner cartridge chip circuit during toner filling connection.

[0023] Figure 2 This is a circuit schematic diagram of the first embodiment of the toner cartridge chip of the present invention.

[0024] Figure 3 This is a circuit schematic diagram of the second embodiment of the toner cartridge chip of the present invention.

[0025] Figure 4This is a circuit schematic diagram of the third embodiment of the toner cartridge chip of the present invention.

[0026] Figure 5 This is a circuit schematic diagram of the fourth embodiment of the toner cartridge chip of the present invention.

[0027] Figure 6 This is a circuit schematic diagram of the fifth embodiment of the toner cartridge chip of the present invention.

[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0029] First embodiment of toner cartridge chip:

[0030] like Figure 2 As shown, in this embodiment, the toner cartridge chip 4 includes a printer interface 41, a toner cartridge chip controller 42, and a toner cartridge interface 43. The printer interface 41 is used to connect to the printer control circuit 1, and the toner cartridge interface 43 is used to connect to the toner cartridge chip 3.

[0031] The printer interface 41 includes a first power terminal 411, a first test terminal 412, a first I / O terminal 413, and a first ground terminal 414. The toner cartridge chip controller 42 includes a power pin VCC1, an I / O pin I / O1, and a ground pin GND1. The toner cartridge interface 43 includes a second test terminal 431, a second I / O terminal 432, and a second ground terminal 433. The first test terminal 412 and the second test terminal 431 are electrically connected. The first I / O terminal 413, the I / O pin I / O1, and the second I / O terminal 432 are electrically connected to each other. The first ground terminal 414, the ground pin GND1, and the second ground terminal 433 are electrically connected to each other.

[0032] The toner cartridge chip 4 also includes a direct power supply circuit 44, which obtains power from the first power terminal 411 of the printer interface 41 and supplies power to the power pin VCC1. In this embodiment, the direct power supply circuit 44 includes a first current-limiting resistor R5, the first end of which is electrically connected to the first power terminal 411, and the second end of which is electrically connected to the power pin VCC1.

[0033] The toner cartridge chip 4 also includes a first capacitor C1, and the power supply pin VCC1 is electrically connected to the ground pin GND1 through the first capacitor C1.

[0034] In this embodiment, the drum chip 4 is electrically connected to the first power terminal 411 via a direct power supply circuit 44 through the power supply pin VCC1 of the drum chip controller 42. This allows the drum chip controller 42 to be directly powered by the printer power supply, so that only the toner cartridge chip 3 obtains power from the first I / O terminal 413. Therefore, the requirements for the printer's I / O driving capability are reduced, and the power supply stability of the I / O terminal is improved. At the same time, the drum chip and / or toner cartridge chip can use processors with slightly higher power consumption, and the range of selectable devices is wider.

[0035] Second embodiment of the toner cartridge chip:

[0036] like Figure 3 As shown, in this embodiment, the toner cartridge chip 5 includes a printer interface 51, a toner cartridge chip controller 52, and a toner cartridge interface 53. The printer interface 51 is used to connect to the printer control circuit 1, and the toner cartridge interface 53 is used to connect to the toner cartridge chip 3.

[0037] The printer interface 51 includes a first power terminal 511, a first test terminal 512, a first I / O terminal 513, and a first ground terminal 514. The toner cartridge chip controller 52 includes a power pin VCC2, an I / O pin I / O2, and a ground pin GND2. The toner cartridge interface 53 includes a second test terminal 531, a second I / O terminal 532, and a second ground terminal 533. The first test terminal 512 and the second test terminal 531 are electrically connected. The first I / O terminal 513, the I / O pin I / O2, and the second I / O terminal 532 are electrically connected to each other. The first ground terminal 514, the ground pin GND2, and the second ground terminal 533 are electrically connected to each other.

[0038] The toner cartridge chip 5 also includes a direct power supply circuit 54, which is used to obtain power from the first power terminal 511 of the printer interface 51 and to transmit power to the power pin VCC2 and the first I / O terminal 513.

[0039] In this embodiment, the direct power supply circuit 54 includes a second current-limiting resistor R6, a first NMOS transistor Q1, a first PMOS transistor Q2, a first voltage divider resistor R7, and a second voltage divider resistor R8. The first end of the second current-limiting resistor R6 is electrically connected to the first power supply terminal 511, and the second end of the second current-limiting resistor R6 is electrically connected to the power supply pin VCC2. The gate of the first NMOS transistor Q1 is electrically connected to the first I / O terminal 513, the drain of the first NMOS transistor Q1 is electrically connected to the second end of the second current-limiting resistor R6, the source of the first NMOS transistor Q1 is electrically connected to the first end of the first voltage divider resistor R7, the second end of the first voltage divider resistor R7 is electrically connected to the first end of the second voltage divider resistor R8, and the second end of the second voltage divider resistor R8 is electrically connected to the ground pin GND2. The gate of the first PMOS transistor Q2 is electrically connected to the second end of the first voltage divider resistor R7, the drain of the first PMOS transistor Q2 is electrically connected to the second end of the second current-limiting resistor R6, and the source of the first PMOS transistor Q2 is electrically connected to the I / O pin I / O2. Preferably, the resistance values ​​of the first voltage divider resistor R7 and the second voltage divider resistor R8 are equal.

[0040] The toner cartridge chip 5 also includes a first capacitor C2, and the power supply pin VCC2 is electrically connected to the ground pin GND2 through the first capacitor C2.

[0041] In this embodiment, the power supply pin VCC2 of the toner cartridge chip controller 52 is electrically connected to the first power terminal 511 through the second current-limiting resistor R6. This allows the toner cartridge chip controller 52 to be directly powered by the printer power supply, ensuring that only the toner cartridge chip 3 draws power from the first I / O terminal 513. Therefore, the requirements for the printer's I / O drive capability are reduced, improving the stability of the I / O terminal power supply. Simultaneously, the direct power supply circuit 54 includes a first NMOS transistor Q1, a first PMOS transistor Q2, a first voltage divider resistor R7, and a second voltage divider resistor R8. When the first I / O terminal 513 outputs a high level, the first NMOS transistor is turned on. The voltage at the first power terminal 511 is divided by the first voltage divider resistor R7 and the second voltage divider resistor R8. If the voltage difference between the divided voltage and the voltage at the first I / O terminal 513 when it is high is greater than the voltage at the turn-on voltage... When the voltage VGS is reduced (for example, when the voltage of the first power supply terminal 511 is 3.3V and the high level on the first I / O terminal 513 drops to 2.5V~3.0V, the gate voltage of the first PMOS transistor Q2 is about 1.6V after voltage division, and at this time the VGS of the first PMOS transistor Q2 is -0.9V~-1.4V), then the first PMOS transistor Q2 is turned on, and the first power supply terminal 511 supplies power to the I / O pin I / O2. At this time, the first power supply terminal 511 will pull the high level of the first I / O terminal 513 back to about the voltage of the first power supply terminal 511. When the first I / O terminal 513 outputs a low level, the first NMOS transistor Q1 is turned off. Since the gate and source of the first PMOS transistor Q2 are both at a low level, it will not be turned on, and the voltage of the first power supply terminal 511 will not affect the voltage on the I / O pin I / O2.

[0042] Third embodiment of toner cartridge chip:

[0043] like Figure 4 As shown, in this embodiment, the toner cartridge chip 6 includes a printer interface 61, a toner cartridge chip controller 62, and a toner cartridge interface 63. The printer interface 61 is used to connect to the printer control circuit 1, and the toner cartridge interface 63 is used to connect to the toner cartridge chip 3.

[0044] The printer interface 61 includes a first power terminal 611, a first test terminal 612, a first I / O terminal 613, and a first ground terminal 614. The toner cartridge chip controller 62 includes a power pin VCC3, an I / O pin I / O3, and a ground pin GND3. The toner cartridge interface 63 includes a second test terminal 631, a second I / O terminal 632, and a second ground terminal 633. The first test terminal 612 and the second test terminal 631 are electrically connected. The first I / O terminal 613, the I / O pin I / O3, and the second I / O terminal 632 are electrically connected to each other. The first I / O terminal 613 is electrically connected to the power pin VCC3 through a diode D1. The positive terminal of the diode D1 is electrically connected to the first I / O terminal 613, and the negative terminal of the diode D1 is electrically connected to the power pin VCC3. The first ground terminal 614, the ground pin GND3, and the second ground terminal 633 are electrically connected to each other.

[0045] The toner cartridge chip 6 also includes a direct power supply circuit 64, which obtains power from the first power terminal 611 of the printer interface 61 and supplies power to the first I / O terminal 613. In this embodiment, the direct power supply circuit 64 includes a third current-limiting resistor R9, the first end of which is electrically connected to the first power terminal 611, and the second end of which is electrically connected to the first I / O terminal 613.

[0046] The toner cartridge chip also includes a first capacitor C3, and the power supply pin VCC3 is electrically connected to the ground pin GND3 through the first capacitor C3.

[0047] In this embodiment, the toner cartridge chip 6 connects the first power terminal 611 to the first I / O terminal 613 through the third current-limiting resistor R9, which indirectly increases the driving capability of the first I / O terminal 613 and plays the role of auxiliary power supply. In this way, even if the toner cartridge chip controller 62 and the toner cartridge chip 3 simultaneously obtain power from the first I / O terminal 613, it is difficult to lower the data level on the first I / O terminal 613, thereby improving the power supply stability of the I / O terminal.

[0048] Fourth embodiment of toner cartridge chip:

[0049] like Figure 5 As shown, in this embodiment, the toner cartridge chip 7 includes a printer interface 71, a toner cartridge chip controller 72, and a toner cartridge interface 73. The printer interface 71 is used to connect to the printer control circuit 1, and the toner cartridge interface 73 is used to connect to the toner cartridge chip 3.

[0050] The printer interface 71 includes a first test terminal 711, a first I / O terminal 712, and a first ground terminal 713. The toner cartridge chip controller 72 includes a power supply pin VCC4, an I / O pin I / O4, and a ground pin GND4. The toner cartridge interface 73 includes a second test terminal 731, a second I / O terminal 732, and a second ground terminal 733. The first test terminal 711 and the second test terminal 731 are electrically connected. The first I / O terminal 712, the I / O pin I / O4, and the second I / O terminal 732 are electrically connected to each other. The first I / O terminal 712 is electrically connected to the power supply pin VCC4 through a diode D2. The positive terminal of the diode D2 is electrically connected to the first I / O terminal 712, and the negative terminal of the diode D2 is electrically connected to the power supply pin VCC4. The first ground terminal 713, the ground pin GND4, and the second ground terminal 733 are electrically connected to each other.

[0051] The toner cartridge chip 7 also includes an auxiliary power supply circuit 74, which obtains power from the first test terminal 711 of the printer interface 71 and supplies power to the first I / O terminal 712. In this embodiment, the auxiliary power supply circuit 74 includes a fourth current-limiting resistor R10, the first end of which is electrically connected to the first test terminal 711, and the second end of which is electrically connected to the first I / O terminal 712.

[0052] The toner cartridge chip 7 also includes a first capacitor C4, and the power supply pin VCC4 is electrically connected to the ground pin GND4 through the first capacitor C4.

[0053] In this embodiment, the drum chip 7 electrically connects the first test terminal 711 to the first I / O terminal 712 through the fourth current-limiting resistor R10. By adjusting the resistance value of the fourth current-limiting resistor R10, the test terminal 711 is kept within the acceptable voltage error range of the printer, while the driving capability of the first I / O terminal 712 is increased. This allows the first I / O terminal 712 to be powered by the first test terminal 711. Thus, even if the drum chip controller 72 and the toner cartridge chip 3 simultaneously draw power from the first I / O terminal 712, it is difficult to lower the data level on the first I / O terminal 712, thereby improving the power supply stability of the I / O terminal. When certain printer models, due to product updates or firmware upgrades, remove the power terminal VCC connected to the printer interface 71 or the power terminal VCC no longer outputs power, the drum chip 7 provided in this embodiment can still improve the power supply stability of the I / O terminal.

[0054] Fifth embodiment of toner cartridge chip:

[0055] like Figure 6As shown, in this embodiment, the toner cartridge chip 8 includes a printer interface 81, a toner cartridge chip controller 82, and a toner cartridge interface 83. The printer interface 81 is used to connect to the printer control circuit 1, and the toner cartridge interface 83 is used to connect to the toner cartridge chip 3.

[0056] The printer interface 81 includes a first test terminal 811, a first I / O terminal 812, and a first ground terminal 813. The toner cartridge chip controller 82 includes a power supply pin VCC5, an I / O pin I / O5, and a ground pin GND5. The toner cartridge interface 83 includes a second test terminal 831, a second I / O terminal 832, and a second ground terminal 833. The first test terminal 811 and the second test terminal 831 are electrically connected. The first I / O terminal 812, the I / O pin I / O5, and the second I / O terminal 832 are electrically connected to each other. The first I / O terminal 812 is electrically connected to the power supply pin VCC5 through a diode D3. The positive terminal of the diode D3 is electrically connected to the first I / O terminal 812, and the negative terminal of the diode D3 is electrically connected to the power supply pin VCC5. The first ground terminal 813, the ground pin GND5, and the second ground terminal 833 are electrically connected to each other.

[0057] The toner cartridge chip 8 also includes an auxiliary power supply circuit 84, which is used to obtain power from the first test terminal 811 of the printer interface 81 and to supply power to the first I / O terminal 812.

[0058] In this embodiment, the auxiliary power supply circuit 84 includes a fifth current-limiting resistor R11, a second NMOS transistor Q3, a second PMOS transistor Q4, a third voltage-dividing resistor R12, and a fourth voltage-dividing resistor R13. The gate of the second NMOS transistor Q3 is electrically connected to the first I / O terminal 812, the drain of the second NMOS transistor Q3 is electrically connected to the second end of the fifth current-limiting resistor R11, the source of the second NMOS transistor Q3 is electrically connected to the first end of the third voltage-dividing resistor R12, the second end of the third voltage-dividing resistor R12 is electrically connected to the first end of the fourth voltage-dividing resistor R13, and the second end of the fourth voltage-dividing resistor R13 is electrically connected to the ground pin GND5. The gate of the second PMOS transistor Q4 is electrically connected to the second end of the third voltage-dividing resistor R12, the drain of the second PMOS transistor Q4 is electrically connected to the second end of the fifth current-limiting resistor R11, and the source of the second PMOS transistor Q4 is electrically connected to the I / O pin I / O5. The resistance values ​​of the third voltage-dividing resistor R12 and the fourth voltage-dividing resistor R13 are equal.

[0059] The toner cartridge chip also includes a first capacitor C5, and the power supply pin VCC5 is electrically connected to the ground pin GND5 through the first capacitor C5.

[0060] In this embodiment, the toner cartridge chip is electrically connected to the first test terminal 811 and the first I / O terminal 812 via a fifth current-limiting resistor R11, a second NMOS transistor Q3, a second PMOS transistor Q4, a third voltage divider resistor R12, and a fourth voltage divider resistor R13. When the first I / O terminal 812 outputs a high level, the second NMOS transistor Q3 is turned on. The voltage at the first test terminal 811 is divided by the third voltage divider resistor R12 and the fourth voltage divider resistor R13. If the divided voltage is the same as the high level at the first I / O terminal 812... When the voltage difference is greater than the turn-on voltage VGS, the second PMOS transistor Q4 turns on, and the first test terminal 811 supplies power to the I / O pin I / O5, thereby pulling the high level on the I / O pin I / O5 back to around the voltage of the first test terminal 811. When the first I / O terminal 812 outputs a low level, the second NMOS transistor Q3 turns off. Since the gate and source of the second PMOS transistor Q4 are both at a low level, it will not turn on, and the voltage of the first test terminal 811 will not affect the voltage on the I / O pin I / O5.

[0061] Toner cartridge example:

[0062] In this embodiment, the toner cartridge is equipped with a toner cartridge chip, and the toner cartridge chip is any of the toner cartridge chips in the first to fifth embodiments described above.

[0063] Printer Example:

[0064] In this embodiment, the printer includes a printer control circuit and a toner cartridge, which is the same as the toner cartridge in the above embodiment; the printer control circuit is electrically connected to the printer interface, and the printer control circuit interacts with the toner cartridge chip and the toner cartridge chip circuit.

[0065] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept also fall within the protection scope of the present invention.

Claims

1. A toner cartridge chip, comprising a printer interface, a toner cartridge chip controller, and a toner cartridge interface, wherein the printer interface includes a first power terminal, a first test terminal, a first I / O terminal, and a first ground terminal; the toner cartridge chip controller includes a power pin, an I / O pin, and a ground pin; the toner cartridge interface includes a second test terminal, a second I / O terminal, and a second ground terminal; the first test terminal and the second test terminal are electrically connected; the first I / O terminal, the I / O pin, and the second I / O terminal are electrically connected to each other; and the first ground terminal, the ground pin, and the second ground terminal are electrically connected to each other; characterized in that: The toner cartridge chip also includes a direct power supply circuit for obtaining power from the first power terminal of the printer interface or an auxiliary power supply circuit for obtaining power from the first test terminal. The direct power supply circuit supplies power to the power pin and / or the first I / O terminal, or the auxiliary power supply circuit supplies power to the first I / O terminal; The direct power supply circuit includes a first current-limiting resistor; or the direct power supply circuit includes a first NMOS transistor, a first PMOS transistor, a first voltage divider resistor, a second voltage divider resistor, and a second current-limiting resistor; or the direct power supply circuit includes a third current-limiting resistor. The auxiliary power supply circuit includes a fourth current-limiting resistor; or the auxiliary power supply circuit includes a second NMOS transistor, a second PMOS transistor, a third voltage divider resistor, a fourth voltage divider resistor, and a fifth current-limiting resistor.

2. The toner cartridge chip according to claim 1, characterized in that: When the direct power supply circuit includes a first current-limiting resistor, the first end of the first current-limiting resistor is electrically connected to the first power supply terminal, and the second end of the first current-limiting resistor is electrically connected to the power supply pin.

3. The toner cartridge chip according to claim 1, characterized in that: When the direct power supply circuit includes a first NMOS transistor, a first PMOS transistor, a first voltage divider resistor, a second voltage divider resistor, and a second current-limiting resistor, the first end of the second current-limiting resistor is electrically connected to the first power supply terminal, the second end of the second current-limiting resistor is electrically connected to the power supply pin, the gate of the first NMOS transistor is electrically connected to the first I / O terminal, the drain of the first NMOS transistor is electrically connected to the second end of the second current-limiting resistor, the source of the first NMOS transistor is electrically connected to the first end of the first voltage divider resistor, the second end of the first voltage divider resistor is electrically connected to the first end of the second voltage divider resistor, the second end of the second voltage divider resistor is electrically connected to the ground pin, the gate of the first PMOS transistor is electrically connected to the second end of the first voltage divider resistor, the drain of the first PMOS transistor is electrically connected to the second end of the second current-limiting resistor, and the source of the first PMOS transistor is electrically connected to the I / O pin.

4. The toner cartridge chip according to claim 3, characterized in that: The resistance values ​​of the first voltage divider resistor and the second voltage divider resistor are equal.

5. The toner cartridge chip according to claim 1, characterized in that: When the direct power supply circuit includes a third current-limiting resistor, the first end of the third current-limiting resistor is electrically connected to the first power supply terminal, and the second end of the third current-limiting resistor is electrically connected to the first I / O terminal.

6. The toner cartridge chip according to claim 1, characterized in that: When the auxiliary power supply circuit includes a fourth current-limiting resistor, the first end of the fourth current-limiting resistor is electrically connected to the first test terminal, and the second end of the fourth current-limiting resistor is electrically connected to the first I / O terminal.

7. The toner cartridge chip according to claim 1, characterized in that: When the auxiliary power supply circuit includes a second NMOS transistor, a second PMOS transistor, a third voltage divider resistor, a fourth voltage divider resistor, and a fifth current-limiting resistor, the first end of the fifth current-limiting resistor is electrically connected to the first test terminal; the gate of the second NMOS transistor is electrically connected to the first I / O terminal; the drain of the second NMOS transistor is electrically connected to the second end of the fifth current-limiting resistor; the source of the second NMOS transistor is electrically connected to the first end of the third voltage divider resistor; the second end of the third voltage divider resistor is electrically connected to the first end of the fourth voltage divider resistor; the second end of the fourth voltage divider resistor is electrically connected to the ground pin; the gate of the second PMOS transistor is electrically connected to the second end of the third voltage divider resistor; the drain of the second PMOS transistor is electrically connected to the second end of the fifth current-limiting resistor; and the source of the second PMOS transistor is electrically connected to the I / O pin.

8. The toner cartridge chip according to claim 7, characterized in that: The resistance values ​​of the third voltage divider resistor and the fourth voltage divider resistor are equal.

9. A toner cartridge, wherein the toner cartridge is provided with a toner cartridge chip, characterized in that: The toner cartridge chip is the toner cartridge chip according to any one of claims 1 to 8.

10. A printer, comprising a printer control circuit and a toner cartridge, characterized in that: The toner cartridge is the toner cartridge according to claim 9; The printer control circuit is electrically connected to the printer interface.

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