Pixel compensation circuit and display panel

Abstract

The present application discloses a pixel compensation circuit and a display panel. The pixel compensation circuit includes a driving transistor, a compensation module, a first writing module, a second writing module, a light-emitting module, a first capacitor and a second capacitor. The compensation module is connected to the second global signal and is connected to the first node and the first gate of the driving transistor; the first writing module is connected to the third global signal, the first initialization signal, the fourth global signal and the second initialization signal, and is connected to the second node and the first gate of the driving transistor; the light-emitting module is connected to the first global signal and is connected in series between the second power supply terminal and the first node. The present application only requires one set of row scanning level transmission signals to achieve internal compensation, thereby improving the display uniformity of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel compensation circuit and a display panel. Background Art

[0002] In existing pixel compensation circuits, current driving is often used to drive the light emitting device to emit light. However, the above driving method is sensitive to the electrical variation of the driving transistor, and the threshold voltage drift of the driving transistor will affect the brightness uniformity of the screen display.

[0003] There are two mainstream threshold voltage compensation methods, external compensation and internal compensation. External compensation has a wide compensation range for the threshold voltage of the driving transistor, but the driving system is complex and costly. The internal compensation driving system is relatively simple and low-cost, but internal compensation requires multiple sets of row scanning level transmission signals. Summary of the invention

[0004] The present application provides a pixel compensation circuit and a display panel to solve the technical problem in the prior art that an internal compensation circuit requires multiple sets of row scanning stages to transmit signals.

[0005] The present application provides a pixel compensation circuit, which includes:

[0006] a driving transistor, wherein a source of the driving transistor is connected to the first power supply terminal, and a drain of the driving transistor is connected to the first node;

[0007] A light emitting module, comprising a first control end, a first end and a second end; the first control end is connected to a first signal line, the first end is connected to a second power supply end, the second end is connected to the first node, and the light emitting module is used to emit light under the control of a first global signal transmitted by the first signal line;

[0008] a compensation module, comprising a second control terminal, a third terminal and a fourth terminal, wherein the second control terminal is connected to the second signal line, the third terminal is connected to the first node, and the fourth terminal is connected to the first gate of the driving transistor, and the compensation module is used to compensate the threshold voltage of the driving transistor under the control of the second global signal transmitted by the second signal line;

[0009] A first writing module, comprising a third control end, a fourth control end, a first input end, a second input end, a first output end and a second output end, wherein the third control end is connected to a third signal line, the first input end is connected to a first routing line, the fourth control end is connected to a fourth signal line, the second input end is connected to a second routing line, the first output end is connected to a second node, and the second output end is connected to a first gate of the driving transistor; the first writing module is used to output a first initialization signal transmitted by the first routing line to the second node under the control of a third global signal transmitted by the third signal line, and to output a second initialization signal transmitted by the second routing line to the first gate of the driving transistor under the control of a fourth global signal transmitted by the fourth signal line;

[0010] a second writing module, comprising a fifth control terminal, a third input terminal and a third output terminal, wherein the fifth control terminal is connected to the scan line, the third input terminal is connected to the data line, the third output terminal is connected to the second node, and the second writing module is used for outputting the data signal transmitted by the data line to the second node under the control of the scan signal transmitted by the scan line;

[0011] a first capacitor, one end of the first capacitor being connected to the second node, and the other end of the first capacitor being connected to the first gate of the driving transistor; and

[0012] A second capacitor, one end of the second capacitor is connected to the first gate of the driving transistor, and the other end of the second capacitor is connected to the first power supply end.

[0013] Optionally, in some embodiments of the present application, the first writing module includes a first transistor and a second transistor;

[0014] Among them, the gate of the first transistor is connected to the third signal line, the source of the first transistor is connected to the first routing line, and the drain of the first transistor is connected to the second node; the gate of the second transistor is connected to the fourth signal line, the source of the second transistor is connected to the second routing line, and the drain of the second transistor is connected to the first gate of the driving transistor.

[0015] Optionally, in some embodiments of the present application, the first initialization signal is a signal connected to the first power supply terminal, and the second initialization signal is a signal connected to the second power supply terminal.

[0016] Optionally, in some embodiments of the present application, the first initialization signal and the data signal are both output by the corresponding data lines, and the second initialization signal is a signal connected to the second power supply terminal.

[0017] Optionally, in some embodiments of the present application, the first initialization signal is independent of a signal connected to the first power supply terminal, and the second initialization signal is independent of a signal connected to the second power supply terminal.

[0018] Optionally, in some embodiments of the present application, the voltage value of the first initialization signal is less than the voltage value of the data signal.

[0019] Optionally, in some embodiments of the present application, the driving transistor is a dual-gate transistor, and the second gate of the driving transistor is connected to a third signal line to access an adjustment signal.

[0020] Optionally, in some embodiments of the present application, the compensation module includes a compensation transistor;

[0021] The gate of the compensation transistor is connected to the second signal line, the source of the compensation transistor is connected to the first gate of the driving transistor, and the drain of the compensation transistor is connected to the first node.

[0022] Optionally, in some embodiments of the present application, the light emitting module includes a switching transistor and a light emitting device;

[0023] The gate of the switch transistor is connected to the first signal line, the source of the switch transistor is connected to the second power supply terminal, the drain of the switch transistor is connected to the anode of the light emitting device, and the cathode of the light emitting device is connected to the first node;

[0024] Alternatively, the gate of the switching transistor is connected to the first signal line, the source of the switching transistor is connected to the cathode of the light-emitting device, the drain of the switching transistor is connected to the first node, and the anode of the light-emitting device is connected to the second power supply terminal.

[0025] Correspondingly, the present application also provides a display panel, which includes a plurality of pixel units arranged in an array, and each of the pixel units includes any one of the pixel compensation circuits described above.

[0026] The present application provides a pixel compensation circuit and a display panel. The pixel compensation circuit includes a driving transistor, a compensation module, a first writing module, a second writing module, a light-emitting module, a first capacitor, and a second capacitor. The pixel compensation circuit provided in the present application can internally compensate for the threshold voltage drift of the driving transistor by setting the compensation module, thereby improving the brightness uniformity of the display panel. In addition, in the pixel compensation circuit, the second global signal, the third global signal, the fourth global signal, and the first global signal are used to respectively control the compensation module, the first writing module, and the light-emitting module, thereby reducing the number of line-by-line scanning signals to one, and the circuit structure is simple, which is conducive to realizing a narrow frame of the display panel or reducing chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a structural schematic diagram of a pixel compensation circuit provided by the present application;

[0029] Figure 2 is a first circuit schematic diagram of a pixel compensation circuit provided by the present application;

[0030] Figure 3 yes Figure 2 The signal timing diagram of the pixel compensation circuit shown;

[0031] Figure 4 is a second circuit schematic diagram of the pixel compensation circuit provided by the present application;

[0032] Figure 5 is a third circuit schematic diagram of the pixel compensation circuit provided by the present application;

[0033] Figure 6 is a fourth circuit schematic diagram of the pixel compensation circuit provided by the present application;

[0034] Figure 7 yes Figure 6 The signal timing diagram of the pixel compensation circuit shown in

[0035] Figure 8 is a fifth circuit schematic diagram of the pixel compensation circuit provided by the present application;

[0036] Fig. 9 It is a structural schematic diagram of a display panel provided in this application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0038] In the description of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" etc. may explicitly or implicitly include one or more of the said features, and therefore cannot be understood as limitations on the present application. In addition, it should be noted that, unless otherwise clearly specified and defined, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0039] The present application provides a pixel compensation circuit and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.

[0040] See also Figure 1 , Figure 1 In the embodiment of the present application, the pixel compensation circuit 10 includes a driving transistor Td, a compensation module 102, a first writing module 104, a second writing module 101, a light emitting module 103, a first capacitor C1 and a second capacitor Cst.

[0041] The source of the driving transistor Td is connected to the first power supply terminal VSS, and the drain of the driving transistor Td is connected to the first node P.

[0042] The light emitting module 103 includes a first control terminal a, a first terminal b and a second terminal c. The first control terminal a is connected to the first signal line 21 to access the first global signal EM. The first terminal b is connected to the second power supply terminal VDD. The second terminal c is connected to the first node P. The light emitting module 103 is used to emit light under the control of the first global signal EM.

[0043] The compensation module 102 includes a second control terminal d, a third terminal e and a fourth terminal f. The second control terminal d is connected to the second signal line 22 to access the second global signal Comp. The third terminal e is connected to the first node P. The fourth terminal f is connected to the first gate of the driving transistor Td. The compensation module 102 is used to compensate the threshold voltage of the driving transistor Td under the control of the second global signal Comp.

[0044] The first writing module 104 includes a third control terminal g, a fourth control terminal h, a first input terminal i, a second input terminal j, a first output terminal k and a second output terminal m. The third control terminal g is connected to the third signal line 23 to access the third global signal Ctr. The first input terminal i is connected to the first wiring 25 to access the first initialization signal V1. The fourth control terminal h is connected to the fourth signal line 24 to access the fourth global signal Res. The second input terminal j is connected to the second wiring 26 to access the second initialization signal V2. The first output terminal k is connected to the second node Q. The second output terminal m is connected to the first gate of the driving transistor Td. The first writing module 104 is used to output the first initialization signal V1 to the second node Q under the control of the third global signal Ctr, and output the fourth global signal Res to the first gate of the driving transistor Td under the control of the fourth global signal Res.

[0045] The second writing module 101 includes a fifth control terminal r, a third input terminal s and a third output terminal t. The fifth control terminal r is connected to the scanning line 27 to receive the scanning signal SPAM. The third input terminal s is connected to the data line 28 to receive the data signal Da. The third output terminal t is connected to the second node Q. The second writing module 101 is used to output the data signal Da to the second node Q under the control of the scanning signal SPAM.

[0046] One end of the first capacitor C1 is connected to the second node Q. The other end of the first capacitor C1 is connected to the first gate of the driving transistor Td.

[0047] One end of the second capacitor Cst is connected to the first gate of the driving transistor Td, and the other end of the second capacitor Cst is connected to the first power supply terminal VSS.

[0048] The embodiment of the present application can compensate for the threshold voltage drift of the driving transistor Td and improve the brightness uniformity of the display panel by setting the compensation module 102 in the pixel compensation circuit 10. In addition, the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the first global signal EM are used in the pixel compensation circuit 10 to respectively control the compensation module 102, the first writing module 104 and the light-emitting module 103, so that multiple pixel compensation circuits 10 in the display panel can simultaneously perform reset, threshold voltage compensation, data writing and other steps, thereby reducing the number of line-by-line scanning signals to one, that is, only the scanning signal SPAM is a multi-stage transmission signal, and the circuit structure is simple.

[0049] Specifically, when the level transfer scanning signal is generated by the GOA circuit, the pixel compensation circuit 10 in the embodiment of the present application only needs one set of GOA circuits, and the circuit structure is simple, which is conducive to realizing the narrow frame of the display panel. When the level transfer scanning signal is generated by the chip, the internal circuit structure of the chip can be simplified and the power consumption of the chip can be reduced.

[0050] In the embodiment of the present application, the first power supply terminal VSS and the second power supply terminal VDD are both used to access a preset voltage signal. In addition, in the embodiment of the present application, the potential of the signal accessed by the first power supply terminal VSS is less than the potential of the signal accessed by the second power supply terminal VDD. Specifically, the potential of the signal accessed by the first power supply terminal VSS can be the potential of the ground terminal. Of course, it can be understood that the potential of the signal accessed by the first power supply terminal VSS can also be other.

[0051] In the embodiments of this application, please refer to Figure 2 , Figure 2 This is a first circuit diagram of the pixel compensation circuit provided in the present application. Figure 1 and Figure 2 As shown, the first writing module 104 includes a first transistor T1 and a second transistor T2.

[0052] The gate of the first transistor T1 is connected to the third signal line 23 to access the third global signal Ctr. The source of the first transistor T1 is connected to the first wiring 25 to access the first initialization signal V1. The drain of the first transistor T1 is connected to the second node Q. The gate of the second transistor T2 is connected to the fourth signal line 24 to access the fourth global signal Res. The source of the second transistor T2 is connected to the second wiring 26 to access the second initialization signal V2. The drain of the second transistor T2 is connected to the first gate of the driving transistor Td.

[0053] The compensation module 102 includes a compensation transistor T4. The gate of the compensation transistor T4 is connected to the second signal line 22 to receive the second global signal Comp. The source of the compensation transistor T4 is connected to the first gate of the driving transistor Td. The drain of the compensation transistor T4 is connected to the drain of the driving transistor Td.

[0054] The second writing module 101 includes a third transistor T3. The gate of the third transistor T3 is connected to the scanning line 27 to receive the scanning signal SPAM. The source of the third transistor T3 is connected to the data line 28 to receive the data signal Da. The drain of the third transistor T3 is connected to the second node Q. Of course, it can be understood that the second writing module 101 can also be formed by connecting multiple transistors in series.

[0055] The light emitting module 103 includes a switching transistor T5 and a light emitting device D. The gate of the switching transistor T5 is connected to the first signal line 21 to access the first global signal EM. The source of the switching transistor T5 is connected to the second power supply terminal VDD. The drain of the switching transistor T5 is connected to the anode of the light emitting device D. The cathode of the light emitting device D is connected to the drain of the driving transistor Td.

[0056] Of course, it can be understood that in the pixel compensation circuit 10 provided in the embodiment of the present application, the light emitting module 103 may include 2, 3, 4 or more transistors. Each transistor is connected in series between the first power supply terminal VSS and the second power supply terminal VDD. Multiple transistors can be connected to the same first global signal EM, or to different light emitting control signals.

[0057] It should be noted that the transistors used in all embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the accompanying drawings, the middle end of the switching transistor is specified as the gate, the signal input end is the source, and the output end is the drain. In addition, the transistors used in the embodiments of the present application may include P-type transistors and / or N-type transistors, wherein the P-type transistor is turned on when the gate is low and turned off when the gate is high, and the N-type transistor is turned on when the gate is high and turned off when the gate is low.

[0058] In addition, the following embodiments of the present application are described by taking the transistors in the pixel compensation circuit 10 as N-type transistors as an example, but this should not be construed as a limitation on the present application.

[0059] See also Figure 3 , Figure 3 yes Figure 2The signal timing diagram of the pixel compensation circuit shown in FIG. Figure 2 and Figure 3 , the second global signal Comp, the third global signal Ctr, the fourth global signal Res, the first global signal EM and the scanning signal SPAM are combined to correspond to the reset stage t1, the threshold voltage compensation stage t2, the data writing stage t3 and the light emitting stage t4. That is, within one frame time, the driving control timing of the pixel compensation circuit 10 provided in the embodiment of the present application includes the reset stage t1, the threshold voltage compensation stage t2, the data writing stage t3 and the light emitting stage t4.

[0060] In the reset phase t1, the third global signal Ctr and the fourth global signal Res are both at high potentials, the second global signal Comp, the first global signal EM and the scanning signal SPAM are all at low potentials, at this time, the first transistor T1 and the second transistor T2 are turned on, the third transistor T3, the compensation transistor T4 and the switch transistor T5 are all turned off, and the first initialization signal V1 is output to the second node Q through the first transistor T1. The second initialization signal V2 is output to the first gate of the driving transistor Td through the second transistor T2. The potential of the second node Q is reset to the potential of the first initialization signal V1. The potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2.

[0061] In some embodiments, in the reset phase, the timing of the third global signal Ctr precedes the timing of the fourth global signal Res, that is, the third global signal Ctr is first at a high level, and after a period of time, the fourth global signal Res changes from a low level to a high level.

[0062] It can be understood that the third global signal Ctr first changes from a low potential to a high potential, the first transistor T1 is turned on first, and the potential of the second node Q is reset to the potential of the first initialization signal V1. Then, when the fourth global signal Res changes from a low potential to a high potential, the potential of the first gate of the driving transistor Td is reset to the potential of the second initialization signal V2, and since the first transistor T1 is continuously turned on, the potential of the second node Q can be stabilized at the potential of the first initialization signal V1, so as to avoid the potential of the first gate of the driving transistor Td being coupled to the second node Q through the first capacitor C1, thereby avoiding affecting the subsequent threshold voltage compensation.

[0063] In the threshold voltage compensation stage t2, the third global signal Ctr and the second global signal Comp are both at high potential, the fourth global signal Res, the first global signal EM and the scanning signal SPAM are all at low potential, at this time, the second transistor T2, the third transistor T3 and the switch transistor T5 are all turned off, the first transistor T1 remains turned on to stabilize the potential of the second node Q at the potential of the first initialization signal V1, the compensation transistor T4 and the driving transistor Td are turned on, the potential of the first gate of the driving transistor Td begins to leak through the compensation transistor T4, the driving transistor Td and the first power supply terminal VSS until the driving transistor Td is turned off, at this time the potential of the first gate of the driving transistor Td is Vss+Vth. Wherein, Vth is the threshold voltage of the driving transistor Td, and Vss represents the potential of the signal connected to the first power supply terminal VSS.

[0064] It is understandable that the driving transistor Td is in an open state under the driving of the second initialization signal V2. Therefore, the voltage value of the second initialization signal V2 needs to be greater than the sum of the voltage value of the signal connected to the first power supply terminal VSS and the threshold voltage of the driving transistor Td.

[0065] In the data writing phase t3, the scanning signal SPAM is at a high potential, the third transistor T3 is turned on, and the data signal Da is written to the first gate of the driving transistor Td through the third transistor T3 and the first capacitor C1. At this time, the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the first global signal EM are all at a low potential, and the first transistor T1, the second transistor T2, the compensation transistor T4 and the switch transistor T5 are all turned off. The driving transistor Td is turned on by the voltage written to the first gate of the driving transistor Td.

[0066] The voltage Vg written into the first gate of the driving transistor Td is Vss+Vth+(Da-V1)*C1 / (C1+Cst).

[0067] It should be noted that in the reset stage t1 and the threshold voltage compensation stage t2, since the second global signal Comp, the third global signal Ctr, the fourth global signal Res, and the first global signal EM used by the pixel compensation circuit 10 are all global signals, all pixel compensation circuits 10 in the display panel are reset and threshold voltage compensated at the same time. In the embodiment of the present application, only the scanning signal SPAM is a cascade signal and needs to be output by a group of GOA circuits. In the data writing stage t3, multiple rows of scanning signals SPAM (for example, SPAM1, SPAM2, SPAM(n)) are output in sequence, and the data signal Da is written into the corresponding pixel compensation circuit 10 row by row.

[0068] In the light-emitting stage t4, the first global signal EM is at a high potential, the second global signal Comp, the third global signal Ctr, the fourth global signal Res and the scanning signal SPAM are all at low potentials, at this time, the switch transistor T5 is turned on, the first transistor T1, the second transistor T2, the third transistor T3 and the compensation transistor T4 are all turned off, the second power supply terminal VDD, the light-emitting device D, the switch transistor T5, the driving transistor Td and the first power supply terminal VSS form a path, and the driving transistor Td generates a driving current corresponding to the data signal Da through the potential of the first gate. The driving current flows through the light-emitting device D, driving the light-emitting device D to emit light. Since the first global signal EM is a global signal, all the light-emitting devices D in the display panel emit light at the same time, thereby displaying a frame of picture.

[0069] In the light-emitting stage t4, the gate-source voltage difference of the driving transistor Td is Vgs=Vss+Vth+(Da-V1)*C1 / (C1+Cst)-Vss=Vth+(Da-V1)*C1 / (C1+Cst). Since the driving transistor Td operates in the saturation region, the current flowing through the light-emitting device D is I=k(Vgs-Vth) 2 =k[(Da-V1)*C1 / (C1+Cst)] 2 , where k represents mobility. Therefore, the current flowing through the light-emitting device D is independent of the threshold voltage Vth of the driving transistor Td, thereby ensuring that the current flowing through the light-emitting device D remains unchanged. Even if the threshold voltage Vth of the driving transistor Td drifts, it does not affect the normal light emission of the light-emitting device D, thereby improving the light emission uniformity of the display panel.

[0070] Theoretically, the pixel compensation circuit 10 provided in the embodiment of the present application can maintain the current variation of the threshold voltage offset ΔVth of the driving transistor Td within 5% within the range of 0-nV, wherein the value of n depends on the voltage values ​​of the data voltage Da, the first initialization signal V1 and the like.

[0071] In addition, it can be known from the calculation formula of the current flowing through the light emitting device D that the voltage value of the first initialization signal V1 needs to be smaller than the voltage value of the data signal Da, so as to ensure that the light emitting device D emits light normally.

[0072] Please continue reading Figure 2 In the embodiment of the present application, the first initialization signal V1 is a signal connected to the first power supply terminal VSS. The second initialization signal V2 is a signal connected to the second power supply terminal VDD. At this time, the voltage Vg written to the first gate of the driving transistor Td is Vss+Vth+(Da-Vss)*C1 / (C1+Cst). The current I flowing through the light-emitting device D is k(Vgs-Vth) 2 =k[(Da-Vss)*C1 / (C1+Cst)]2 , which is also independent of the threshold voltage Vth of the driving transistor Td.

[0073] In the embodiment of the present application, the first initialization signal V1 and the signal connected to the first power supply terminal VSS are set to be the same signal, and the second initialization signal V2 and the signal connected to the second power supply terminal VDD are set to be the same signal, so as to reduce the signals required by the pixel compensation circuit 10 and simplify the circuit arrangement.

[0074] See also Figure 4 , Figure 4 is a second circuit diagram of the pixel compensation circuit provided by the present application. Figure 2 The difference of the pixel compensation circuit 10 shown is that, in the light-emitting module 103 of the embodiment of the present application, the gate of the switching transistor T5 is connected to the first signal line 21 to access the first global signal EM; the source of the switching transistor T5 is connected to the cathode of the light-emitting device D; the drain of the switching transistor T5 is connected to the drain of the driving transistor Td; and the anode of the light-emitting device D is connected to the second power supply terminal VDD.

[0075] It should be noted that the signal driving timing of the pixel compensation circuit 10 in this embodiment is similar to Figure 2 The signal driving timing of the pixel compensation circuit 10 shown is the same, and the details can be referred to the above embodiment, which will not be repeated here.

[0076] See also Figure 5 , Figure 5 is a third circuit diagram of the pixel compensation circuit provided by the present application. Figure 2 The difference of the pixel compensation circuit 10 shown is that, in the embodiment of the present application, the first initialization signal V1 is independent of the signal connected to the first power supply terminal VSS, and the second initialization signal V2 is independent of the signal connected to the second power supply terminal VDD.

[0077] The signal driving timing of the pixel compensation circuit 10 in this embodiment can also refer to the above embodiment, and will not be repeated here. At this time, the voltage Vg written into the first gate of the driving transistor Td is Vss+Vth+(Da-V1)*C1 / (C1+Cst). The current I flowing through the light emitting device D is k(Vgs-Vth) 2 =k[(Da-V1)*C1 / (C1+Cst)] 2 , which is also independent of the threshold voltage Vth of the driving transistor Td.

[0078] At the same time, since the first initialization signal V1 and the signal connected to the first power supply terminal VSS are independent of each other, the current flowing through the light-emitting device D is independent of the signal connected to the first power supply terminal VSS, which can reduce the impact of uneven display caused by IR drop (voltage drop) of the signal connected to the first power supply terminal VSS.

[0079] See also Figure 6 , Figure 6 is a fourth circuit diagram of the pixel compensation circuit provided by the present application. Figure 2 The difference of the pixel compensation circuit 10 shown is that, in the embodiment of the present application, the first initialization signal V1 and the data signal Da are both output by the corresponding data line 28, and the second initialization signal V2 and the signal connected to the second power supply terminal VDD are the same signal.

[0080] For details, please refer to Figure 7 , Figure 7 yes Figure 6 The signal timing diagram of the pixel compensation circuit 10 is shown. Figure 3 The difference between the signal timing diagram shown is that, in the embodiment of the present application, the data line outputs the data signal Da twice within one frame display period. The first time is in the reset phase t1, and the data signal Da output by the data line is the first initialization signal V1 to initialize the potential of the second node Q. The second time is in the data writing phase t3, and the data line outputs the data signal Da to the first gate of the driving transistor Td.

[0081] Similarly, the first initialization signal V1 output by the data line is independent of the signal connected to the first power supply terminal VSS, so the current flowing through the light-emitting device D is independent of the signal connected to the first power supply terminal VSS, which can reduce the impact of uneven display caused by IR drop (voltage drop) of the signal connected to the first power supply terminal VSS. In addition, the first initialization signal V1 output via the data line can further simplify the signal wiring within the plane.

[0082] See also Figure 8 , Figure 8 is a fifth circuit diagram of the pixel compensation circuit provided by the present application. Figure 2 The difference of the pixel compensation circuit 10 shown is that in the embodiment of the present application, the driving transistor Td is a dual-gate transistor. The second gate of the driving transistor Td is connected to the third signal line 29 to receive an adjustment signal BG.

[0083] Specifically, the adjustment signal BG is a DC signal. When the adjustment signal BG is a negative voltage, the threshold voltage Vth of the driving transistor Td can be adjusted in a positive direction. When the adjustment signal BG is a positive voltage, the threshold voltage Vth of the driving transistor Td can be adjusted in a negative direction.

[0084] The embodiment of the present application can also increase the compensation range of the threshold voltage Vth, so that the compensable range is shifted from 0 to nV to -mV to +pV, to achieve the compensation of the threshold voltage negative drift, thereby achieving the compensation of the threshold voltage Vth in the case of positive and negative drift. Among them, n, m, and p can be determined by the actual application of the driving transistor Td.

[0085] See also Fig. 9 , Fig. 9 A schematic diagram of a structure of a display panel provided in an embodiment of the present application. The embodiment of the present application also provides a display panel 100, comprising a plurality of pixel units 11 arranged in an array. Each pixel unit 11 comprises the pixel compensation circuit 10 described above, and the specifics can be referred to the above description of the pixel compensation circuit 10, which will not be described here.

[0086] In the embodiment of the present application, the display panel 100 can be an OLED (Organic Light-Emitting Diode, active matrix organic light-emitting diode) display panel, a Mini LED (Mini Light-Emitting Diode, mini light-emitting diode) display panel, a Micro LED (Micro Light-Emitting Diode, micron light-emitting diode) display panel, etc.

[0087] In the display panel 100 provided in the embodiment of the present application, the pixel compensation circuit 10 includes a driving transistor, a compensation module, a first writing module, a second writing module, a light emitting module, a first capacitor and a second capacitor. The pixel compensation circuit 10 provided in the embodiment of the present application can compensate for the threshold voltage difference of the driving transistor by setting the compensation module, thereby improving the brightness uniformity of the display panel 100. In addition, the second global signal, the third global signal, the fourth global signal and the first global signal are respectively used in the pixel compensation circuit 10 to control the compensation module, the first writing module and the light emitting module accordingly, and only one group of row scanning level transmission signals is required to realize internal compensation, and the circuit structure is simple, which is conducive to realizing the narrow frame of the display panel 100 or reducing the chip power consumption.

[0088] The pixel compensation circuit and display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A pixel compensation circuit, characterized in that: include: a driving transistor, wherein a source of the driving transistor is connected to the first power supply terminal, and a drain of the driving transistor is connected to the first node; A light emitting module, comprising a first control end, a first end and a second end; the first control end is connected to a first signal line, the first end is connected to a second power supply end, the second end is connected to the first node, and the light emitting module is used to emit light under the control of a first global signal transmitted by the first signal line; a compensation module, comprising a second control terminal, a third terminal and a fourth terminal, wherein the second control terminal is connected to the second signal line, the third terminal is connected to the first node, and the fourth terminal is connected to the first gate of the driving transistor, and the compensation module is used to compensate the threshold voltage of the driving transistor under the control of the second global signal transmitted by the second signal line; A first writing module, comprising a third control end, a fourth control end, a first input end, a second input end, a first output end and a second output end, wherein the third control end is connected to a third signal line, the first input end is connected to a first routing line, the fourth control end is connected to a fourth signal line, the second input end is connected to a second routing line, the first output end is connected to a second node, and the second output end is connected to a first gate of the driving transistor; the first writing module is used to output a first initialization signal transmitted by the first routing line to the second node under the control of a third global signal transmitted by the third signal line, and to output a second initialization signal transmitted by the second routing line to the first gate of the driving transistor under the control of a fourth global signal transmitted by the fourth signal line; a second writing module, comprising a fifth control terminal, a third input terminal and a third output terminal, wherein the fifth control terminal is connected to the scan line, the third input terminal is connected to the data line, the third output terminal is connected to the second node, and the second writing module is used for outputting the data signal transmitted by the data line to the second node under the control of the scan signal transmitted by the scan line; a first capacitor, one end of the first capacitor being connected to the second node, and the other end of the first capacitor being connected to the first gate of the driving transistor; as well as a second capacitor, one end of the second capacitor being connected to the first gate of the driving transistor, and the other end of the second capacitor being connected to the first power supply terminal; The driving control timing of the pixel compensation circuit includes a reset phase, a threshold voltage compensation phase, a data writing phase and a light emitting phase; In the reset phase, the third global signal and the fourth global signal are both at high potentials, and the second global signal, the first global signal and the scan signal are all at low potentials; In the threshold voltage compensation stage, the third global signal and the second global signal are both at high potentials, and the fourth global signal, the first global signal and the scanning signal are all at low potentials; In the data writing phase, the scanning signal is at a high potential, and the second global signal, the third global signal, the fourth global signal and the first global signal are all at a low potential; In the light emitting stage, the first global signal is at a high potential, and the second global signal, the third global signal, the fourth global signal and the scanning signal are all at a low potential.

2. The pixel compensation circuit according to claim 1, characterized in that: The first writing module includes a first transistor and a second transistor; Among them, the gate of the first transistor is connected to the third signal line, the source of the first transistor is connected to the first routing line, and the drain of the first transistor is connected to the second node; the gate of the second transistor is connected to the fourth signal line, the source of the second transistor is connected to the second routing line, and the drain of the second transistor is connected to the first gate of the driving transistor.

3. The pixel compensation circuit according to claim 1, characterized in that: The first initialization signal is a signal connected to the first power supply terminal, and the second initialization signal is a signal connected to the second power supply terminal.

4. The pixel compensation circuit according to claim 1, characterized in that: The first initialization signal and the data signal are both output by the corresponding data lines, and the second initialization signal is a signal connected to the second power supply terminal.

5. The pixel compensation circuit according to claim 1, characterized in that: The first initialization signal is independent of a signal connected to the first power supply terminal, and the second initialization signal is independent of a signal connected to the second power supply terminal.

6. The pixel compensation circuit according to any one of claims 1 to 5, characterized in that: A voltage value of the first initialization signal is smaller than a voltage value of the data signal.

7. The pixel compensation circuit according to claim 1, characterized in that: The driving transistor is a dual-gate transistor, and the second gate of the driving transistor is connected to the third signal line to receive an adjustment signal.

8. The pixel compensation circuit according to claim 1, characterized in that: The compensation module includes a compensation transistor; The gate of the compensation transistor is connected to the second signal line, the source of the compensation transistor is connected to the first gate of the driving transistor, and the drain of the compensation transistor is connected to the first node.

9. The pixel compensation circuit according to claim 1, characterized in that: The light emitting module comprises a switching transistor and a light emitting device; The gate of the switch transistor is connected to the first signal line, the source of the switch transistor is connected to the second power supply terminal, the drain of the switch transistor is connected to the anode of the light emitting device, and the cathode of the light emitting device is connected to the first node; Alternatively, the gate of the switching transistor is connected to the first signal line, the source of the switching transistor is connected to the cathode of the light-emitting device, the drain of the switching transistor is connected to the first node, and the anode of the light-emitting device is connected to the second power supply terminal.

10. A display panel, characterized in that: The display panel includes a plurality of pixel units arranged in an array, and each of the pixel units includes the pixel compensation circuit according to any one of claims 1 to 9.

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