A chip testing apparatus and method

Abstract

The application discloses a chip testing device and method, which is applied to the technical field of digital circuit design and comprises a chip testing seat provided with N slot positions, a switching circuit, a storage medium and an FPGA. The FPGA is used for receiving a first firmware and a first testing program issued by a host and storing the first firmware and the first testing program in the storage medium. When a first control command is received, the FPGA performs circuit control on the switching circuit, so that k to-be-tested chips specified by the first control command are sequentially connected to k chip firmware interfaces of the FPGA, and power supply control of the chip testing seat is performed, so that the k to-be-tested chips are powered on. When a reading instruction sent by any to-be-tested chip is received, the FPGA sends the first firmware and the first testing program to the to-be-tested chip. The host is used for recording a testing result when any to-be-tested chip performs testing on the first testing program. The scheme of the application can batch implement testing of to-be-tested chips, has a high flashing speed and is automatically completed, and therefore the testing efficiency is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and in particular to a chip testing apparatus and method. Background Technology

[0002] In the design and development of SoC (System on Chip), after the chip design and tape-out are completed, specific methods are needed to verify the basic functions of the chip. This allows for the rapid elimination of malfunctioning chips from the large number of SoC chips produced, and the selection of basically usable chips for delivery.

[0003] Currently, when testing SoC chips, the chip firmware and the test programs to be run are typically programmed manually or automatically to external storage media, such as QSPI (Quad Serial Peripheral Interface) FLASH or SD (Secure Digital) card. Then, the SoC chip under test is powered on manually or automatically. After the SoC chip powers on, the firmware is read from the QSPI FLASH or SD card to boot the SoC system, and then the test programs are read and executed. During the execution of the test programs, the host computer can observe and record the chip test results via serial port.

[0004] After testing one SoC chip, another SoC chip can be replaced manually or automatically to continue testing. If it is necessary to change the firmware and test program, the new firmware data and test program need to be written to external storage media, and the testing process needs to be repeated.

[0005] The current solution tests only one SoC chip at a time, requiring a replacement SoC chip after each test, making it unsuitable for large-scale testing and limiting it to sampling. Furthermore, testing different SoC chips often necessitates changing the firmware and test program. Currently, external QSPI FLASH or SD cards require specialized tools for programming, which is slow and prone to damage from repeated programming, impacting testing efficiency.

[0006] In conclusion, how to effectively conduct chip testing and improve testing efficiency is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] The purpose of this invention is to provide a chip testing apparatus and method to effectively perform chip testing and improve testing efficiency.

[0008] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0009] A chip testing apparatus, comprising:

[0010] A chip test socket with N slots is provided to hold up to N chips under test.

[0011] The switching circuit connected to the chip test socket;

[0012] Storage medium;

[0013] The FPGA connected to the storage medium is used to receive the first firmware and the first test program sent by the host and store them in the storage medium. When it receives the first control command sent by the host, it performs circuit control of the switching circuit so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and performs power supply control of the chip test socket so that the k chips under test specified by the first control command are powered on. When it receives a read command sent by any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the test of the first test program.

[0014] The host computer connected to the FPGA and the chip test socket is used to record the test results when any chip under test is tested by the first test program.

[0015] Where N is a positive integer not less than 2, and k is a positive integer and k≤N.

[0016] Preferably, the FPGA is provided with A types of chip firmware interfaces to support A types of interface protocols; A is a positive integer not less than 2;

[0017] When the FPGA performs circuit control of the switching circuit for any one of the k chips under test specified by the first control command, it is specifically used to: control the switching circuit so that the chip under test is connected to the chip firmware interface in the FPGA that matches the interface protocol of the chip under test.

[0018] Preferably, the FPGA is provided with at least an SPI interface and an SD card interface.

[0019] Preferably, the FPGA is specifically used for:

[0020] The system receives and stores the first firmware, first test program, second firmware, and second test program sent by the host in the storage medium. When it receives the first control command and the second control command sent by the host, it performs circuit control of the switching circuit so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and the m chips under test specified by the second control command are sequentially connected to the m chip firmware interfaces of the FPGA through the switching circuit. It also performs power supply control of the chip test socket so that the k chips under test specified by the first control command and the m chips under test specified by the second control command are powered on. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test performs the first test program test. When it receives a read command from any of the m chips under test, it sends the second firmware and the second test program to the chip under test so that the chip under test performs the second test program test.

[0021] Preferably, the host is connected to the FPGA via a USB interface and / or an Ethernet interface.

[0022] Preferably, the storage medium includes a first storage device and a second storage device, and the storage medium uses the first storage device and / or the second storage device to store data.

[0023] Preferably, the first storage device is the default data storage device, and when the first storage device fails, the second storage device is switched to the default data storage device.

[0024] Preferably, the host is further used for:

[0025] When the first test program is performed on any chip under test, the memory test of the chip under test is performed by interacting with the chip under test through data.

[0026] Preferably, the host is further used for:

[0027] When the first test program is performed on any chip under test, the network configuration test of the chip under test is performed by interacting with the chip under test through data.

[0028] A chip testing method is applied to an FPGA, wherein the FPGA is connected to a storage medium, a switching circuit, a host computer, and a chip test socket. The chip test socket has N slots to hold up to N chips under test. The switching circuit is connected to the chip test socket, and the host computer is connected to the FPGA and the chip test socket. The chip testing method includes:

[0029] Receive the first firmware and the first test program sent by the host and store them in the storage medium;

[0030] When the first control command sent by the host is received, the circuit control of the switching circuit is performed so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and the power supply control of the chip test socket is performed so that the k chips under test specified by the first control command are powered on.

[0031] When a read command is received from any of the k chips under test, the first firmware and the first test program are sent to the chip under test so that the chip under test can perform the test of the first test program.

[0032] Wherein, when any chip under test is tested by the first test program, the host records the test results; N is a positive integer not less than 2, and k is a positive integer and k≤N.

[0033] The chip test socket provided by the embodiments of this invention has N slots. Therefore, this application can test up to N chips under test at a time, improving efficiency. Specifically, the FPGA can receive the first firmware and the first test program sent by the host and store them in the storage medium. When a first control command is received from the host, the FPGA controls the switching circuit to connect the k chips under test specified by the first control command to the k chip firmware interfaces of the FPGA in sequence through the switching circuit. The FPGA also controls the power supply of the chip test socket to power on the k chips under test specified by the first control command. When a read command is received from any of the k chips under test, the FPGA sends the first firmware and the first test program to the chip under test to perform the first test program. While any chip under test is performing the first test program, the host can record the test results. It can be seen that after the host sends the first control command, the testing of the k chips under test can be performed automatically, effectively improving the testing efficiency of this application. Furthermore, unlike traditional methods where the first firmware and test program are manually flashed to an external storage medium, this application allows the host to send them to the FPGA and temporarily store them in a storage medium connected to the FPGA. This process is fast and less prone to damage from repeated flashing, thus further improving testing efficiency. Additionally, this solution can complete the process automatically after the host sends the first control command, which also contributes to improved testing efficiency.

[0034] In summary, the solution proposed in this application can perform batch testing of chips under test, with fast writing speed and automatic completion, thus effectively improving testing efficiency. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a chip testing device according to the present invention;

[0037] Figure 2 This is a schematic diagram of the chip testing device in a specific embodiment of the present invention;

[0038] Figure 3 This is a flowchart illustrating the implementation of a chip testing method according to the present invention. Detailed Implementation

[0039] The core of this invention is to provide a chip testing device that can perform batch testing of chips under test, with fast writing speed and automatic completion, thus effectively improving testing efficiency.

[0040] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a chip testing device according to the present invention. The chip testing device may include:

[0042] A chip test socket 10 with N slots is provided for placing up to N chips under test;

[0043] Switching circuit 20 connected to chip test socket 10;

[0044] Storage medium 30;

[0045] The FPGA 40, connected to the storage medium 30, receives the first firmware and the first test program from the host 50 and stores them in the storage medium 30. When it receives the first control command from the host 50, it controls the switching circuit 20 to connect the k chips under test specified by the first control command to the k chip firmware interfaces of the FPGA 40 in sequence through the switching circuit 20, and controls the power supply of the chip test socket 10 to power on the k chips under test specified by the first control command. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the test of the first test program.

[0046] The host 50, which is connected to the FPGA40 and the chip test socket 10, is used to record the test results when any chip under test is tested using the first test program.

[0047] Where N is a positive integer not less than 2, and k is a positive integer and k≤N.

[0048] Specifically, in the solution of this application, considering the programmable lines and real-time operation of FPGA (Field Programmable Gate Array), and the ability to meet the requirements of chip firmware interface, this application is based on FPGA40 to implement a chip testing device.

[0049] The specific FPGA40 model can be set and selected according to needs. For example, a Zynq FPGA chip can be used. The Zynq FPGA chip is a scalable processing platform SoC series chip that integrates an FPGA and an ARM processor. Of course, in other situations, other types of FPGA40 can be used, such as FPGAs with Xilinx Microblaze soft cores or Intel Nios soft cores.

[0050] FPGA 40 needs to communicate with host 50 to transmit corresponding data. For example, considering the universality of the interface, FPGA 40 can use a USB (Universal Serial Bus) interface to communicate with host 50. Furthermore, this application considers that when host 50 and FPGA 40 are remotely connected, the flexibility of the solution can be further improved. Therefore, in one specific embodiment of the present invention, host 50 can connect to FPGA 40 via a USB interface and / or an Ethernet interface. For example... Figure 2 In this implementation, an Ethernet interface is set up to enable communication between the host 50 and the FPGA 40, allowing the host 50 to be placed remotely, which makes the organization of the test environment more flexible.

[0051] FPGA40 can receive the first firmware and first test program sent by host 50 and store them in storage medium 30. To ensure efficient writing, storage medium 30 is typically a DDR (Double Data Rate) memory mounted on FPGA40. Furthermore... Figure 2 The FPGA40 also has an external SD card, which can be used to store the FPGA40's own firmware and operating system image.

[0052] The FPGA40 can use the PS (Processing System) section to run an operating system to implement Ethernet or USB drivers, thereby quickly establishing a connection with the host 50. The PL (Programmable Logic) section mainly includes a data forwarding module, a chip firmware interface module, and a test switching control module, used to fulfill the functional requirements of the FPGA40 in this application.

[0053] FPGA40 can receive the first control command sent by host 50, and then perform circuit control of switching circuit 20 and power supply control of chip test socket 10 according to the first control command.

[0054] Specifically, the first control command can specify k chips under test. For example, it can specify the chip under test in the first slot, the chip under test in the third slot, and the chip under test in the fourth slot of the chip test socket 10, i.e., k=3 in this example.

[0055] Since the first control command specifies k chips under test, the FPGA40 can perform circuit control of the switching circuit 20, for example... Figure 2 In this implementation, the switching circuit 20 is controlled by the test switching control module, so that the k chips under test specified by the first control command are connected to the k chip firmware interfaces of the FPGA 40 in sequence through the switching circuit 20.

[0056] Taking the chip under test in the first slot of the chip test socket 10 as an example, and for example, the FPGA40 has 10 chip firmware interfaces, and the interface protocols of these 10 chip firmware interfaces are all the same and all match the interface protocol of the chip under test in the first slot, then the chip under test in the first slot can be connected to any one of the 10 chip firmware interfaces of the FPGA40 through the switching circuit 20.

[0057] It is understandable that in the above example, when the interface protocols of the firmware interfaces of each chip of FPGA40 are the same, that is, FPGA40 only supports testing the chip under test with one interface protocol, it can usually be applied in situations where the interface protocol of the chip under test is relatively simple.

[0058] In addition to controlling the switching circuit 20, power supply control for the chip test socket 10 is also required. In the example above, the test switching control module needs to power on the chip under test in the first slot, the third slot, and the fourth slot of the chip test socket 10 based on the first control command.

[0059] After any one of the k chips under test (DUTs) is powered on, it can automatically send a read command to the FPGA 40 since it has already been connected to the FPGA 40 via the switching circuit 20. When the FPGA 40 receives a read command from any one of the k DUTs, it can send the first firmware and the first test program to the DUT. For example... Figure 2 In this scenario, the first firmware and the first test program previously issued by the host 50 are temporarily stored in the DDR memory. At this time, the PS part of the FPGA 40 can send the first firmware and the first test program to the chip firmware interface module in the PL part through the data forwarding module.

[0060] The chip firmware interface module can implement the external interface model of FPGA40, and can send the first firmware and the first test program to k chips under test.

[0061] The chip test socket 10 has N slots, so it can hold up to N chips under test. It is understood that for any one of the chips under test in any slot, the FPGA 40 can control the power-on of that slot, and through the control switching circuit 20, the chip under test in that slot can be connected to any one of the chip firmware interfaces of the FPGA 40.

[0062] The host 50 is connected to the chip test socket 10, either directly or indirectly through the switching circuit 20. For example... Figure 2 In this scenario, an indirect connection is established via switching circuit 20, and the connection method used is a serial port connection. When any chip under test is being tested using the first test program, the host 50 can observe and record the test results.

[0063] Furthermore, in some cases, the host 50 can also interact with the chip under test to perform other tests, further improving the flexibility of the solution. For example, in one specific embodiment of the present invention, the host 50 can also be used for:

[0064] When any chip under test is being tested using the first test program, memory testing of the chip under test is performed by interacting with the chip under test via data exchange.

[0065] Specifically, for example, at a certain stage of the first test program for the chip under test, the host 50 can send a memory test command to the chip under test via a serial port, thereby recording relevant data and obtaining the memory test results of the chip under test.

[0066] In this implementation, considering that memory is an important part of the chip under test, data interaction is performed between the host 50 and the chip under test. While the chip under test is being tested by the first test program, the memory test of the chip under test is also realized, which improves the flexibility of the solution and helps to ensure the quality of the chips leaving the factory.

[0067] In one specific embodiment of the present invention, the host 50 can also be used for:

[0068] When any chip under test is being tested using the first test program, the network configuration of the chip under test is tested by interacting with the chip under test through data exchange.

[0069] Specifically, for example, at a certain stage of the first test program for the chip under test, the host 50 can send network configuration commands to the chip under test via serial port, thereby recording relevant data and obtaining the network configuration test results of the chip under test.

[0070] In this implementation, considering that the network is an important part of the chip under test, just like the memory, and is also prone to errors, the host 50 interacts with the chip under test to perform network configuration testing while the chip under test is performing the first test program. This improves the flexibility of the solution and also helps to ensure the quality of the chips leaving the factory.

[0071] In one specific embodiment of the present invention, the FPGA40 may be configured with a type A chip firmware interface to support a type A interface protocol; where A is a positive integer not less than 2.

[0072] When the FPGA40 performs circuit control of the switching circuit 20 for any one of the k chips under test specified by the first control command, it is specifically used to: control the switching circuit 20 so that the chip under test is connected to the chip firmware interface in the FPGA40 that matches the interface protocol of the chip under test.

[0073] In one of the aforementioned embodiments, the interface protocols of each chip firmware interface of FPGA40 are the same, that is, FPGA40 only supports testing of the chip under test with one interface protocol, which can usually be applied in situations where the interface protocol of the chip under test is relatively simple.

[0074] This implementation takes into account that in some cases, different chips under test may use different interface protocols. Therefore, the FPGA40 can be configured with a type A chip firmware interface to support a type A interface protocol; A is a positive integer not less than 2.

[0075] Since the FPGA40 has different types of chip firmware interfaces to support different interface protocols, when controlling the switching circuit 20, the chip under test (DUT) needs to be connected to the chip firmware interface in the FPGA40 that matches the DUT's interface protocol. Of course, the host 50 should specify which interface protocol the DUT currently supports and reflect this in the first control command issued.

[0076] Furthermore, considering that the commonly used interfaces for the chip under test are SPI interface and SD card interface, in one specific embodiment of the present invention, FPGA40 is provided with at least SPI interface and SD card interface.

[0077] There can be several specific types of SPI interfaces, such as Figure 2 In the implementation method, a QSPI model is set up to manage each QSPI interface, and an SD model is set up to manage each SD card interface.

[0078] In one specific embodiment of the present invention, FPGA40 is specifically used for:

[0079] The system receives the first firmware, first test program, second firmware, and second test program from the host 50 and stores them in the storage medium 30. When it receives the first control command and the second control command from the host 50, it performs circuit control of the switching circuit 20 so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA 40 through the switching circuit 20, and the m chips under test specified by the second control command are sequentially connected to the m chip firmware interfaces of the FPGA 40 through the switching circuit 20. It also performs power supply control of the chip test socket 10 so that the k chips under test specified by the first control command and the m chips under test specified by the second control command are powered on. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the first test program test. When it receives a read command from any of the m chips under test, it sends the second firmware and the second test program to the chip under test so that the chip under test can perform the second test program test.

[0080] For different chips under test, the required firmware and test programs may be the same or different. In some batch testing scenarios, firmware and test program switching may not be required for a long time. In this case, the host 50 can send the first firmware and the first test program, which is then stored in the storage medium 30 via the FPGA 40. After the batch testing is completed, for example, if the next batch of chips under test requires the third firmware and the third test program, the host 50 can send the third firmware and the third test program, which is then stored in the storage medium 30 via the FPGA 40. Alternatively, a command can be sent to delete the previously stored first firmware and the first test program.

[0081] In this implementation, considering that in some cases a small number of chips under test are being tested, for example, k=3, and these 3 chips under test require the first firmware and the first test program, m=5, and these 5 chips under test require the second firmware and the second test program.

[0082] In this embodiment, the host 50 is allowed to simultaneously send the first firmware, the first test program, the second firmware, and the second test program to the FPGA 40, which can then store all this data in the storage medium 30. Subsequently, during circuit control of the switching circuit 20, based on the interface protocols supported by each chip under test, k+m chips under test can be connected to the corresponding chip firmware interface of the FPGA 40 via the switching circuit 20. Similarly, during power supply control of the chip test socket 10, all k+m chips under test can be powered on.

[0083] Accordingly, when a read command is received from any of the k chips under test, the first firmware and the first test program are sent. When a read command is received from any of the m chips under test, the second firmware and the second test program are sent.

[0084] As can be seen, in this implementation, when different firmware and test programs are required for different chips under test, tests can be performed simultaneously. Of course, the number of k+m cannot exceed the total number of slots N, and the FPGA40 needs to be equipped with a sufficient number of chip firmware interfaces to connect the corresponding chips under test.

[0085] Furthermore, in some cases, when different chips under test require the same firmware but different test programs, or the same test program but different firmware, this implementation method can also be applied. Essentially, the first firmware can be the same as the second firmware, but the first test program and the second test program can be different. Alternatively, the first firmware and the second firmware can be different, but the first test program and the second test program can be the same. In other words, in this implementation method, the specific content of the first firmware, the first test program, the second firmware, and the second test program can all be set as needed. Additionally, in some cases, to ensure testing accuracy and reduce the likelihood of errors, k chips under test and m chips under test are usually selected that support the same interface protocol. That is, for chips under test that support different interface protocols, they can be tested in batches instead of being tested in the same batch as in this implementation method.

[0086] Furthermore, it is understandable that the specific value of the number of slots N in the chip test socket 10 can be set as needed. The larger the value of N, the more chips under test can be placed at one time, and the higher the testing efficiency. However, the requirements for the number of chip firmware interfaces of FPGA40 will be higher, and the structure of switching circuit 20 and chip test socket 10 will be more complex, resulting in higher costs. Therefore, the value of N can be designed according to the actual business requirements.

[0087] Figure 2 Furthermore, the FPGA40, switching circuit 20, and chip test socket 10 are all arranged on the same test board, which helps to improve integration and reduce size.

[0088] In one specific embodiment of the present invention, the storage medium 30 includes a first storage device and a second storage device, and the storage medium 30 uses the first storage device and / or the second storage device to store data.

[0089] As described above, to ensure efficient writing, the storage medium 30 is typically a DDR memory mounted on the FPGA 40. In this embodiment, to ensure redundancy of the storage function, the storage medium 30 may specifically include a first storage device and a second storage device. The storage medium 30 can then utilize the first storage device and / or the second storage device for data storage.

[0090] For example, the first storage device and the second storage device can typically be configured in a primary-backup redundant manner. For instance, in one specific embodiment of the present invention, the first storage device is the default data storage device, and when the first storage device fails, the second storage device switches to become the default data storage device.

[0091] In other words, firmware and test programs can be preferentially stored in the first storage device, such as a DDR memory. When the first storage device fails, the second storage device, such as an SD card, will switch to the default data storage device, so that the storage medium 30 of this application can still perform its functions.

[0092] Of course, the storage medium 30 can also be configured with other rules when using the first storage device and / or the second storage device for data storage. For example, the first storage device can be used by default, but the second storage device can be used when the storage space of the first storage device is exhausted. Alternatively, after the host 50 sends out firmware and test programs, it can simultaneously store data in both the first and second storage devices. When the FPGA 40 needs to use the data, it compares whether the data stored in the two devices is consistent to avoid the impact of data transmission errors on chip testing.

[0093] Using the technical solution provided in this embodiment of the invention, the chip test socket 10 is provided with N slots. Therefore, when performing chip testing, this application can test up to N chips under test at a time, improving efficiency. Specifically, the FPGA 40 can receive the first firmware and the first test program sent by the host 50 and store them in the storage medium 30. When it receives the first control command sent by the host 50, it performs circuit control of the switching circuit 20 so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA 40 through the switching circuit 20, and performs power supply control of the chip test socket 10 so that the k chips under test specified by the first control command are powered on. When it receives a read instruction sent by any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the test of the first test program. When any chip under test is performing the test of the first test program, the host 50 can record the test results. It can be seen that after the host 50 sends the first control command, the test of k chips under test can be performed automatically, effectively improving the testing efficiency of this application. Furthermore, unlike traditional methods where the first firmware and first test program are manually flashed to the external storage medium 30, this application allows the host 50 to send them to the FPGA 40 and temporarily store them in the storage medium 30 connected to the FPGA 40. This process is fast and less prone to damage caused by repeated flashing, thus further improving testing efficiency. In addition, this application's solution can be completed automatically after the host 50 sends the first control command, which also contributes to improved testing efficiency.

[0094] In summary, the solution proposed in this application can perform batch testing of chips under test, with fast writing speed and automatic completion, thus effectively improving testing efficiency.

[0095] Corresponding to the above embodiments of the chip testing apparatus, this invention also provides a chip testing method, which can be referred to in conjunction with the above.

[0096] See Figure 3 The diagram shows a flowchart of a chip testing method applied to an FPGA. The FPGA is connected to a storage medium, a switching circuit, a host computer, and a chip test socket. The chip test socket has N slots to hold up to N chips under test. The switching circuit is connected to the chip test socket, and the host computer is connected to the FPGA and the chip test socket. The chip testing method includes the following steps:

[0097] Step S301: Receive the first firmware and the first test program sent by the host and store them in the storage medium;

[0098] Step S302: When the first control command sent by the host is received, the circuit control of the switching circuit is performed so that the k chips under test specified by the first control command are connected to the k chip firmware interfaces of the FPGA in sequence through the switching circuit, and the power supply control of the chip test socket is performed so that the k chips under test specified by the first control command are powered on.

[0099] Step S303: When a read command is received from any of the k chips under test, the first firmware and the first test program are sent to the chip under test so that the chip under test can perform the test of the first test program.

[0100] In this process, when any chip under test is tested using the first test program, the host records the test results; N is a positive integer not less than 2, and k is a positive integer and k≤N.

[0101] In one specific embodiment of the present invention, the FPGA is provided with A types of chip firmware interfaces to support A types of interface protocols; A is a positive integer not less than 2;

[0102] For any one of the k chips under test specified by the first control command, the circuit control for switching circuits described in step S302 includes:

[0103] By controlling the switching circuit, the chip under test (DUT) is connected to the chip firmware interface in the FPGA that matches the interface protocol of the DUT.

[0104] In one specific embodiment of the present invention, the FPGA is provided with at least an SPI interface and an SD card interface.

[0105] In one specific embodiment of the present invention, the FPGA is specifically used for:

[0106] The system receives and stores the first firmware, first test program, second firmware, and second test program sent by the host in a storage medium. When it receives the first control command and the second control command sent by the host, it performs circuit control of the switching circuit so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and the m chips under test specified by the second control command are sequentially connected to the m chip firmware interfaces of the FPGA through the switching circuit. It also performs power supply control of the chip test socket so that the k chips under test specified by the first control command and the m chips under test specified by the second control command are powered on. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the first test program test. When it receives a read command from any of the m chips under test, it sends the second firmware and the second test program to the chip under test so that the chip under test can perform the second test program test.

[0107] In one specific embodiment of the present invention, the host is connected to the FPGA via a USB interface and / or an Ethernet interface.

[0108] In one specific embodiment of the present invention, the storage medium includes a first storage device and a second storage device, and the storage medium uses the first storage device and / or the second storage device to store data.

[0109] In one specific embodiment of the present invention, the first storage device is the default data storage device, and when the first storage device fails, the second storage device is switched to the default data storage device.

[0110] In one specific embodiment of the present invention, it further includes:

[0111] When the host performs the first test program on any chip under test, it performs memory testing on the chip under test by exchanging data with the chip under test.

[0112] In one specific embodiment of the present invention, it further includes:

[0113] When the host performs the first test program on any chip under test, it performs network configuration test on the chip under test by interacting with the chip under test through data exchange.

[0114] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0115] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0116] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A chip testing device, characterized in that, include: A chip test socket with N slots is provided to hold up to N chips under test. The switching circuit connected to the chip test socket; Storage medium; The FPGA connected to the storage medium is used to receive the first firmware and the first test program sent by the host and store them in the storage medium. When it receives the first control command sent by the host, it performs circuit control of the switching circuit so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and performs power supply control of the chip test socket so that the k chips under test specified by the first control command are powered on. When it receives a read command sent by any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test can perform the test of the first test program. The host computer connected to the FPGA and the chip test socket is used to record the test results when any chip under test is tested by the first test program. Where N is a positive integer not less than 2, and k is a positive integer and k≤N; The FPGA is specifically used for: The system receives and stores the first firmware, first test program, second firmware, and second test program sent by the host in the storage medium. When it receives the first control command and the second control command sent by the host, it performs circuit control of the switching circuit so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and the m chips under test specified by the second control command are sequentially connected to the m chip firmware interfaces of the FPGA through the switching circuit. It also performs power supply control of the chip test socket so that the k chips under test specified by the first control command and the m chips under test specified by the second control command are powered on. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test so that the chip under test performs the first test program test. When it receives a read command from any of the m chips under test, it sends the second firmware and the second test program to the chip under test so that the chip under test performs the second test program test; where k+m≤N.

2. The chip testing apparatus according to claim 1, characterized in that, The FPGA is equipped with A types of chip firmware interfaces to support A types of interface protocols; A is a positive integer not less than 2; When the FPGA performs circuit control of the switching circuit for any one of the k chips under test specified by the first control command, it is specifically used to: control the switching circuit to connect the chip under test to the chip firmware interface in the FPGA that matches the interface protocol of the chip under test.

3. The chip testing apparatus according to claim 2, characterized in that, The FPGA is equipped with at least an SPI interface and an SD card interface.

4. The chip testing apparatus according to claim 1, characterized in that, The host is connected to the FPGA via a USB interface and / or an Ethernet interface.

5. The chip testing apparatus according to claim 1, characterized in that, The storage medium includes a first storage device and a second storage device, and the storage medium uses the first storage device and / or the second storage device to store data.

6. The chip testing apparatus according to claim 5, characterized in that, The first storage device is the default data storage device. When the first storage device fails, the second storage device is switched to the default data storage device.

7. The chip testing apparatus according to any one of claims 1 to 6, characterized in that, The host is also used for: When the first test program is performed on any chip under test, the memory test of the chip under test is performed by interacting with the chip under test through data.

8. The chip testing apparatus according to any one of claims 1 to 6, characterized in that, The host is also used for: When the first test program is performed on any chip under test, the network configuration test of the chip under test is performed by interacting with the chip under test through data.

9. A chip testing method, characterized in that, Applied in an FPGA, the FPGA is connected to a storage medium, a switching circuit, a host computer, and a chip test socket. The chip test socket has N slots to hold up to N chips under test. The switching circuit is connected to the chip test socket. The host computer is connected to the FPGA and the chip test socket. The chip testing method includes: Receive the first firmware and the first test program sent by the host and store them in the storage medium; When the first control command sent by the host is received, the circuit control of the switching circuit is performed so that the k chips under test specified by the first control command are sequentially connected to the k chip firmware interfaces of the FPGA through the switching circuit, and the power supply control of the chip test socket is performed so that the k chips under test specified by the first control command are powered on. When a read command is received from any of the k chips under test, the first firmware and the first test program are sent to the chip under test so that the chip under test can perform the test of the first test program. Wherein, when any chip under test is tested by the first test program, the host records the test results; N is a positive integer not less than 2, and k is a positive integer and k≤N; FPGA, specifically used for: The system receives and stores the first firmware, first test program, second firmware, and second test program sent by the host in a storage medium. When it receives the first control command and the second control command sent by the host, it performs circuit control of the switching circuit to connect the k chips under test specified by the first control command to the k chip firmware interfaces of the FPGA in sequence through the switching circuit, and connects the m chips under test specified by the second control command to the m chip firmware interfaces of the FPGA in sequence through the switching circuit. It also performs power supply control of the chip test socket to power on the k chips under test specified by the first control command and the m chips under test specified by the second control command. When it receives a read command from any of the k chips under test, it sends the first firmware and the first test program to the chip under test to perform the first test program test. When it receives a read command from any of the m chips under test, it sends the second firmware and the second test program to the chip under test to perform the second test program test. Where k+m≤N.

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