Electronic devices, high electron mobility transistors and their fabrication methods

Abstract

This disclosure provides an electronic device, a high electron mobility transistor, and a method for fabricating the same. The method for fabricating the high electron mobility transistor includes: forming a heterojunction structure on a substrate, the heterojunction structure including a source region, a drain region, and a gate region located between the source and drain regions; forming a first dielectric layer, a sacrificial gate, a second dielectric layer, and a protective layer in the gate region, the first dielectric layer, the sacrificial gate, and the second dielectric layer being stacked, and the protective layer covering the sidewalls of the sacrificial gate; forming a first window on the second dielectric layer to expose the sacrificial gate; removing the sacrificial gate through the first window to form a cavity between the first and second dielectric layers; and forming a gate that passes through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer. This disclosure can reduce parasitic capacitance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an electronic device, a high electron mobility transistor, and a method for fabricating the same. Background Technology

[0002] Nitride semiconductor materials are widely used in high electron mobility transistors (HEMTs) due to their wider bandgap, higher breakdown electric field, higher electron density, and higher mobility compared to traditional semiconductor materials. However, existing HEMTs still require further improvement. Summary of the Invention

[0003] The purpose of this disclosure is to provide an electronic device, a high electron mobility transistor, and a method for fabricating the same, which can reduce parasitic capacitance.

[0004] According to one aspect of this disclosure, a method for fabricating a high electron mobility transistor is provided, comprising:

[0005] A heterojunction structure is formed on a substrate, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region;

[0006] A first dielectric layer, a sacrificial gate, a second dielectric layer, and a protective layer are formed in the gate region. The first dielectric layer, the sacrificial gate, and the second dielectric layer are stacked. The first dielectric layer is located between the second dielectric layer and the substrate. The protective layer covers the sidewall of the sacrificial gate.

[0007] A first window is formed on the second dielectric layer to expose the sacrificial gate;

[0008] The sacrificial gate is removed through the first window to form a cavity between the first dielectric layer and the second dielectric layer;

[0009] A gate is formed, which passes through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer.

[0010] Furthermore, forming a first dielectric layer, a sacrificial gate, a second dielectric layer, and a protective layer in the gate region includes:

[0011] A first dielectric layer, a sacrificial gate, and a second dielectric layer are stacked in the gate region;

[0012] A protective layer is formed covering the second dielectric layer and the heterojunction structure, the protective layer covering the sacrificial gate sidewall.

[0013] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the fabrication method further includes:

[0014] A heavily doped structure is formed on the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial gate, and the heavily doped structure has the same conductivity type as the barrier layer.

[0015] Further, forming a first window on the second dielectric layer to expose the sacrificial gate includes:

[0016] A passivation layer is formed covering the heavily doped structure and the second dielectric layer;

[0017] A second window is formed on the passivation layer by photolithography, and a first window is formed on the second dielectric layer to expose the sacrificial gate. The first window is connected to the second window.

[0018] Further, removing the sacrificial gate through the first window includes:

[0019] The sacrificial gate is removed by a wet etching process.

[0020] Furthermore, the material of the sacrificial gate includes polysilicon, and the etching solution used in the wet etching process includes tetramethylammonium hydroxide.

[0021] Furthermore, the material of the first dielectric layer includes silicon nitride or silicon oxide; and / or

[0022] The material of the second dielectric layer includes silicon nitride or silicon oxide.

[0023] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the fabrication method further includes:

[0024] Remove the portion of the protective layer located in the drain region and the source region;

[0025] The portion of the barrier layer located in the source region and the drain region is thinned.

[0026] A heavily doped structure is formed in the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial gate, and the heavily doped structure has the same conductivity type as the barrier layer.

[0027] Furthermore, the cross-sectional area of ​​the portion of the gate located inside the cavity is smaller than the cross-sectional area of ​​the portion of the gate located outside the cavity.

[0028] Furthermore, the preparation method further includes:

[0029] A source electrode is formed in the source region, and a drain electrode is formed in the drain region.

[0030] According to one aspect of this disclosure, a high electron mobility transistor is provided, comprising:

[0031] Substrate;

[0032] A heterojunction structure, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region;

[0033] A first dielectric layer is disposed in the gate region;

[0034] The second dielectric layer is disposed on the side of the first dielectric layer away from the substrate and is spaced apart from the first dielectric layer; the second dielectric layer has a first window penetrating the second dielectric layer;

[0035] The protective layer has a cylindrical structure and is connected between the first dielectric layer and the second dielectric layer;

[0036] A gate extends through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer.

[0037] Furthermore, the heterojunction structure includes a channel layer and a barrier layer, and the high electron mobility transistor further includes:

[0038] A heavily doped structure is disposed on the source region and the drain region, the heavily doped structure covers the sidewall of the protective layer, and the heavily doped structure has the same conductivity type as the barrier layer.

[0039] Furthermore, the high electron mobility transistor also includes:

[0040] A passivation layer covers the heavily doped structure and the second dielectric layer. The passivation layer has a second window, and the first window is connected to the second window.

[0041] Furthermore, the cross-sectional area of ​​the portion of the gate located inside the cavity is smaller than the cross-sectional area of ​​the portion of the gate located outside the cavity.

[0042] Furthermore, the high electron mobility transistor also includes:

[0043] A source electrode is disposed on the source electrode region;

[0044] The drain electrode is located in the drain region.

[0045] According to one aspect of this disclosure, an electronic device is provided, including the aforementioned high electron mobility transistor.

[0046] The electronic device, high electron mobility transistor, and fabrication method disclosed herein are provided. A first dielectric layer and a second dielectric layer are disposed opposite each other, with a sacrificial gate located between the first and second dielectric layers. This disclosure removes the sacrificial gate through a first window disposed on the second dielectric layer, thereby forming a cavity between the first and second dielectric layers. The gate formed thereafter passes through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer, thereby reducing the parasitic capacitance of the gate and enhancing the application performance of the high electron mobility transistor at millimeter-wave and terahertz frequencies. Simultaneously, this disclosure also provides good structural support for miniaturized gates, improving yield. Attached Figure Description

[0047] Figure 1 This is a schematic diagram after the second dielectric layer is formed in an embodiment of this disclosure.

[0048] Figure 2 This is a schematic diagram of the protective layer after it has been formed in the embodiments of this disclosure.

[0049] Figure 3 This is a schematic diagram of the barrier layer after thinning in the embodiments of this disclosure.

[0050] Figure 4 This is a schematic diagram of the heavily doped structure formed in the embodiments of this disclosure.

[0051] Figure 5 yes Figure 4 The diagram shows a cross-sectional view of the structure shown.

[0052] Figure 6 This is a schematic diagram after the passivation layer is formed in an embodiment of this disclosure.

[0053] Figure 7 This is a schematic diagram after the first window is formed in the embodiments of this disclosure.

[0054] Figure 8 yes Figure 7 A partial schematic diagram of the structure shown.

[0055] Figure 9 This is a schematic diagram after the gate material layer is formed in an embodiment of this disclosure.

[0056] Figure 10 This is a schematic diagram after the gate is formed in an embodiment of this disclosure.

[0057] Figure 11 This is a schematic diagram showing the formation of the source and drain in the embodiments of this disclosure.

[0058] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Heterojunction structure; 201. Channel layer; 202. Barrier layer; 3. First dielectric layer; 4. Sacrificial gate; 5. Second dielectric layer; 6. Protective layer; 7. Heavily doped structure; 8. Passivation layer; 9. Gate; 10. Cavity; 11. Gate material layer; 12. Photoresist layer; 13. First window; 14. Second window; 15. Source; 16. Drain. Detailed Implementation

[0059] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0060] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. Unless otherwise defined, the technical or scientific terms used in this disclosure should be understood in their ordinary sense by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “a” or “one,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. “A plurality” or “several” indicates two or more. Unless otherwise stated, the terms “front,” “rear,” “lower,” and / or “upper,” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The terms “comprising,” “including,” and similar terms mean that the elements or objects preceding “comprising,” encompass the elements or objects listed following “comprising,” and their equivalents, and do not exclude other elements or objects. The terms “connected,” “linked,” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0061] This disclosure provides a method for fabricating a high electron mobility transistor. The method for fabricating the high electron mobility transistor may include steps 100-140, wherein:

[0062] Step 100, as follows Figure 1As shown, a heterojunction structure 2 is formed on a substrate 1. The heterojunction structure 2 includes a source region, a drain region, and a gate region located between the source region and the drain region.

[0063] Step 110, as follows Figure 3 As shown, a first dielectric layer 3, a sacrificial gate 4, a second dielectric layer 5, and a protective layer 6 are formed in the gate region. The first dielectric layer 3, the sacrificial gate 4, and the second dielectric layer 5 are stacked. The first dielectric layer 3 is located between the second dielectric layer 5 and the substrate 1, and the protective layer 6 covers the sidewall of the sacrificial gate 4.

[0064] Step 120, as follows Figure 7 and Figure 8 As shown, a first window 13 is formed on the second dielectric layer 5 to expose the sacrificial gate 4.

[0065] Step 130, as Figure 9 As shown, the sacrificial gate 4 is removed through the first window 13 to form a cavity 10 between the first dielectric layer 3 and the second dielectric layer 5.

[0066] Step 140, as follows Figure 10 As shown, a gate 9 is formed, which passes through the first window 13 to contact the first dielectric layer 3, and the gate 9 is spaced apart from the protective layer 6.

[0067] The method for fabricating a high electron mobility transistor according to the present disclosure includes a first dielectric layer 3 and a second dielectric layer 5 disposed opposite to each other, and a sacrificial gate 4 located between the first dielectric layer 3 and the second dielectric layer 5. The present disclosure removes the sacrificial gate 4 by providing a first window 13 on the second dielectric layer 5, thereby forming a cavity 10 between the first dielectric layer 3 and the second dielectric layer 5. The gate 9 formed thereafter passes through the first window 13 to contact the first dielectric layer 3, and the gate 9 is spaced apart from the protective layer 6, thereby reducing the parasitic capacitance of the gate 9.

[0068] The following is a detailed description of each step in the fabrication method of the high electron mobility transistor according to the present disclosure:

[0069] In step 100, as Figure 1 As shown, a heterojunction structure 2 is formed on a substrate 1. The heterojunction structure 2 includes a source region, a drain region, and a gate region located between the source region and the drain region.

[0070] The substrate 1 can be a silicon substrate or a silicon carbide substrate. Of course, the substrate 1 can also be a sapphire substrate, but the embodiments disclosed herein are not limited to this. The substrate 1 can also be silicon-on-insulator, etc.

[0071] The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The channel layer 201 may be disposed between the barrier layer 202 and the substrate 1. The material of the channel layer 201 may be at least one of GaN, AlGaN, InGaN, and AlInGaN. The bandgap of the barrier layer 202 is greater than the bandgap of the channel layer 201. The material of the barrier layer 202 may be at least one of GaN, AlGaN, InGaN, and AlInGaN. The barrier layer 202 may be an n-type semiconductor, but this disclosure does not specifically limit it. The channel layer 201 and the barrier layer 202 may be fabricated by epitaxial growth. The gate region may be strip-shaped, but the embodiments of this disclosure are not limited to this. Furthermore, in a direction parallel to the substrate 1 and perpendicular to the strip-shaped gate region, the length of one end of the gate region is greater than the length of the other end of the gate region, that is, the gate region may be "T"-shaped. The arrangement direction of the source region, drain region, and gate region may be perpendicular to the extension direction of the strip-shaped gate region.

[0072] In step 110, as Figure 1 As shown, a first dielectric layer 3, a sacrificial gate 4, a second dielectric layer 5, and a protective layer 6 are formed in the gate region. The first dielectric layer 3, the sacrificial gate 4, and the second dielectric layer 5 are stacked. The first dielectric layer 3 is located between the second dielectric layer 5 and the substrate 1, and the protective layer 6 covers the sidewall of the sacrificial gate 4.

[0073] The material of the first dielectric layer 3 may include nitrides, such as silicon nitride (SiN). x The material of the first dielectric layer 3 may also include oxides, such as silicon oxide (SiO2). The material of the sacrificial gate 4 may include polysilicon. The material of the second dielectric layer 5 may include oxides, such as silicon oxide (SiO2), and of course, the material of the second dielectric layer 5 may also include nitrides, such as silicon nitride (SiN). x The material of the protective layer 6 can also include oxides, such as silicon oxide (SiO2), etc. Of course, the material of the protective layer 6 can also include nitrides, such as silicon nitride (SiN). xThe material of the protective layer 6 can be the same as or different from that of the second dielectric layer 5. The thickness of the first dielectric layer 3 can be 10 nm. The thickness of the sacrificial gate 4 can be 200 nm. The thickness of the second dielectric layer 5 can be 100 nm. The thickness of the protective layer 6 can be 100 nm. The shapes of the first dielectric layer 3, the sacrificial gate 4, and the second dielectric layer 5 can be the same as the shape of the gate region. Taking a strip-shaped gate region as an example, the shapes of the first dielectric layer 3, the sacrificial gate 4, and the second dielectric layer 5 are all strip-shaped, and their extension lengths can be 0.5 μm to 0.8 μm. The protective layer 6 can have a cylindrical structure, the axis of which is perpendicular to the substrate 1, and the cylindrical structure can surround the sacrificial gate 4.

[0074] For example, step 110 may include steps 1101-1102, wherein:

[0075] Step 1101, as follows Figure 1 As shown, a first dielectric layer 3, a sacrificial gate 4, and a second dielectric layer 5 are stacked in the gate region.

[0076] Specifically, this disclosure can first form a first dielectric layer 3, a sacrificial gate 4, and a second dielectric layer 5 stacked on the heterojunction structure 2, and then remove the portions of the first dielectric layer 3, the sacrificial gate 4, and the second dielectric layer 5 located outside the gate region.

[0077] Step 1102, as follows Figure 2 As shown, a protective layer 6 is formed covering the second dielectric layer 5 and the heterojunction structure 2, and the protective layer 6 covers the sidewall of the sacrificial gate 4.

[0078] Of course, the protective layer 6 also covers the sidewall of the first dielectric layer 3, and the protective layer 6 also covers the sidewall of the second dielectric layer 5.

[0079] Following step 1102 above, step 110 may further include steps 1103-1105, wherein:

[0080] Step 1103, as follows Figure 3 As shown, the portion of the protective layer 6 located in the drain and source regions is removed.

[0081] Specifically, this disclosure may retain the portion of the protective layer 6 located on the sidewall of the first dielectric layer 3, the portion of the protective layer 6 located on the sidewall of the sacrificial gate 4, and the portion of the protective layer 6 located on the sidewall of the second dielectric layer 5, and remove the remaining portion of the protective layer 6. The retained protective layer 6 has a cylindrical structure.

[0082] Step 1104, as follows Figure 3 As shown, the portion of the barrier layer 202 located in the source and drain regions is thinned.

[0083] Specifically, this disclosure allows for the thinning of the portion of the barrier layer 202 located outside the gate region. This disclosure allows for the thinning of the barrier layer 202 using an etching process.

[0084] Step 1105, as follows Figure 4 and Figure 5 As shown, a heavily doped structure 7 is formed in the source and drain regions. The heavily doped structure 7 covers the sidewall of the protective layer 6 facing away from the sacrificial gate 4. The heavily doped structure 7 has the same conductivity type as the barrier layer 202.

[0085] Taking the barrier layer 202 as an n-type semiconductor as an example, the heavily doped structure 7 can also be an n-type semiconductor, and the doping concentration of the heavily doped structure 7 is greater than the doping concentration of the barrier layer 202. The thickness of the heavily doped structure 7 can be 200 nm.

[0086] In step 120, a first window 13 is formed on the second dielectric layer 5 to expose the sacrificial gate 4.

[0087] For example, step 120 may include: Figure 6 As shown, a passivation layer 8 is formed covering the heavily doped structure 7 and the second dielectric layer 5. The material of the passivation layer 8 may include nitrides, such as silicon nitride (SiN). x The passivation layer 8 can have a thickness of 100 nm; for example... Figure 7 and Figure 8 As shown, a second window 14 is formed on the passivation layer 8 using photolithography, and a first window 13 exposing the sacrificial gate 4 is formed on the second dielectric layer 5. The first window 13 and the second window 14 are connected. During the photolithography process, this disclosure can first form a patterned photoresist layer 12, and then use the patterned photoresist layer 12 as a mask to form the first window 13 and the second window 14. Taking the second dielectric layer 5 as a strip shape as an example, the first window 13 can also be strip-shaped, and the extension direction of the first window 13 is the same as the extension direction of the second dielectric layer 5. The extension length of the first window 13 can be less than or equal to the extension length of the second dielectric layer 5. The shape of the second window 14 is the same as that of the first window 13. The width of the strip-shaped first window 13 can be less than 100 nm.

[0088] In step 130, as Figure 9 As shown, the sacrificial gate 4 is removed through the first window 13 to form a cavity 10 between the first dielectric layer 3 and the second dielectric layer 5.

[0089] This disclosure allows for the removal of the sacrificial gate 4 using a wet etching process. Taking polysilicon as an example, the etching solution used in this wet etching process may include tetramethylammonium hydroxide (TMAH), but this disclosure does not specifically limit this method. The top wall of the formed cavity 10 is the second dielectric layer 5, the bottom wall of the cavity 10 is the first dielectric layer 3, and the side walls of the cavity 10 are the protective layer 6.

[0090] In step 140, a gate 9 is formed, which passes through the first window 13 to contact the first dielectric layer 3, and the gate 9 is spaced apart from the protective layer 6.

[0091] like Figure 9 and Figure 10 As shown, this disclosure allows for the first formation of a gate material layer 11, followed by patterning of the gate material layer 11 to form a gate 9. The cross-sectional area of ​​the portion of the gate 9 located within the cavity 10 is smaller than the cross-sectional area of ​​the portion of the gate 9 located outside the cavity 10; that is, the gate 9 is "T"-shaped. The cross-section of the gate 9 is the cross-section of the gate 9 in a direction parallel to the substrate 1. Furthermore, the cross-sectional area of ​​the portion of the gate 9 located within the cavity 10 can be equal to the cross-sectional area of ​​the portion of the gate 9 located within the first window 13. The gate 9 can be fabricated using a vapor deposition process. In the direction perpendicular to the substrate 1, the gate 9 can be a stacked structure, such as Ti / Al / Ti. The orthogonal projection of the gate 9 onto the substrate 1 can be strip-shaped, and the extension direction can be the same as the extension direction of the strip-shaped first window 13. In the direction perpendicular to the extension direction of the first window 13, the width of the portion of the gate 9 located outside the cavity 10 can be 0.3 μm-0.4 μm. After step 140, the fabrication method of this disclosure may further include: Figure 11 As shown, a source electrode 15 is formed in the source region and a drain electrode 16 is formed in the drain region.

[0092] This disclosure also provides a high electron mobility transistor, which can be fabricated by the fabrication method of any of the high electron mobility transistors described above. For example... Figure 10 and Figure 11 As shown, the high electron mobility transistor may include: a substrate 1; a heterojunction structure 2, which includes a source region, a drain region, and a gate region located between the source region and the drain region; a first dielectric layer 3 disposed in the gate region; a second dielectric layer 5 disposed on the side of the first dielectric layer 3 away from the substrate 1 and spaced apart from the first dielectric layer 3, wherein the second dielectric layer 5 has a first window 13 penetrating the second dielectric layer 5; a protective layer 6 having a cylindrical structure and connecting the first dielectric layer 3 and the second dielectric layer 5; and a gate 9 passing through the first window 13 to contact the first dielectric layer 3, wherein the gate 9 is spaced apart from the protective layer 6.

[0093] The heterojunction structure 2 may include a channel layer 201 and a barrier layer 202. The high electron mobility transistor may also include a heavily doped structure 7. The heavily doped structure 7 is disposed on the source region and the drain region, and covers the sidewalls of the protective layer 6. The heavily doped structure 7 has the same conductivity type as the barrier layer 202.

[0094] The high electron mobility transistor may also include a passivation layer 8. The passivation layer 8 covers the heavily doped structure 7 and the second dielectric layer 5, and the passivation layer 8 has a second window 14, which is connected to the first window 13.

[0095] The cross-sectional area of ​​the portion of the gate 9 located inside the cavity 10 is smaller than the cross-sectional area of ​​the portion of the gate 9 located outside the cavity 10.

[0096] The high electron mobility transistor may also include a source 15 and a drain 16. The source 15 is disposed on the source region. The drain 16 is disposed on the drain region.

[0097] This disclosure also provides an electronic device. This electronic device may include a high electron mobility transistor.

[0098] The high electron mobility transistor fabrication method, high electron mobility transistor, and electronic device provided in this disclosure belong to the same inventive concept. Related details and beneficial effects can be referred to each other and will not be repeated here.

[0099] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure in any way. Although this disclosure has been disclosed above with reference to preferred embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A method for fabricating a high electron mobility transistor, characterized in that, include: A heterojunction structure is formed on a substrate, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region; A first dielectric layer, a sacrificial gate, a second dielectric layer, and a protective layer are formed in the gate region. The first dielectric layer, the sacrificial gate, and the second dielectric layer are stacked. The first dielectric layer is located between the second dielectric layer and the substrate. The protective layer covers the sidewall of the sacrificial gate. A first window is formed on the second dielectric layer to expose the sacrificial gate; The sacrificial gate is removed through the first window to form a cavity between the first dielectric layer and the second dielectric layer, and the protective layer forms the sidewall of the cavity; A gate is formed, which passes through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer.

2. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, Forming a first dielectric layer, a sacrificial gate, a second dielectric layer, and a protective layer in the gate region includes: A first dielectric layer, a sacrificial gate, and a second dielectric layer are stacked in the gate region; A protective layer is formed covering the second dielectric layer and the heterojunction structure, the protective layer covering the sacrificial gate sidewall.

3. The method for fabricating a high electron mobility transistor according to claim 1 or 2, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the preparation method further includes: A heavily doped structure is formed on the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial gate, and the heavily doped structure has the same conductivity type as the barrier layer.

4. The method for fabricating a high electron mobility transistor according to claim 3, characterized in that, Forming a first window on the second dielectric layer to expose the sacrificial gate includes: A passivation layer is formed covering the heavily doped structure and the second dielectric layer; A second window is formed on the passivation layer by photolithography, and a first window is formed on the second dielectric layer to expose the sacrificial gate. The first window is connected to the second window.

5. The method for fabricating a high electron mobility transistor according to claim 1 or 4, characterized in that, Removing the sacrificial gate through the first window includes: The sacrificial gate is removed by a wet etching process.

6. The method for fabricating a high electron mobility transistor according to claim 5, characterized in that, The material of the sacrificial gate includes polysilicon, and the etching solution used in the wet etching process includes tetramethylammonium hydroxide.

7. The method for fabricating a high electron mobility transistor according to claim 6, characterized in that, The material of the first dielectric layer includes silicon nitride or silicon oxide; and / or The material of the second dielectric layer includes silicon nitride or silicon oxide.

8. The method for fabricating a high electron mobility transistor according to claim 2, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the preparation method further includes: Remove the portion of the protective layer located in the drain region and the source region; The portion of the barrier layer located in the source region and the drain region is thinned. A heavily doped structure is formed in the source region and the drain region, the heavily doped structure covering the sidewall of the protective layer facing away from the sacrificial gate, and the heavily doped structure has the same conductivity type as the barrier layer.

9. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The cross-sectional area of ​​the portion of the gate located inside the cavity is smaller than the cross-sectional area of ​​the portion of the gate located outside the cavity.

10. The method for fabricating a high electron mobility transistor according to claim 1, characterized in that, The preparation method further includes: A source electrode is formed in the source region, and a drain electrode is formed in the drain region.

11. A high electron mobility transistor, characterized in that, include: Substrate; A heterojunction structure, the heterojunction structure including a source region, a drain region, and a gate region located between the source region and the drain region; A first dielectric layer is disposed in the gate region; The second dielectric layer is disposed on the side of the first dielectric layer away from the substrate and is spaced apart from the first dielectric layer; the second dielectric layer has a first window penetrating the second dielectric layer; The protective layer has a cylindrical structure and is connected between the first dielectric layer and the second dielectric layer; A gate extends through the first window to contact the first dielectric layer, and the gate is spaced apart from the protective layer. The protective layer, the first dielectric layer, the second dielectric layer, and the gate enclose a cavity, and the protective layer forms at least a portion of the sidewall of the cavity.

12. The high electron mobility transistor according to claim 11, characterized in that, The heterojunction structure includes a channel layer and a barrier layer, and the high electron mobility transistor further includes: A heavily doped structure is disposed on the source region and the drain region, the heavily doped structure covers the sidewall of the protective layer, and the heavily doped structure has the same conductivity type as the barrier layer.

13. The high electron mobility transistor according to claim 12, characterized in that, The high electron mobility transistor also includes: A passivation layer covers the heavily doped structure and the second dielectric layer. The passivation layer has a second window, and the first window is connected to the second window.

14. The high electron mobility transistor according to claim 11, characterized in that, The cross-sectional area of ​​the portion of the gate located inside the cavity is smaller than the cross-sectional area of ​​the portion of the gate located outside the cavity.

15. The high electron mobility transistor according to claim 11, characterized in that, The high electron mobility transistor also includes: A source electrode is disposed on the source electrode region; The drain electrode is located in the drain region.

16. An electronic device, characterized in that, Includes the high electron mobility transistor according to any one of claims 11-15.

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