Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a preparation method thereof. By forming an opening on an isolation structure of a semiconductor substrate, a bottom of the opening exposes part of the substrate, a first alloy layer is formed on the surface of the exposed part of the substrate, and a substrate lead-out structure in contact with the first alloy layer is formed in the opening, so that the substrate lead-out structure forms a good ohmic contact with the substrate through the first alloy layer, realizes low-resistance electrical connection, and has better lead-out effect when a back gate is led out, thereby improving the stability and reliability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] MOS (Metal Oxide Semiconductor) devices are affected by back-gate effect during operation. The back-gate effect mainly refers to the influence of substrate bias (also referred to as back-gate voltage) on threshold voltage. For SOI (Silicon On Insulator) MOS devices, since the buried oxide layer separates the active region and the substrate, the extra charge existing in the substrate forms a back-gate voltage, and the back-gate voltage will affect the device through the buried oxide layer. In order to eliminate the adverse effects of the back-gate effect on the device, the substrate needs to be extracted so as to realize controllable back-gate voltage.

[0003] However, during the extraction of the substrate, there is usually a large contact resistance between the surface of the substrate and the extraction end, thereby reducing the reliability of the semiconductor device. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device and a preparation method thereof, so as to reduce the contact resistance between the surface of the substrate and the extraction end and improve the reliability of the semiconductor device.

[0005] In order to achieve the purpose of the present application, the present application adopts the following technical solutions:

[0006] A preparation method of a semiconductor device, comprising:

[0007] providing a semiconductor substrate, the semiconductor substrate comprising a substrate, an insulating buried layer, a semiconductor layer and a gate structure which are sequentially stacked on the substrate, and the semiconductor substrate further comprising an isolation structure penetrating from the upper surface of the semiconductor layer to the insulating buried layer;

[0008] forming an opening in the isolation structure, the bottom of the opening exposing part of the substrate;

[0009] forming a first alloy layer on the surface of the exposed part of the substrate;

[0010] forming a substrate extraction structure in contact with the first alloy layer in the opening.

[0011] In one of the embodiments, the step of forming an opening in the isolation structure, the bottom of the opening exposing part of the substrate, comprises:

[0012] the opening extends into the substrate, and the bottom wall of the opening and the bottom side wall of the opening both expose part of the substrate.

[0013] In one embodiment, the forming the substrate extraction structure in contact with the first alloy layer in the opening comprises:

[0014] forming an insulating medium layer, the insulating medium layer filling the opening;

[0015] forming a substrate extraction hole in the insulating medium layer in the opening, a bottom of the substrate extraction hole exposing part of the first alloy layer;

[0016] filling a conductive medium in the substrate extraction hole to form the substrate extraction structure.

[0017] In one embodiment, the forming the first alloy layer on the exposed surface of the substrate further comprises:

[0018] simultaneously with the forming the first alloy layer on the exposed surface of the substrate, forming a second alloy layer on an upper surface of the semiconductor layer and an upper surface of the gate structure.

[0019] In one embodiment, the forming the substrate extraction structure in contact with the first alloy layer in the opening further comprises:

[0020] forming an insulating medium layer, the insulating medium layer covering the isolation structure, the first alloy layer and the second alloy layer;

[0021] forming a substrate extraction hole in the insulating medium layer in the opening, a source-drain extraction hole in the insulating medium layer above the source-drain region of the semiconductor layer, and a gate extraction hole in the insulating medium layer above the gate structure, wherein a bottom of the substrate extraction hole exposes part of the first alloy layer, a bottom of the source-drain extraction hole exposes part of the second alloy layer, and a bottom of the gate extraction hole exposes part of the second alloy layer;

[0022] filling a conductive medium in the substrate extraction hole, the source-drain extraction hole and the gate extraction hole to form a substrate extraction structure, a source-drain extraction structure and a gate extraction structure.

[0023] In one embodiment, the substrate extraction structure is electrically connected with a circuit located on an upper surface of the semiconductor layer to form a silicon charge discharge path of the substrate.

[0024] A semiconductor device comprises:

[0025] a semiconductor substrate comprising a substrate, an insulating buried layer, a semiconductor layer and a gate structure sequentially stacked on the substrate, and an isolation structure sequentially penetrating the semiconductor layer and the insulating buried layer from an upper surface of the semiconductor layer;

[0026] a substrate lead-out structure electrically connected with the substrate through the isolation structure;

[0027] a first alloy layer on the substrate surface at the bottom of the substrate lead-out structure for electrically connecting the substrate lead-out structure and the substrate.

[0028] In one embodiment, the bottom of the isolation structure also extends to the upper surface of the substrate, and the substrate lead-out structure also extends into the substrate.

[0029] In one embodiment, the first alloy layer surrounds the lower surface of the substrate lead-out structure and the sidewall of the bottom of the substrate lead-out structure.

[0030] In one embodiment, the semiconductor device further comprises:

[0031] a second alloy layer on the upper surface of the semiconductor layer and the upper surface of the gate structure;

[0032] a source-drain lead-out structure on part of the second alloy layer on the upper surface of the source-drain region of the semiconductor layer for leading out the source-drain region;

[0033] a gate lead-out structure on part of the second alloy layer on the upper surface of the gate structure for leading out the gate structure.

[0034] The semiconductor device and the preparation method thereof provided above, by forming an opening on the isolation structure of the semiconductor substrate, the bottom of the opening exposes part of the substrate, and then a first alloy layer is formed on the surface of the exposed substrate, and a substrate lead-out structure is formed in the opening and in contact with the first alloy layer, so that the substrate lead-out structure forms a good ohmic contact with the substrate through the first alloy layer, realizes low-resistance electrical connection, and further has better lead-out effect when the back gate is led out, improves the stability and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 Flow chart of the preparation method of the semiconductor device in one embodiment;

[0036] Figure 2 Structural schematic diagram of the semiconductor substrate in one embodiment;

[0037] Figure 3 Structural schematic diagram of the semiconductor device in one embodiment;

[0038] Figure 4 Structural schematic diagram of the semiconductor device in one embodiment;

[0039] Figure 5 Flow chart of step 103 in one embodiment;

[0040] Figure 6 A schematic diagram of a structure of a semiconductor device in an embodiment;

[0041] Figure 7 A flowchart of step 104 in an embodiment;

[0042] Figure 8 A flowchart of a method of manufacturing a semiconductor device in an embodiment;

[0043] Figure 9 A schematic diagram of a structure of a semiconductor device in an embodiment;

[0044] Figure 10 A flowchart of step 203 in an embodiment;

[0045] Figure 11 A schematic diagram of a structure of a semiconductor device in an embodiment;

[0046] Figure 12 A schematic diagram of a structure of a semiconductor device in an embodiment;

[0047] Figure 13 A schematic diagram of a structure of a semiconductor device in an embodiment;

[0048] Figure 14 A schematic diagram of a structure of a semiconductor device in an embodiment. DETAILED DESCRIPTION

[0049] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description in conjunction with the above noted Figures. The Figures are not drawn to scale and are only intended to conceptually illustrate the features of the present application. The application can be implemented in numerous ways, including, but not limited to, the methods and systems described herein. These and other numerous embodiments, aspects and features of the application are described in more detail in the following description.

[0050] It should be understood that the terms "first", "second", etc. can be used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one element from another. They do not imply a relative importance or a specific order between the elements. Thus, a feature defined with a "first", "second" etc. can include at least one of the feature, explicitly or implicitly. In the description of the application, the meaning of "a plurality" is at least two, for example, two, three, etc., unless otherwise specifically defined.

[0051] It should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment.

[0054] Step 101: Provide a semiconductor substrate, which includes a substrate, an insulating buried layer, a semiconductor layer and a gate structure sequentially stacked on the substrate, and the semiconductor substrate also includes an isolation structure extending from the upper surface of the semiconductor layer to the insulating buried layer.

[0055] Please refer to the following for further information. Figure 2 ( Figure 2 In this diagram, 101 is the substrate, 102 is the buried insulating layer, 103 is the semiconductor layer, 104 is the gate structure, and 105 is the isolation structure. The buried insulating layer is disposed within the substrate, the semiconductor layer is disposed on the side of the substrate closest to the buried insulating layer, the gate structure is disposed on the semiconductor layer, and the isolation structure extends from the upper surface of the semiconductor layer through the buried insulating layer. Furthermore, the gate structure is disposed on the source / drain regions of the semiconductor layer and can divide the source / drain regions into source and drain regions, and the isolation structure surrounds the source / drain regions of the semiconductor layer.

[0056] For example, in this embodiment, such as Figure 2 As shown, the gate structure includes a gate oxide layer disposed on the semiconductor layer, a gate layer disposed on the gate oxide layer, and sidewalls disposed on both sides of the gate oxide layer and the gate layer. Figure 2 In this structure, 1041 is the gate oxide layer, 1042 is the gate layer, and 1043 is the sidewall. The shape of the sidewall helps prevent subsequent large-drain injections from getting too close to the channel, thus preventing the channel from becoming too short or even causing source-drain interconnection. For example, in this embodiment, the semiconductor device is an SOI (Silicon-On-Insulator) device, the substrate is a silicon substrate, the buried insulating layer is a buried oxide layer, and the semiconductor layer is the top silicon layer.

[0057] The isolation structure can be used to isolate the semiconductor from silicon, and the material of the isolation structure is an insulating material. Compared to forming openings in other areas of the semiconductor substrate, forming openings in the isolation structure is faster and more convenient. Furthermore, while ensuring isolation performance, it does not occupy the area of ​​other device placement areas on the semiconductor substrate, which is beneficial for effectively utilizing the area of ​​the semiconductor substrate and reducing costs.

[0058] For example, the isolation structure may extend in the depth direction to the interface between the semiconductor layer and the buried insulating layer, or it may extend to the buried insulating layer, or it may extend directly to the substrate. Figure 2 (Taking an isolation structure extending to the substrate as an example). The closer the isolation structure is to the substrate region, the faster and more convenient it is to create a hole.

[0059] For example, the isolation structure is a shallow trench isolation structure, which is formed by depositing, patterning, and etching silicon using a silicon nitride mask, and then filling the trench with deposited oxide to form a shallow trench isolation structure.

[0060] It should be noted that the semiconductor substrate provided in this embodiment can be a pre-fabricated semiconductor substrate, or it can be prepared by sequentially forming an insulating buried layer, a semiconductor layer, an isolation structure, and a gate structure on a substrate according to conventional fabrication methods. In this embodiment, the fabrication method of the semiconductor substrate is not further limited.

[0061] Step 102: Form an opening in the isolation structure, with the bottom of the opening exposing part of the substrate.

[0062] Please refer to the following for further information. Figure 3 ( Figure 3 In the diagram, 100 is a semiconductor substrate, 101 is a substrate, 102 is an insulating buried layer, 103 is a semiconductor layer, 104 is a gate structure, 105 is an isolation structure, 106 is an opening, and 200 is a first alloy layer. The opening 106 is formed to expose part of the substrate so that the first alloy layer 200 can be formed on the contact area in subsequent steps.

[0063] In some embodiments, step 102 includes: an opening 106 extending into the substrate 101, with the bottom wall and bottom sidewall of the opening 106 both exposing portions of the substrate. This allows the first alloy layer 200 to be formed on the substrate surface or in a groove on the substrate, achieving electrical connection with the substrate to form an ohmic contact.

[0064] The size of the aperture 106 can be adjusted according to the integration level of the device and the size of the isolation structure. For example, when the integration level of the device is high and the size of the isolation structure is small, the size of the aperture 106 can be reduced accordingly; when the integration level of the device is low and the size of the isolation structure is large, the size of the aperture 106 can be increased accordingly.

[0065] In some embodiments, such asFigure 3 and Figure 4 As shown in FIG. 6, in the XZ cross section, the longitudinal section shape of the opening can be an open shape with gradually increasing opening. Thus, in the subsequent step, the first alloy layer can be uniformly deposited and spread on the exposed contact area. For example, the longitudinal section shape of the opening is an inverted trapezoidal shape (as shown in FIG. 7). Figure 4 As shown in FIG. 7, in the XZ cross section, the longitudinal section shape of the opening can be an open shape with gradually increasing opening. Thus, in the subsequent step, the first alloy layer can be uniformly deposited and spread on the exposed contact area. For example, the longitudinal section shape of the opening is an inverted trapezoidal shape (as shown in FIG. 7). Figure 3 As shown in FIG. 7, in the XZ cross section, the longitudinal section shape of the opening can be an open shape with gradually increasing opening. Thus, in the subsequent step, the first alloy layer can be uniformly deposited and spread on the exposed contact area. For example, the longitudinal section shape of the opening is an inverted trapezoidal shape (as shown in FIG. 7).

[0066] In some embodiments, there can be multiple openings. Multiple openings are formed on the isolation structure. Thus, in the subsequent step, multiple first alloy layers can be formed, and then multiple substrate lead-out structures are obtained. When the substrate contact area allows, the more the number of substrate lead-out structures, the lower the equivalent resistance.

[0067] It should be noted that the method of forming the opening can adopt a conventional preparation method, for example, the opening can be formed by photolithography and etching process, and in the present embodiment, the method of forming the opening is not further limited.

[0068] Step 103: forming a first alloy layer on the surface of the exposed part of the substrate.

[0069] The first alloy layer has good conductivity, and when the first alloy layer forms part of the surface of the substrate, it can form an ohmic contact with the substrate to achieve a low-resistance electrical connection.

[0070] In some embodiments, the first alloy layer is a silicide alloy layer, which is formed by first forming a metal layer capable of reacting with silicon on the surface of the exposed part of the substrate in the opening, and then performing alloying treatment on the metal layer to make the metal layer react with the silicon of the substrate to form the first alloy layer. Please see Figure 5 , step 103 includes step 1031 and step 1032.

[0071] Step 1031: forming a metal layer on the surface of the exposed part of the substrate.

[0072] The metal material of the metal layer is a metal capable of reacting with silicon and forming an ohmic contact, for example, the material of the metal layer includes one or more of Ni, Co, W, Ta, Ti, Cr, Mo and Zr.

[0073] The metal material of the metal layer can be selected according to the integration level of the wafer, for example, the integration level is high (for example, the integration level is 90 nm), and the Ni metal can be selected, and the integration level is relatively low (for example, the integration level is higher than 90 nm), and the Co metal can be selected.

[0074] The metal layer can be formed by a vacuum electron beam evaporation method, or can be formed by other methods, such as a radio frequency magnetron sputtering technique, thermal evaporation, etc. The forming method of the metal layer is not limited in the embodiment.

[0075] It should be noted that the thickness of the metal layer is not limited in the embodiment. The thickness of the metal layer can be adjusted adaptively by a person skilled in the art according to different metal materials, different device integration degrees, and different sizes of the isolation structure, etc.

[0076] Step 1032: alloying treatment is performed on the metal layer, so that the metal layer reacts with the exposed part of the substrate to form a first alloy layer.

[0077] The alloying treatment on the metal layer includes: annealing treatment is performed on the metal layer under a preset temperature condition, so that the metal layer and the exposed part of the substrate silicon react to generate a silicide alloy layer with an ohmic characteristic, and the silicide alloy layer partially penetrates into the substrate. On the one hand, the substrate directly reacts with the metal layer, which can make the substrate and the metal layer penetrate each other, strengthen the adhesion between the substrate and the metal layer, and optimize the electrical connection performance and the stability of the combination between the substrate and the first alloy layer. On the other hand, the substrate directly reacts with the metal layer to generate the first alloy layer, which can also save reaction materials and reduce costs.

[0078] The preset temperature is set to different temperature ranges according to the selection of the metal material, and is usually in the range of 800°-1000°. For example, when the material of the metal layer is Co, the preset temperature can be set to 850°-900°.

[0079] On the one hand, the substrate directly reacts with the metal layer, which can make the substrate and the metal layer penetrate each other, strengthen the adhesion between the substrate and the metal layer, and optimize the electrical connection performance and the stability of the combination between the substrate and the first alloy layer. On the other hand, the substrate directly reacts with the metal layer to generate the first alloy layer, which can also save reaction materials and reduce costs.

[0080] It should be noted that the thickness of the first alloy layer is not limited in the embodiment. The thickness of the first alloy layer can be adjusted adaptively by a person skilled in the art according to different alloy materials, different device integration degrees, and different sizes of the isolation structure, etc.

[0081] Step 104: a substrate lead-out structure in contact with the first alloy layer is formed in the opening.

[0082] The substrate lead-out structure (see Figure 3 and Figure 6 , Figure 6The substrate lead-out structure 300 is used for leading out the substrate. The substrate lead-out structure 300 can form a good ohmic contact with the substrate by being in contact with the first alloy layer, realize a low-resistance electrical connection, and thus can effectively lead out the substrate to the circuit to form a substrate charge discharge path and prevent the back gate effect from affecting the operation of the device.

[0083] The material of the substrate lead-out structure can be a metal material, for example, tungsten metal. When the tungsten metal is in direct contact with the substrate, there is a problem of a large contact resistance between the substrate surface and the tungsten metal, which affects the effect of the back gate lead-out. When the tungsten metal is in contact with the substrate through the first alloy layer, a good ohmic contact can be formed with the substrate, a low-resistance electrical connection is realized, and thus the back gate lead-out has a better lead-out effect.

[0084] In some embodiments, the substrate lead-out structure is electrically connected to the circuit on the upper surface of the semiconductor layer to form a silicon charge discharge path of the substrate. Thus, the substrate charge is discharged through the circuit on the upper surface of the semiconductor layer, and the back gate effect is prevented from affecting the operation of the device.

[0085] In some embodiments, please refer to Figure 7 As shown in FIG. 1, step 104 includes:

[0086] Step 1041: Form an insulating medium layer, and the insulating medium layer fills the opening.

[0087] The insulating medium layer is formed on the isolation structure and the first alloy layer and completely covers the semiconductor substrate, fills the opening, and is used for forming a substrate lead-out hole to fill a conductive material in a subsequent step, and is also used for isolating and protecting the device from external electrical contact interference. For different application environments, the material of the insulating medium layer can be selected from silicon dioxide, polyimide, or other materials with electrical insulation properties.

[0088] Step 1042: Form a substrate lead-out hole in the insulating medium layer in the opening, and the bottom of the substrate lead-out hole exposes part of the first alloy layer.

[0089] The substrate lead-out hole is used for exposing the first alloy layer and filling a conductive medium to form a substrate lead-out structure in contact with the first alloy layer, so that the substrate lead-out structure is electrically connected to the first alloy layer.

[0090] The substrate lead-out hole penetrates to the surface of the first alloy layer or penetrates part of the first alloy layer, so that the substrate lead-out structure can be formed on the surface of the first alloy layer or on a groove of the first alloy layer to realize electrical connection with the first alloy layer to form an ohmic contact.

[0091] The size of the substrate lead-out hole can be adjusted according to the integration of the device and the size of the isolation structure. For example, when the integration of the device is high and the size of the isolation structure is small, the size of the substrate lead-out hole is correspondingly small; when the integration of the device is low and the size of the isolation structure is large, the size of the substrate lead-out hole can be correspondingly large.

[0092] In some embodiments, when there are multiple openings, there are also multiple substrate lead-out holes. The multiple substrate lead-out holes correspond one-to-one to the positions of the multiple openings. Thus, multiple substrate lead-out structures can be formed in subsequent steps. When the area of the substrate contact region allows, the more the number of substrate lead-out structures, the lower the equivalent resistance.

[0093] It should be noted that the method of forming the substrate lead-out hole can use a conventional preparation method. For example, the substrate lead-out hole can be formed by photolithography and etching process. In this embodiment, the method of forming the substrate lead-out hole is not limited further.

[0094] Step 1043: filling the conductive medium in the substrate lead-out hole to form a substrate lead-out structure.

[0095] The substrate lead-out structure is used to lead out the substrate. By contacting the first alloy layer, the substrate lead-out structure can form a good ohmic contact with the substrate, realize low-resistance electrical connection, and thus effectively lead out the substrate to the circuit to form a substrate charge discharge path and prevent the back gate effect from affecting the operation of the device.

[0096] The conductive medium can be a metal material, such as tungsten metal. When the tungsten metal directly contacts the substrate, there is a problem of large contact resistance between the substrate surface and the tungsten metal, which affects the back gate lead-out. When the tungsten metal contacts the substrate through the first alloy layer, a good ohmic contact can be formed between the substrate and the tungsten metal, realizing low-resistance electrical connection, and thus having a better lead-out effect when the back gate is led out.

[0097] The preparation method provided in this embodiment forms an opening on the isolation structure of the semiconductor substrate, exposes part of the substrate at the bottom of the opening, forms a first alloy layer on the surface of the exposed part of the substrate, and forms a substrate lead-out structure in the opening that contacts the first alloy layer. Thus, the substrate lead-out structure forms a good ohmic contact with the substrate through the first alloy layer, realizes low-resistance electrical connection, and thus has a better lead-out effect when the back gate is led out, improving the stability and reliability of the device.

[0098] Figure 8 The flowchart of the preparation method of the semiconductor device of an embodiment.

[0099] Step 201: providing a semiconductor substrate, the semiconductor substrate comprising a substrate, an insulating buried layer, a semiconductor layer and a gate structure which are sequentially stacked on the substrate, and further comprising an isolation structure penetrating through the semiconductor layer from the upper surface of the semiconductor layer to the insulating buried layer.

[0100] In step 201, refer to the related description of the above-mentioned embodiment 101, which will not be repeated here.

[0101] Step 202: forming an opening on the isolation structure, the bottom of the opening exposing part of the substrate.

[0102] In step 202, refer to the related description of the above-mentioned embodiment 102, which will not be repeated here.

[0103] Step 203: forming a first alloy layer on the surface of the exposed part of the substrate, and forming a second alloy layer on the upper surface of the semiconductor layer and the upper surface of the gate structure (see Figure 9 , Figure 9 In FIG. 400, the second alloy layer, wherein 401 is the second alloy layer on the upper surface of the semiconductor layer, and 402 is the second alloy layer on the upper surface of the gate structure), thereby simplifying the steps and improving the preparation efficiency.

[0104] In the first alloy layer, refer to the related description of the above-mentioned embodiment, which will not be repeated here.

[0105] The second alloy layer has good electrical conductivity, and when the second alloy layer covers the semiconductor layer and the gate structure, it can form ohmic contact with the semiconductor layer and the gate structure respectively, and realize low-resistance electrical connection.

[0106] In some embodiments, the first alloy layer and the second alloy layer are silicide alloy layers. By forming a metal layer capable of reacting with silicon in the semiconductor layer and the gate structure on the surface of the exposed part of the substrate in the opening, the semiconductor layer and the gate structure, and then alloying the metal layer, the metal layer reacts with the silicon in the substrate to form the first alloy layer, and the metal layer reacts with the silicon in the semiconductor layer and the gate structure to form the second alloy layer. As Figure 10 shown, step 203 includes:

[0107] Step 2031: forming a metal layer on the surface of the exposed part of the substrate in the opening, the semiconductor layer and the gate structure.

[0108] In the metal layer, refer to the related description in the above-mentioned embodiment, which will not be repeated here.

[0109] Step 2032: alloying the metal layer to make the metal layer react with the silicon in the substrate to form the first alloy layer, and the metal layer react with the contact area of the semiconductor layer and the gate structure to form the second alloy layer.

[0110] The alloying treatment can be annealing treatment of the metal layer under preset temperature conditions, so that the metal layer and the substrate silicon react to form a first alloy layer, and the metal layer and the silicon on the semiconductor layer and the gate structure react to form a second alloy layer. The alloying treatment will be described in detail in the related description of the above embodiments, and will not be described here.

[0111] On the one hand, the direct reaction of the semiconductor layer and the gate structure with the metal layer can make the semiconductor layer and the gate structure and the metal layer penetrate each other, strengthen the adhesion between the semiconductor layer and the gate structure and the metal layer, and optimize the electrical connection performance and the stability of the combination between the semiconductor layer and the gate structure and the second alloy layer. On the other hand, the direct reaction of the semiconductor layer and the gate structure with the metal layer to form the second alloy layer can also save reaction materials and reduce costs.

[0112] The alloying treatment can be annealing treatment of the metal layer under preset temperature conditions, so that the metal layer and the substrate silicon react to form a first alloy layer, and the metal layer and the silicon on the semiconductor layer and the gate structure react to form a second alloy layer. The alloying treatment will be described in detail in the related description of the above embodiments, and will not be described here.

[0113] It should be noted that the thickness of the second alloy layer is not limited in this embodiment. According to different alloy materials, different device integration levels, and different sizes of the isolation structure, the thickness of the second alloy layer can be adjusted adaptively by those skilled in the art.

[0114] Step 204: forming a substrate lead-out hole in the insulating medium layer in the opening, forming a source / drain lead-out hole in the insulating medium layer above the source / drain region of the semiconductor layer, and forming a gate lead-out hole in the insulating medium layer above the gate structure, wherein the bottom of the substrate lead-out hole exposes part of the first alloy layer, the bottom of the source / drain lead-out hole exposes part of the second alloy layer, and the bottom of the gate lead-out hole exposes part of the second alloy layer (see Figure 11 , Figure 11 , wherein 600 is the insulating medium layer, 601 is the substrate lead-out hole, 602 is the source / drain lead-out hole, and 603 is the gate lead-out hole.

[0115] The semiconductor layer source / drain region is located on the active region on both sides of the gate structure, and the isolation structure is located on the side of the semiconductor layer source / drain region away from the gate structure, that is, the side of the source / drain region is the gate structure, and the other side of the source / drain region is the isolation structure. The active regions of two adjacent devices are isolated by the isolation structure.

[0116] The substrate lead-out hole will be described in detail in the related description of the above embodiments, and will not be described here.

[0117] The second alloy layer exposed at the bottom of the source-drain lead-out hole is used to fill the conductive medium to form a source-drain lead-out structure, so that the subsequent source-drain lead-out structure is electrically connected with the second alloy layer. The second alloy layer exposed at the bottom of the gate lead-out hole is used to fill the conductive medium to form a gate lead-out structure, so that the subsequent gate lead-out structure is electrically connected with the second alloy layer.

[0118] The source-drain lead-out hole and the gate lead-out hole penetrate to the surface of the second alloy layer or penetrate part of the second alloy layer, so that part of the bottom of the source-drain lead-out hole and part of the bottom of the gate lead-out hole can expose the second alloy layer, or the entire bottom of the source-drain lead-out hole and the entire bottom of the gate lead-out hole can expose the second alloy layer. After filling the conductive medium in the source-drain lead-out hole and the gate lead-out hole, a better ohmic contact between the second alloy layer can be achieved.

[0119] The size of the source-drain lead-out hole and the gate lead-out hole can be adjusted according to the integration of the device and the size of the semiconductor layer and the gate structure. For example, when the integration of the device is high and the size of the semiconductor layer and the gate structure is small, the size of the source-drain lead-out hole and the gate lead-out hole can be correspondingly reduced. When the integration of the device is low and the size of the semiconductor layer and the gate structure is large, the size of the source-drain lead-out hole and the gate lead-out hole can be correspondingly increased.

[0120] In some embodiments, there can be multiple source-drain lead-out holes and gate lead-out holes. Therefore, multiple source-drain lead-out structures and gate lead-out structures can be formed in subsequent steps. When the area of the semiconductor layer and the size of the gate structure allow, the more the number of source-drain lead-out structures and gate lead-out structures, the lower the equivalent resistance.

[0121] It should be noted that the method for forming the source-drain lead-out hole and the gate lead-out hole can adopt a conventional preparation method. For example, the substrate lead-out hole can be formed by photolithography and etching process. In the present embodiment, the method for forming the source-drain lead-out hole and the gate lead-out hole is not limited further.

[0122] The insulating medium layer is formed on the isolation structure, the first alloy layer and the second alloy layer and completely covers the semiconductor substrate, fills the opening, and is used to form the substrate lead-out hole, the source-drain lead-out hole and the gate lead-out hole to fill the conductive material in subsequent steps, and is also used to isolate and protect the device to avoid external electrical contact interference. For different application environments, the material of the insulating medium layer can be selected from silicon dioxide, polyimide or other materials with electrical insulation properties.

[0123] Step 205: Fill the conductive medium in the substrate lead-out hole, the source-drain lead-out hole and the gate lead-out hole to form a substrate lead-out structure 300, a source-drain lead-out structure 501 and a gate lead-out structure 502 (see Figure 12 ,Figure 12 The middle 501 is a source-drain lead-out structure, and the 502 is a gate lead-out structure.

[0124] The substrate lead-out structure is described above and will not be repeated here.

[0125] The source-drain lead-out structure is used to lead out the source-drain region, and the gate lead-out structure is used to lead out the gate structure. The source-drain lead-out structure can form a good ohmic contact with the source-drain region of the semiconductor layer through contact with the second alloy layer, and can realize low-resistance electrical connection, thereby effectively leading out the source-drain region. The gate lead-out structure can form a good ohmic contact with the gate structure through contact with the second alloy layer, and can realize low-resistance electrical connection, thereby effectively leading out the gate structure.

[0126] The conductive medium can be a metal material, such as tungsten metal. When the tungsten metal is in direct contact with the source-drain region and the gate structure of the semiconductor layer, there is a problem of large contact resistance between the surface of the semiconductor layer and the surface of the gate structure and the tungsten metal, which affects the lead-out effect. When the tungsten metal is in contact with the source-drain region and the gate structure of the semiconductor layer through the second alloy layer, a good ohmic contact can be formed between the tungsten metal and the source-drain region and the gate structure of the semiconductor layer, realizing low-resistance electrical connection, and thereby improving the lead-out effect.

[0127] The preparation method provided in this embodiment exposes the contact area of the substrate by forming an opening that penetrates the substrate on the isolation structure of the semiconductor substrate, forms a first alloy layer on the opening to cover the contact area, and then forms a substrate lead-out structure in contact with the first alloy layer on the opening, so that the substrate lead-out structure forms a good ohmic contact with the substrate through the first alloy layer, realizes low-resistance electrical connection, and thereby has a better lead-out effect when the back gate is led out, improving the stability and reliability of the device. By forming a second alloy layer on the semiconductor layer and the gate structure, and then forming a second conductive structure on the second alloy layer, the second conductive structure forms a good ohmic contact with the semiconductor layer and the gate structure through the second alloy layer, realizes low-resistance electrical connection, and thereby has a better lead-out effect when the semiconductor layer and the gate structure are led out, further improving the stability and reliability of the device. Moreover, by simultaneously forming an alloy layer on the semiconductor layer, the gate structure, and the exposed part of the substrate, and simultaneously forming the substrate lead-out structure, the source-drain lead-out hole, and the gate lead-out hole, the overall number of photolithography times is not increased compared to the existing preparation method, and the steps are also simplified, improving the preparation efficiency.

[0128] It should be understood that although the steps in the flowcharts in the above embodiments are shown in sequence according to the arrows, the steps are not necessarily executed in the order of the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, at least some of the steps in the above flowcharts can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.

[0129] Figure 13 A structure diagram of a semiconductor device prepared by a preparation method according to an embodiment is shown. Figure 1 A structure diagram of a semiconductor device prepared by a preparation method according to an embodiment is shown.

[0130] In this embodiment, the semiconductor device includes a semiconductor substrate, a substrate lead-out structure 200, and a first alloy layer 300.

[0131] The semiconductor substrate includes a substrate 101, an insulating buried layer 102, a semiconductor layer 103, and a gate structure 104 which are sequentially stacked on the substrate 101, and further includes an isolation structure 105 which sequentially penetrates the semiconductor layer 103 and the insulating buried layer 102 from the upper surface of the semiconductor layer 103.

[0132] The substrate lead-out structure 200 is electrically connected to the substrate 101 after penetrating the isolation structure 105.

[0133] The first alloy layer 300 is located on the surface of the substrate 101 at the bottom of the substrate lead-out structure 200, and is used to electrically connect the substrate lead-out structure 200 and the substrate 101.

[0134] In this embodiment, the semiconductor substrate, the substrate lead-out structure 200, and the first alloy layer 300 are described above, and will not be described here.

[0135] In some embodiments, the bottom of the isolation structure 105 also extends to the upper surface of the substrate 101, and the substrate lead-out structure 200 also extends into the substrate 101. The more the isolation structure 105 approaches the substrate 101, the faster and more convenient the opening is.

[0136] In some embodiments, the first alloy layer 300 surrounds the lower surface of the substrate lead-out structure 200 and the sidewall at the bottom of the substrate lead-out structure 200. Thus, the first alloy layer 300 can realize the electrical connection between the lower surface of the substrate lead-out structure 200 and the sidewall at the bottom of the substrate lead-out structure 200 and the substrate to form an ohmic contact.

[0137] The semiconductor device provided in the embodiment comprises a semiconductor substrate, a substrate lead-out structure 200 and a first alloy layer 300. The semiconductor substrate comprises a substrate 101, an insulating buried layer 102, a semiconductor layer 103 and a gate structure 104 which are sequentially arranged on the substrate 101. The semiconductor substrate further comprises an isolation structure 105 which sequentially penetrates the semiconductor layer 103 and the insulating buried layer 102 from the upper surface of the semiconductor layer 103. The substrate lead-out structure 200 is electrically connected with the substrate 101 after penetrating the isolation structure 105. The first alloy layer 300 is located on the surface of the substrate 101 at the bottom of the substrate lead-out structure 200, and is used to electrically connect the substrate lead-out structure 200 and the substrate 101. The substrate lead-out structure 200 forms a good ohmic contact with the substrate 101 through the first alloy layer 300, realizes low-resistance electrical connection, and further has a better lead-out effect when the back gate is led out, thereby improving the stability and reliability of the device.

[0138] Figure 14 A structure schematic diagram of a semiconductor device prepared by a preparation method according to an embodiment is shown. Figure 8 A structure schematic diagram of a semiconductor device prepared by a preparation method according to an embodiment is shown.

[0139] In the embodiment, the semiconductor device comprises a semiconductor substrate, a substrate lead-out structure 200, a first alloy layer 300, a second alloy layer 400, a source-drain lead-out structure 501 and a gate lead-out structure 502.

[0140] The semiconductor substrate, the substrate lead-out structure 200 and the first alloy layer 300 are described in the above embodiments, and will not be described here.

[0141] The second alloy layer 400 is arranged on the upper surface of the semiconductor layer 103 and the upper surface of the gate structure 104.

[0142] The source-drain lead-out structure 501 is arranged on the part of the second alloy layer 400 on the upper surface of the source-drain region of the semiconductor layer 103, and is used to lead out the source-drain region. The gate lead-out structure 502 is arranged on the part of the second alloy layer 400 on the upper surface of the gate structure 104, and is used to lead out the gate structure 104.

[0143] In the embodiment, the semiconductor substrate, the substrate lead-out structure 200, the first alloy layer 300, the second alloy layer 400, the source-drain lead-out structure 501 and the gate lead-out structure 502 are described in the above embodiments, and will not be described here.

[0144] The semiconductor device provided by the embodiment comprises a semiconductor substrate, a substrate lead-out structure 200, a first alloy layer 300, a second alloy layer 400, a source-drain lead-out structure 501 and a gate lead-out structure 502. The semiconductor substrate comprises a substrate 101, an insulating buried layer 102, a semiconductor layer 103 and a gate structure 104 which are sequentially arranged on the substrate 101. The semiconductor substrate further comprises an isolation structure 105 which sequentially penetrates the semiconductor layer 103 and the insulating buried layer 102 from the upper surface of the semiconductor layer 103. The substrate lead-out structure 200 is electrically connected with the substrate 101 after penetrating the isolation structure 105. The first alloy layer 300 is arranged on the surface of the substrate 101 at the bottom of the substrate lead-out structure 200 for electrically connecting the substrate lead-out structure 200 and the substrate 101. The second alloy layer 400 is arranged on the upper surface of the semiconductor layer 103 and the upper surface of the gate structure 104. The source-drain lead-out structure 501 is arranged on the part of the second alloy layer 400 on the upper surface of the source-drain region of the semiconductor layer 103 for leading out the source-drain region. The gate lead-out structure 502 is arranged on the part of the second alloy layer 400 on the upper surface of the gate structure 104 for leading out the gate structure 104. On the one hand, the substrate lead-out structure 200 forms a good ohmic contact with the substrate 101 through the first alloy layer 300, realizes low-resistance electrical connection, and thus has a better lead-out effect when leading out the back gate, and improves the stability and reliability of the device. On the other hand, the source-drain lead-out structure 501 and the gate lead-out structure 502 form a good ohmic contact with the semiconductor layer 103 and the gate structure 104 through the second alloy layer 400, realize low-resistance electrical connection, and thus have a better lead-out effect when leading out the semiconductor layer 103 and the gate structure 104, and further improve the stability and reliability of the device.

[0145] Any combination of the technical features in the above-described embodiments can be made, and to make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they shall be considered as the scope of the description.

[0146] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as the limitation on the patent scope of the present application. It shall be pointed out that, for the ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate comprising a substrate, an insulating buried layer, a semiconductor layer and a gate structure sequentially stacked on the substrate, and the semiconductor substrate further comprising an isolation structure extending from the upper surface of the semiconductor layer to the insulating buried layer; An opening is formed within the isolation structure, the opening extending into the substrate, and both the bottom wall and the bottom sidewall of the opening are partially exposed within the substrate. A first alloy layer is formed on the surface of the substrate in the exposed portion; An insulating dielectric layer is formed, and the insulating dielectric layer fills the opening; A substrate lead-out hole is formed in the insulating dielectric layer within the opening, and a portion of the first alloy layer is exposed at the bottom of the substrate lead-out hole; A conductive dielectric is filled into the substrate lead-out hole to form a substrate lead-out structure.

2. The preparation method according to claim 1, characterized in that, The process of forming a first alloy layer on the surface of the substrate in the exposed portion further includes: While forming a first alloy layer on the surface of the exposed portion of the substrate, a second alloy layer is formed on the upper surface of the semiconductor layer and the upper surface of the gate structure.

3. The preparation method according to claim 2, characterized in that, The substrate lead-out structure formed in the opening and in contact with the first alloy layer further includes: An insulating dielectric layer is formed, which covers the isolation structure, the first alloy layer, and the second alloy layer; A substrate lead-out hole is formed in the insulating dielectric layer within the opening; a source / drain lead-out hole is formed in the insulating dielectric layer above the source / drain region of the semiconductor layer; and a gate lead-out hole is formed in the insulating dielectric layer above the gate structure. The bottom of the substrate lead-out hole exposes a portion of the first alloy layer; the bottom of the source / drain lead-out hole exposes a portion of the second alloy layer; and the bottom of the gate lead-out hole exposes a portion of the second alloy layer. The substrate lead-out holes, the source / drain lead-out holes, and the gate lead-out holes are all filled with conductive dielectric to form a substrate lead-out structure, a source / drain lead-out structure, and a gate lead-out structure.

4. The preparation method according to claim 1, characterized in that, The substrate lead-out structure is electrically connected to a circuit located on the upper surface of the semiconductor layer to form a silicon charge discharge path for the substrate.

5. A semiconductor device, characterized in that, include: A semiconductor substrate, the semiconductor substrate comprising a substrate, an insulating buried layer, a semiconductor layer and a gate structure sequentially stacked on the substrate, the semiconductor substrate further comprising an isolation structure that extends from the upper surface of the semiconductor layer through the semiconductor layer and the insulating buried layer sequentially; A substrate lead-out structure extends through the isolation structure and is electrically connected to the substrate; the bottom of the isolation structure also extends to the upper surface of the substrate, and the substrate lead-out structure also extends into the substrate; an opening is provided on the isolation structure. The bottom of the opening exposes a portion of the substrate, and a substrate lead-out hole is formed in the insulating dielectric layer filled in the opening; A first alloy layer, located on the substrate surface at the bottom of the substrate lead-out structure, is used to electrically connect the substrate lead-out structure and the substrate; Wherein, the bottom of the substrate lead-out hole exposes a portion of the first alloy layer, and the substrate lead-out structure is located within the substrate lead-out hole.

6. The semiconductor device according to claim 5, characterized in that, The first alloy layer surrounds the lower surface of the substrate lead-out structure and the bottom sidewall of the substrate lead-out structure.

7. The semiconductor device according to claim 5, characterized in that, The semiconductor device further includes: A second alloy layer is located on the upper surface of the semiconductor layer and the upper surface of the gate structure; A source / drain lead-out structure is located on a portion of the second alloy layer on the upper surface of the source / drain region of the semiconductor layer, for leading out the source / drain region; A gate lead-out structure is located on a portion of the second alloy layer on the upper surface of the gate structure, for leading out the gate structure.

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