Semiconductor failure detection structure and method of detecting the same

Abstract

The application provides a semiconductor failure detection structure and a detection method thereof, which are applied to a semiconductor device failure detection process. The semiconductor failure detection method comprises the following steps: a reference layer is arranged in a preset range of a wafer to be detected; a wafer image of the wafer to be detected corresponding to the reference layer is obtained; the wafer image is compared with a detection standard image; and position information and analysis results of failure in the wafer to be detected are obtained according to the reference layer. In the embodiment of the present application, the reference layer is similar to a metal material, the reference layer is composed of a plurality of minimum unit reference blocks arranged regularly, and in particular, the reference layer composed of the reference blocks is arranged in a rice shape or a T shape. The design of the periphery of the test structure and the upper and lower dummy structures is optimized. On the basis of not affecting various test structures with different functions, not only is it helpful to form clearer and higher-contrast test structure image, but also the accuracy of failure analysis positioning and the success rate and efficiency of physical property failure analysis are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor failure detection, in particular to a semiconductor failure detection structure and a detection method thereof. BACKGROUND

[0002] The increasing requirement of semiconductor integration poses a challenge to semiconductor device failure analysis. The prior art applies failure positioning technologies such as EMMI / OBIRCH / Thermal EMMI to detect abnormal signals of failure positions, commonly known as "hot spots". Then, according to the relative position information of the hot spots and the optical image of the analyzed region, physical failure analysis of the position can be performed to find the abnormal cause.

[0003] However, in the prior art, whether it is a single device or a single layer structure, the physical position of failure positioning is inaccurate due to the large area or long strip design of these structures. In addition, during the failure detection process, dummy structures are set in the layers not involved in the structure. The over-dense dummy will interfere with the detection of failure positioning, and the over-dense dummy will also block the detection of failure analysis signals, affecting the clarity of the optical image, and further causing inaccurate positioning of the physical position of the hot spot.

[0004] Therefore, a new semiconductor failure detection scheme is needed. SUMMARY

[0005] Therefore, the embodiments of the present application provide a semiconductor failure detection structure and a detection method thereof, which are applied to the semiconductor device failure positioning process.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] The embodiments of the present application provide a semiconductor failure detection method, which is applied to the semiconductor device failure positioning detection process, and the semiconductor failure detection method comprises:

[0008] A reference layer is set in a preset range of a wafer to be detected;

[0009] A wafer image of the wafer to be detected corresponding to the reference layer is obtained;

[0010] The wafer image is compared with a detection standard image, and position information and analysis results of failure in the wafer to be detected are obtained according to the reference layer.

[0011] The embodiments of the present application also provide a semiconductor failure detection structure, which is applied to the semiconductor device failure detection method described in any of the technical solutions of the present application for failure positioning, and the semiconductor failure detection structure comprises:

[0012] A reference layer is added in a preset range of a wafer to be detected, and the reference layer is used for reflecting part of the irradiation light of the wafer to be detected when the wafer to be detected is scanned, and is also used for determining the position information of the failure in the wafer to be detected.

[0013] Compared with the prior art, the at least one technical scheme adopted by the embodiments of the present specification can achieve the beneficial effects at least including:

[0014] By setting the reference layer for assisting the physical positioning of the hot spot of the wafer to be detected, the design of the dummy structure around the test structure and the upper and lower layers of the test structure is optimized without affecting the test structure of various functions, so that more accurate hot spot positioning is realized, the precision of the physical positioning of the hot spot is improved without complex detection methods and improvement of equipment, and the accuracy of failure analysis positioning and the success rate and efficiency of physical property failure analysis are greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 is a schematic diagram of the wafer structure in the prior art failure positioning detection;

[0017] Figure 2 is a schematic diagram of wafer hot spot failure positioning in the prior art;

[0018] Figure 3A is a defect schematic diagram of wafer hot spot failure positioning in the prior art;

[0019] Figure 3B is a schematic diagram of the failure hot spot being shielded by dense dunny in the prior art;

[0020] Figure 4 is a flowchart of the semiconductor failure detection method provided by the embodiments of the present specification;

[0021] Figure 5 is a schematic diagram of the semiconductor failure detection structure provided by the embodiments of the present specification Figure 1 ;

[0022] Figure 6 is a schematic diagram of the semiconductor front surface failure detection provided by the embodiments of the present specification;

[0023] Figure 7 is a schematic diagram of the semiconductor back surface failure detection provided by the embodiments of the present specification;

[0024] Figure 8 is a schematic diagram of a reference block provided by embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] The embodiments of the present application will be described in detail below with reference to the drawings.

[0026] The above examples are merely illustrative of the embodiments of the present application, and non-limiting. Numerous modifications and adaptations thereof will be apparent to those skilled in the art without departing from the spirit and scope of the present application. Therefore, the scope of the present application is not limited to the specific embodiments described herein, but only defined by the claims which follow, and their equivalents.

[0027] It is to be understood that the foregoing description is merely illustrative of various aspects of embodiments, and that numerous and various modifications can be made without departing from the spirit and scope of the present application. Notably, aspects described hereinafter in the general description of the application can be implemented in any of the embodiments without departing from the scope of the present application, and aspects described in the general description of the application can be implemented independently of any other aspects likewise without departing from the scope of the present application. No limitation is placed on the scope of the application, which is to be only limited as defined by the claims which follow and their equivalents.

[0028] It is also to be understood that the following description is merely illustrative of the embodiments of the present application and that no limitations are placed on the scope of the present application since the scope of the present application is defined by the claims which follow and their equivalents.

[0029] In addition, in the following description, specific details are provided to thoroughly understand examples. However, one of ordinary skill in the art will understand that the examples can be practiced without these specific details.

[0030] The prior art applies failure location technologies such as EMMI / OBIRCH / Thermal EMMI to detect abnormal signals of failure location, commonly known as "hot spots". However, whether for single device or single layer structure, the physical location of failure location is inaccurate due to the large area or long strip design of these structures. For example, Figure 3A Figure 2 is a partial enlarged view of the superimposed image of the back failure location hot spot signal and the optical image, wherein the largest black dot indicates the failure hot spot. The hot spot location is not accurately positioned by size measurement in the prior art, with a large deviation. In addition, dummy structures are set at levels not involved in the structure during the failure detection process, such as Figure 3B The dummy is too dense to interfere with the detection of failure location, and the too dense dummy also blocks the detection of failure analysis signals, affects the clarity of the optical image, and further causes the inaccuracy of the positioning of the physical location of the hot spot.

[0031] Therefore, the inventors found that when the front or back of the chip is scanned by the infrared laser system of the micro-light microscope, the infrared laser can penetrate the substrate silicon material, polycrystalline silicon and dielectric layer material, but will be reflected back when encountering metal material, so that the structure relatively below the metal material covered will not be displayed. Based on this, a reference layer similar to the metal material is set in the preset range of the wafer to be detected to obtain a high-contrast pattern image of the wafer to be detected, thereby improving the accuracy of the positioning of the failure point at the moment of failure location of the semiconductor device wafer.

[0032] Based on this, the embodiments of the present specification propose a new semiconductor failure detection scheme. As shown in Figure 1 Figure 1 shows a wafer structure, which includes an active area AA and a polycrystalline silicon Poly. Figure 2 Figure 2 shows that the hot spot information of the failure point is superimposed on the test structure pattern image based on the basic principle of the micro-light microscope to obtain the location information of the failure point, but due to the large area or long strip design of these structures, the physical location of failure location is inaccurate. For example, Figure 5 The present specification sets a reference layer similar to a metal material for scanning by the infrared laser system of the micro-light display microscope, the reference layer reflects light so that the structure relatively below the reference layer covered will not be displayed, which helps to form a clearer and higher-contrast test structure pattern image, so that the hot spot information of the failure point is superimposed on the test structure pattern image, and the positioning location information of the failure point can be more accurately obtained according to the reference layer.

[0033] The technical solutions provided by the embodiments of the present application are described below in conjunction with the drawings.

[0034] As shown in Figure 4As shown in the figure, this specification provides a semiconductor failure detection method, which is applied to the failure location process of semiconductor devices. The semiconductor failure detection method includes steps S410 to S430.

[0035] In step S410, a reference layer is set within a preset range of the wafer to be inspected. The wafer to be inspected is a semiconductor device with defects, which appears as bright spots under a low-light microscope.

[0036] This specification describes a method for obtaining high-resolution images of a chip by scanning its front or back using a low-light microscope and infrared laser system. Based on the fundamental principles of low-light microscopy, the hotspot signals of the failure points are superimposed onto the image of the test structure to determine the location of specific failure defects. This embodiment not only employs the above method but also utilizes a reference layer to enhance the contrast of the image. Specifically, the low-light microscope scans the front or back of the chip using an infrared laser system. Infrared laser light can penetrate substrate silicon, polysilicon, and dielectric materials, but it is reflected back upon encountering the reference layer. Therefore, structures relatively below the reference layer are not displayed. Thus, during the process of superimposing the hotspot information of the failure points onto the image, the reference layer further helps to more accurately determine the location of the failure points. Therefore, a reference layer is set within a preset range on the wafer to be tested before scanning the chip using the low-light microscope and infrared laser system. Specifically, for failure detection on the front of the wafer, the reference layer is set on the front of the wafer. For failure detection on the back of the wafer, the reference layer is set within a specific range near the back of the wafer. Alternatively, reference layers can be set on both the front and back of the wafer. This allows for the acquisition of higher-contrast graphic images, ultimately enabling the determination of the location information of the failure in the wafer under inspection.

[0037] Step S420: Obtain the wafer image corresponding to the wafer to be inspected, which is set by the reference layer.

[0038] In conjunction with the above embodiments, during the detection of failures on the front side of the wafer under test, an image of the front wafer is obtained by scanning the front side of the wafer with the reference layer set thereon using a low-light microscope infrared laser system. During the detection of failures on the back side of the wafer under test, an image of the back side of the wafer with the reference layer set thereon is obtained by scanning the back side of the wafer under test using a low-light microscope infrared laser system. Alternatively, both the front and back wafer images of the wafer under test can be obtained. This provides comparative graphic images for locating the failure points on the wafer under test.

[0039] S430, comparing the wafer image with a detection standard image to obtain the position information of the failure and analysis results in the wafer to be detected according to the reference layer. The detection standard image includes a wafer standard image containing a preset reference layer. For example, a reference layer is arranged on the wafer back surface near the wafer polysilicon Poly layer to obtain the back surface wafer image. For another example, a reference layer is arranged on the wafer front surface near the wafer bottom metal layer to obtain the front surface wafer image. In some embodiments, a micro-light microscope, a focused ion beam microscope, and a transmission electron microscope can be used to obtain the corresponding wafer image. The analysis results include at least one of the following: open circuit, short circuit, burnout, leakage, functional failure, electrical parameter drift, and unstable failure.

[0040] In combination with the above embodiments, in the front surface failure detection of the wafer to be detected, the obtained front surface wafer image is superimposed on the detection standard image for comparison, and more accurate failure positioning is achieved according to the position of the reference layer. In the back surface failure detection of the wafer to be detected, the obtained back surface wafer image is superimposed on the detection standard image for comparison, and more accurate position information of the failure and analysis results are obtained according to the position of the reference layer.

[0041] In the present specification, the reference layer of similar metal material is used for scanning by the micro-light display mirror infrared laser system. The reference layer reflects the optical fiber, so that the structure below the reference layer is not displayed, which helps to form a clearer and higher-contrast test structure image. Therefore, the hotspot information of the failure point is superimposed on the test structure image, and the positioning position information of the failure point can be more accurately obtained according to the reference layer.

[0042] In some embodiments, the reference layer is arranged in a preset range of the wafer to be detected, including: one or more first metal layers are arranged on the front surface of the wafer to be detected; and a second metal layer is arranged on the back surface of the wafer to be detected. The first metal layer includes a metal layer, and the second metal layer includes a polysilicon layer with metal silicide. The first metal layer and the second metal layer are only a classification designation of the reference layer, and do not represent the order and composition.

[0043] Specifically, as shown in FIG. 2, a first metal layer 201 is arranged on the front surface of the wafer to be detected, and a second metal layer 202 is arranged on the back surface of the wafer to be detected. Figure 6 In the front surface electrical failure positioning process of the wafer to be detected, the first metal layer with the same number of layers as the metal layer of the wafer to be detected is arranged on the front surface of the wafer to be detected. In some embodiments, the first metal layer can be adjusted according to actual needs to adapt to the metal layer of the wafer to be detected, that is, the first metal layer is appropriately reduced or increased. For example, as shown in FIG. 3, the first metal layer 301 is arranged on the front surface of the wafer to be detected, and the number of layers of the first metal layer 301 is less than that of the metal layer of the wafer to be detected. Figure 7 In the back surface electrical failure positioning process of the wafer to be detected, a second metal layer is arranged in the peripheral space of the back surface of the wafer to be detected, and the second metal layer is the same layer as the polysilicon layer of the structure of the wafer to be detected.

[0044] In some embodiments, the parameter information of the reference blocks in the first and second metal layers is determined based on the wafer to be inspected. The reference block is the smallest unit in which the first and second metal layers are distributed within a preset range of the wafer to be inspected. The parameter information of the reference block includes: the size of the reference block itself, the distance between adjacent reference blocks, the number of reference blocks, and the number of layers in which the reference blocks are disposed.

[0045] like Figure 8 The left and right sides respectively show reference blocks in the second and first metal layers. In this embodiment, the parameter information of the reference blocks in the first and second metal layers is determined according to the wafer under test. Specifically, the wafers under test come in different sizes, such as 6-inch, 8-inch, and 12-inch wafers, and the number of reference blocks set during the failure electrical location process will also differ. For example, larger wafers under test require relatively more reference blocks. Furthermore, the distribution and number of metal layers on the wafer vary depending on the circuit pattern, resulting in differences in the number of reference layers and the number of reference blocks. Additionally, the number of reference blocks may vary depending on the requirements for local failure detection of the wafer under test, thus affecting the proportion of the reference block area to the wafer area under test.

[0046] In some embodiments, the size of the reference block itself and the distance between adjacent reference blocks are as follows: Figure 8 Example. For example... Figure 8 As shown on the right, the reference block within the first metal layer can be divided into large metal cubes (3*3µm) and small metal cubes (2*2µm). The spacing between adjacent large metal cubes is 4µm, the spacing between adjacent small metal cubes is 5µm, and the spacing between adjacent large and small metal cubes is 1µm. This design of the reference block ensures that the corresponding pattern can be clearly identified by a microscopic microscope, while keeping the physical position deviation of the failure location hotspot within 2µm. This reference block is a metal block. Figure 8 As shown on the left, the reference blocks contained in the second metal layer are divided into large reference blocks of 3*3um and small reference strips of 2*3um based on their own size. The interval between two adjacent large reference blocks is 4um, the interval between two adjacent small reference blocks is 5um, and the interval between adjacent large reference blocks and small reference blocks is 2um. The large reference blocks are polycrystalline silicon blocks with metal silicides, and the small reference strips are polycrystalline silicon strips with metal silicides.

[0047] The present specification sets a reference layer similar to a metal material, the reference layer is a plurality of minimum unit regularly arranged reference blocks, a specific reference block size and a gap between reference blocks are set, when scanned by a micro light display mirror infrared laser system, the reference layer will reflect light so that the structure relatively below the reference layer covered will not be displayed, which helps to form a clearer high-contrast test structure pattern image, and then the hotspot information of the failure point is superimposed on the test structure pattern image to realize the effect of 2um failure positioning of the physical position deviation of the hotspot according to the reference layer, which not only improves the accuracy of failure point positioning, but also realizes the required analysis result quickly and accurately.

[0048] In some embodiments, each reference block is set on the front and / or back of the wafer to be detected according to the preset rule according to the parameter information of the reference block. Wherein the preset rule includes that the reference block is set on the front and back of the wafer to be detected, and is arranged according to a specific shape according to the number and size of the reference block, and the reference block is set near the space of the back of the wafer to be detected.

[0049] For example, Figure 6 Or Figure 7 The example reference block rule is set in the preset range of the wafer to be detected. When the front failure electrical property positioning analysis of the wafer to be detected is performed, for example, Figure 6 The reference block rule is set on the front of the wafer to be detected. When the back failure electrical property positioning analysis of the wafer to be detected is performed, for example, Figure 7 When the reference block rule is set near the space of the back of the wafer to be detected, the distance from the polysilicon Poly with metal silicide of the wafer to be detected can be limited according to the size of the wafer to be detected. For example, Figure 5 As shown, the regular arrangement of large metal blocks and small metal blocks in the first metal layer is set on the front of the wafer to be detected, and the regular arrangement of large reference blocks and small reference strips in the second metal layer is set near the space of the back of the wafer to be detected.

[0050] In some embodiments, the reference blocks in the first metal layer are arranged in a first shape; the reference blocks in the second metal layer are arranged in a second shape; wherein the first shape arrangement and the second shape arrangement are used to locate the position information of the failure in the wafer to be detected. Wherein the first shape includes a rice type, and the second shape includes a T type.

[0051] For example, Figure 8 As shown on the right, the reference blocks contained in the first metal layer can be divided into 3*3um large metal blocks and 2*2um small metal blocks, the interval between two adjacent large metal blocks is 4um, the interval between two adjacent small metal blocks is 5um, and the interval between the adjacent large metal block and the small metal block is 1um. The design of the above reference block can ensure that the reference block corresponding pattern can be clearly identified by the micro light microscope, and at the same time, the physical position deviation of the failure positioning hotspot is controlled within 2um. The reference block is a metal block.Figure 8 The left side shows that the reference blocks in the second metal layer include 3*3um large reference blocks and 2*3um small reference strips, the interval between two adjacent large reference blocks is 4um, the interval between two adjacent small reference blocks is 5um, and the interval between the adjacent large reference block and the small reference block is 2um, wherein the large reference block is a polysilicon block with metal silicide, and the small reference strip is a polysilicon strip with metal silicide.

[0052] Reference Figure 5 The large metal blocks and the small metal blocks in the first metal layer are regularly arranged in a "rice" shape, specifically, the interval between two adjacent large metal blocks is 4um, the interval between two adjacent small metal blocks is 5um, and the interval between the adjacent large metal block and the small metal block is 1um. The large reference blocks and the small reference strips in the second metal layer are regularly arranged in a "T" shape, specifically, the interval between two adjacent large reference blocks is 4um, the interval between two adjacent small reference blocks is 5um, and the interval between the adjacent large reference block and the small reference block is 2um.

[0053] The present specification sets a regularly arranged reference block, especially makes the reference layer formed by the reference block arranged in a rice shape or a T shape. When scanned by a micro-light display mirror infrared laser system, the reference layer will reflect light so that the structure below the reference layer will not be displayed, which helps to form a clearer and higher contrast test structure image, and then superimposes the hotspot information of the failure point on the test structure image to realize the effect of 2um failure positioning of the hotspot physical position deviation according to the reference layer. Not only improves the accuracy of failure point positioning, but also realizes the required analysis results quickly and accurately.

[0054] In some embodiments, the method further comprises: respectively acquiring a detection standard image of the front surface of the wafer and a detection standard image of the back surface of the wafer.

[0055] Specifically, during the comparison between the wafer scanning image and the detection standard image, the detection standard image also needs to be acquired. In some embodiments, the detection standard image of the front surface of the wafer is acquired in the failure electrical analysis of the front surface of the wafer to be detected; that is, the wafer sample to be detected with the reference layer is delaminated to the last "rice" shaped metal layer, and the wafer scanning image of the front surface of the wafer to be detected is superimposed on the relative physical position information of this "rice" shaped metal layer structure, which is more accurate for preparing cross-section samples or transmission electron microscope thin section samples of the defect position by a focused ion beam microscope, so as to not only realize rapid and accurate positioning, but also obtain the required analysis results according to the requirements.

[0056] In some embodiments, a standard image of the wafer back surface is obtained in the failure electrical analysis of the wafer back surface to be detected; that is, the wafer sample to be detected with a reference layer is delaminated to the inter layer dielectric (ILD) layer, and the wafer scanning image of the wafer back surface to be detected is superimposed on the relative physical position information of the "T" type band metal silicide polysilicon structure, so that the cross-section sample or the transmission electron microscope thin section sample of the defect position is prepared by the focused ion beam microscope, thereby not only achieving rapid and accurate positioning, but also obtaining the required analysis results according to the requirements.

[0057] The embodiments of the present application are not limited to the typical gate oxide layer integrity reliable test structure, but can also be applied to any test structure requiring auxiliary failure positioning, such as an electron migration test structure, a serpentine metal line structure, a finger capacitor test structure, etc.

[0058] In combination with the above semiconductor failure detection method, the present application provides a semiconductor failure detection structure, which comprises a reference layer added in a preset range of a wafer to be detected; the reference layer is used for reflecting part of the irradiation light of the wafer to be detected when the wafer to be detected is scanned by a micro-light microscope infrared laser, and is also used for determining the position information of the failure in the wafer to be detected.

[0059] As Figure 5 The present application sets a reference layer of similar metal material to reflect light when scanned by a micro-light display microscope infrared laser system, so that the structure below the reference layer covered by the reference layer is not displayed, which helps to form a clearer and higher-contrast test structure image, and thus the positioning position information of the failure point can be more accurately obtained by superimposing the hotspot information of the failure point on the test structure image according to the reference layer.

[0060] In some embodiments, the reference layer is arranged in a preset range of the front surface and the back surface of the wafer to be detected, and the reference layer comprises a plurality of reference blocks. The reference layer comprises a metal layer or a polysilicon layer with metal silicide. The reference block is the smallest unit arranged in the preset range of the wafer to be detected.

[0061] In some embodiments, the size of the reference block itself and the distance between adjacent reference blocks are as follows Figure 8 Examples. As Figure 8 As shown on the right, the reference block can be divided into a large metal square of 3*3um and a small metal square of 2*2um, the interval between two adjacent large metal squares is 4um, the interval between two adjacent small metal squares is 5um, and the interval between the large metal square and the small metal square is 1um. The design of the above reference block can ensure that the corresponding image of the reference block can be clearly recognized by the micro-light microscope, and at the same time, the physical position deviation of the failure positioning hotspot is controlled within 2um. The reference block is a metal block.Figure 8 As shown on the left, the reference blocks can be divided into large reference blocks of 3*3 um and small reference bars of 2*3 um. The interval between two adjacent large reference blocks is 4 um, the interval between two adjacent small reference blocks is 5 um, and the interval between an adjacent large reference block and a small reference block is 2 um. Among them, the large reference blocks are polysilicon blocks with metal silicide, and the small reference bars are polysilicon bars with metal silicide.

[0062] Specifically, when performing front-side failure detection on the wafer to be detected, the reference layer is set on the front side of the wafer to be detected. When performing back-side failure detection on the wafer to be detected, the reference layer is set within a specific range near the back side of the wafer to be detected. Or the reference layer is set on both the front and back sides of the wafer to be detected. Thus, when the wafer to be detected is scanned by an infrared laser, a more high-definition and contrasty graphic image can be obtained, and finally the position information of the failure location in the wafer to be detected can be determined.

[0063] In some embodiments, the arrangement of the reference blocks includes a "rice" shape arrangement and / or a "T" shape arrangement.

[0064] Combined with Figure 8 the reference blocks shown, such as Figure 6 shown, the large metal blocks and small metal blocks are regularly arranged alternately in a "rice" shape. Specifically, the interval between two adjacent large metal squares is 4 um, the interval between two adjacent small metal squares is 5 um, and the interval between an adjacent large metal block and a small metal block is 1 um, etc., and they are regularly arranged alternately. As Figure 7 shown, the large reference blocks and the small reference bars are regularly arranged alternately in a "T" shape. Specifically, the interval between two adjacent large reference blocks is 4 um, the interval between two adjacent small reference blocks is 5 um, and the interval between an adjacent large reference block and a small reference block is 2 um, etc., and they are regularly arranged alternately.

[0065] This specification sets a reference layer of a similar metal material. This reference layer is composed of multiple reference blocks regularly arranged in the smallest units. In particular, the reference layer formed by the reference blocks is arranged in a "rice" shape or a "T" shape. When scanned by a micro-light display mirror infrared laser system, the reference layer will reflect light so that the structure relatively below the reference layer will not be displayed, which helps to form a more clear and high-contrast test structure graphic image. Furthermore, the hot spot information of the failure point is superimposed on the test structure graphic image, and the physical position deviation of the failure location hot spot of 2 um can be achieved according to the reference layer. This not only improves the accuracy of failure point location but also realizes quickly and accurately obtaining the required analysis results.

[0066] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.

[0067] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any changes or replacements within the technical scope disclosed by the present application can be easily conceived by the person skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor failure detection method applied to a semiconductor device failure detection process, characterized by, The semiconductor failure detection method comprises: A reference layer is arranged on the front surface and / or back surface of the wafer to be detected, including arranging one or more first metal layers on the front surface of the wafer to be detected, or arranging a second metal layer on the back surface of the wafer to be detected; A wafer image of the wafer to be detected corresponding to the reference layer is acquired; The wafer image is compared with a detection standard image, and the position information of failure in the wafer to be detected and analysis results are obtained according to the reference layer. The semiconductor failure detection method is applied to a gate oxide layer integrity reliability test structure and an auxiliary failure positioning test structure, and the auxiliary failure positioning test structure includes an electron migration test structure, a snake-shaped metal line structure or a finger capacitor test structure.

2. The semiconductor failure detection method according to claim 1, characterized by, The parameter information of the reference blocks in the first metal layer and the second metal layer is determined according to the wafer to be detected.

3. The semiconductor failure detection method according to claim 2, characterized by, The method further comprises: According to the parameter information of the reference blocks, each reference block is arranged on the front surface and / or back surface of the wafer to be detected according to a preset rule.

4. The semiconductor failure detection method according to claim 2, characterized by, The reference blocks in the first metal layer are arranged in a first shape, and the reference blocks in the second metal layer are arranged in a second shape. The first shape arrangement and the second shape arrangement are used to position the position information of failure in the wafer to be detected.

5. The semiconductor failure detection method according to claim 4, wherein The first shape includes a rice type, and the second shape includes a T type.

6. The semiconductor failure detection method according to any one of claims 1 to 5, characterized by, The method further comprises: Detection standard images of the front surface and back surface of the wafer are acquired respectively.

7. A semiconductor failure detection structure, comprising: The semiconductor failure detection method is applied to failure detection, and the semiconductor failure detection structure comprises: A reference layer is additionally arranged in a preset range of the wafer to be detected; the reference layer is used to reflect part of the irradiation light of the wafer to be detected when the wafer to be detected is scanned by a micro-light microscope infrared laser, and is also used to determine the position information of failure in the wafer to be detected.

8. The semiconductor failure detection structure of claim 7, wherein, The reference layer is arranged in a preset range of the front surface and back surface of the wafer to be detected, and the reference layer comprises a plurality of reference blocks.

9. The semiconductor failure detection structure of claim 8, wherein, The arrangement of the reference blocks includes a rice type shape arrangement and / or a T type shape arrangement.

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