Semiconductor structure and method of forming the same, circuit and method of operating the circuit

Abstract

A semiconductor structure and a method for forming the same are disclosed. The structure includes: a substrate comprising a first well region and a second well region; a first gate structure and a first channel region located on the first well region, wherein the first channel region is located within the first well region at the bottom of the first gate structure, and the conductivity type of the first channel region is the same as that of the first well region; a second gate structure, a second channel region, and a second source region and a second drain region located on the second well region on both sides of the second gate structure, wherein the second channel region is located within the second well region at the bottom of the second gate structure and is located between the second source region and the second drain region, wherein the conductivity type of the second channel region is opposite to that of the second well region, and the conductivity type of the second source region and the second drain region is the same as that of the second channel region; the second drain region and the first gate structure are electrically interconnected, and the second source region and the first well region are electrically interconnected. The semiconductor structure formed by the method exhibits improved performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure, a method for forming the same, a circuit, and a method for operating the circuit. Background Technology

[0002] The main device in integrated circuits, especially very large-scale integrated circuits, is the metal-oxide-semiconductor field-effect transistor (MOS transistor). Since the invention of the MOS transistor, its geometric dimensions have been continuously shrinking according to Moore's Law. Currently, its feature size has entered the 45-nanometer range. At this scale, various secondary effects caused by the physical limitations of the device become increasingly unavoidable, making it increasingly difficult to scale down the feature size of the device. Among these challenges in the manufacturing of MOS transistor devices and circuits, the most significant issue is the leakage current problem from the gate to the substrate caused by the reduction in the thickness of polysilicon or the gate dielectric layer during the scaling down of traditional CMOS processes.

[0003] Therefore, the leakage current from the gate to the substrate is a problem that needs to be addressed continuously. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure, its formation method, circuit, and circuit operation method to improve the performance of the semiconductor structure.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a first well region and a second well region; a first gate structure and a first channel region located on the first well region, the first channel region being located within the first well region at the bottom of the first gate structure, the conductivity type of the first channel region being the same as that of the first well region; a second gate structure, a second channel region, and a second source region and a second drain region located on the second well region on both sides of the second gate structure, the second channel region being located within the second well region at the bottom of the second gate structure, and the second channel region being located between the second source region and the second drain region, the conductivity type of the second channel region being opposite to that of the second well region, the second source region and the second drain region being the same as that of the second channel region, the second drain region and the first gate structure being electrically interconnected; and a first connection region located on the surface of the first well region, the second source region and the first well region being electrically interconnected through the first connection region.

[0006] Optionally, the conductivity type of the first well region is the same as that of the second well region; the conductivity types of the second source region and the second drain region are the same as those of the first source region and the first drain region.

[0007] Optionally, the conductivity type of the first well region is opposite to that of the second well region; the conductivity types of the second source region and the second drain region are opposite to those of the first source region and the first drain region.

[0008] Optionally, the second gate structure contains doped ions, the conductivity type of which is opposite to that of the second channel region.

[0009] Optionally, the substrate includes: a base and a fin structure located on the base, the fin structure including a first fin located in a first well region and a second fin located in a second well region; a first gate structure spanning the first fin and a second gate structure spanning the second fin.

[0010] Optionally, the first fin contains anti-penetration ions, the conductivity type of which is the same as that of the first well region.

[0011] Optionally, the conductivity type of the first connection region is the same as that of the first well region, and the ion concentration in the first connection region is greater than that in the first well region.

[0012] Optionally, it further includes: a first conductive structure and a second conductive structure located on the substrate, wherein the first conductive structure electrically interconnects the second drain region and the first gate structure, and the second conductive structure electrically interconnects the second source region and the first connection region.

[0013] Optionally, the second conductive structure is also electrically connected to the first source region.

[0014] Optionally, it further includes: a second connection region located on the surface of the second well region; the second gate structure and the second well region are electrically connected through the second connection region.

[0015] Optionally, the conductivity type of the second connection region is the same as that of the second well region, and the ion concentration in the second connection region is greater than that in the second well region.

[0016] Optionally, it may also include: a third conductive structure located on the substrate, the third conductive structure being electrically connected to the second gate structure and the second connection region.

[0017] Optionally, it further includes: a dielectric structure located on the substrate, wherein the first gate structure and the second gate structure are located within the dielectric structure, and the first conductive structure, the second conductive structure and the third conductive structure are located within the dielectric structure.

[0018] Optionally, the first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, the high dielectric constant material includes alumina or hafnium oxide, and the material of the gate layer includes a metal, the metal including tungsten.

[0019] Optionally, the first gate structure further includes a work function layer located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, wherein the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0020] Optionally, the material of the second gate structure includes silicon.

[0021] Optionally, the conductivity type of the first well region includes N-type or P-type, and the conductivity type of the second well region includes N-type or P-type; the N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0022] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first well region and a second well region; forming a first gate structure and a first channel region on the first well region, the first channel region being located within the first well region at the bottom of the first gate structure, the first channel region having the same conductivity type as the first well region; forming a second gate structure, a second channel region, and a second source region and a second drain region located within the second well regions on both sides of the second gate structure in the second well region, the second channel region being located within the second well region at the bottom of the second gate structure, and the second channel region being located between the second source region and the second drain region, the conductivity type of the second channel region being opposite to the conductivity type of the second well region, the second source region and the second drain region having the same conductivity type as the second channel region, the second drain region being electrically interconnected with the first gate structure; forming a first connection region on the surface of the first well region, the second source region and the first well region being electrically interconnected through the first connection region.

[0023] Optionally, the process of forming the first gate structure on the first well region further includes: forming a first source region and a first drain region located in the first well regions on both sides of the first gate structure, wherein the conductivity type of the first source region and the first drain region is opposite to the conductivity type of the first channel region.

[0024] Optionally, the conductivity type of the first well region is the same as that of the second well region; the conductivity types of the second source region and the second drain region are the same as those of the first source region and the first drain region.

[0025] Optionally, the second source region and the second drain region are formed simultaneously with the first source region and the first drain region.

[0026] Optionally, the conductivity type of the first well region is opposite to that of the second well region; the conductivity types of the second source region and the second drain region are opposite to those of the first source region and the first drain region.

[0027] Optionally, the second gate structure contains doped ions, the conductivity type of which is opposite to that of the second channel region.

[0028] Optionally, the process of doping ions into the second gate structure is combined with the process of forming the first source region and the first drain region into one process.

[0029] Optionally, the substrate includes: a base and a fin structure located on the base, the fin structure including a first fin located on a first region and a second fin located on a second region; a first gate structure spanning the first fin, and a second gate structure spanning the second fin; a first well region located within the first fin, and a second well region located within the second fin.

[0030] Optionally, before forming the first gate structure, the method further includes: implanting anti-penetration ions into the first fin, wherein the conductivity type of the anti-penetration ions is the same as that of the first well region.

[0031] Optionally, the process for forming the first connection region includes an ion implantation process; the conductivity type of the first connection region is the same as that of the first well region, and the ion concentration in the first connection region is greater than that in the first well region.

[0032] Optionally, it further includes: forming a first conductive structure and a second conductive structure on the substrate, wherein the first conductive structure electrically interconnects the second drain region and the first gate structure, and the second conductive structure electrically interconnects the second source region and the first well region.

[0033] Optionally, the second conductive structure is also electrically connected to the first source region.

[0034] Optionally, the method for forming the first conductive structure and the second conductive structure includes: forming a dielectric structure on a substrate, wherein the first gate structure and the second gate structure are located within the dielectric structure; and forming the first conductive structure and the second conductive structure within the dielectric structure.

[0035] Optionally, it further includes: forming a second connection region on the surface of the second well region; the second gate structure and the second well region are electrically connected through the second connection region.

[0036] Optionally, the process for forming the second connection region includes an ion implantation process; the conductivity type of the second connection region is the same as that of the second well region, and the ion concentration in the second connection region is greater than that in the second well region.

[0037] Optionally, it further includes: forming a third conductive structure on the substrate, the third conductive structure being electrically connected to the second gate structure and the second connection region.

[0038] Optionally, the first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, the high dielectric constant material includes alumina or hafnium oxide, and the material of the gate layer includes a metal, the metal including tungsten.

[0039] Optionally, the first gate structure further includes a work function layer located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, wherein the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0040] Optionally, the material of the second gate structure includes silicon.

[0041] Optionally, the conductivity type of the first well region includes N-type or P-type, and the conductivity type of the second well region includes N-type or P-type; the N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0042] Accordingly, the present invention also provides a protection circuit, comprising: a first transistor having a first gate, a second source, and a second drain, wherein the first source and the first drain are respectively coupled to a power supply voltage node and a ground voltage node; and a second transistor having a second gate, a first source, and a first drain, wherein the first drain is coupled to the first gate, and the first source is coupled to the power supply voltage node.

[0043] Optionally, the first transistor is an N-type transistor; the second source is coupled to a ground voltage node, and the second drain is coupled to a power supply voltage node.

[0044] Optionally, the first transistor is a P-type transistor; the second source is coupled to the power supply voltage node, and the second drain is coupled to the ground voltage node.

[0045] Optionally, the second transistor is a junction transistor.

[0046] Optionally, the second transistor is an N-type transistor or a P-type transistor.

[0047] Accordingly, the present invention also provides a method for operating a protection circuit, comprising: providing a protection circuit, the protection circuit comprising: a first transistor having a first gate, a second source, and a second drain, the second source and the second drain being coupled to a power supply voltage node and a ground voltage node, respectively; a second transistor having a second gate, a first source, and a first drain, the first drain being coupled to the first gate, and the first source being coupled to the power supply voltage node; applying a first voltage to the first gate; and applying a second voltage to the second gate.

[0048] Optionally, the protection circuit further includes: the first transistor is an N-type transistor; the second source is coupled to a ground voltage node, and the second drain is coupled to a power supply voltage node.

[0049] Optionally, the protection circuit further includes: the first transistor is a P-type transistor; the second source is coupled to the power supply voltage node, and the second drain is coupled to the ground voltage node.

[0050] Optionally, the second transistor is a junction transistor.

[0051] Optionally, the second transistor is an N-type transistor or a P-type transistor.

[0052] Optionally, when the second transistor is an N-type transistor, the range of the second voltage is less than 0; when the second transistor is a P-type transistor, the range of the second voltage is greater than the power supply voltage.

[0053] Optionally, the first voltage ranges from 0 to the power supply voltage.

[0054] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0055] The method of the present invention involves forming a first gate structure and a first channel region on a first well region, wherein the first channel region is located within the first well region at the bottom of the first gate structure, and the conductivity type of the first channel region is the same as that of the first well region. A second gate structure, a second channel region, and a second source region and a second drain region are formed in a second well region located on both sides of the second gate structure within the second well regions. The second channel region is located within the second well region at the bottom of the second gate structure and is situated between the second source region and the second drain region. The conductivity type of the second channel region is opposite to that of the second well region. The conductivity type of the second source region and the second drain region is the same as that of the second channel region. The second drain region is electrically interconnected with the first gate structure, and the second source region is electrically interconnected with the first well region. The second drain region and the first gate structure are electrically interconnected, and the second source region and the first well region are electrically interconnected. The conductivity type of the second channel region is opposite to that of the second well region, while the conductivity type of the second source region and the second drain region is the same as that of the second channel region. Therefore, the second source region and the second drain region are connected through the second channel region. On the one hand, the charge accumulated in the first gate structure during manufacturing can be conducted to the first well region through the second drain region, the second channel region, and the second source region, thereby reducing the accumulation of charge in the first gate structure. On the other hand, in the operating state, the second gate structure can be in the off state, avoiding leakage between the second gate structure and the substrate that could affect the operating state of the first gate structure.

[0056] Furthermore, the second gate structure contains doped ions, and the conductivity type of these doped ions is opposite to that of the second channel region. Therefore, when a voltage is applied to the second gate structure, the second gate structure and the second well region cannot conduct to form an effective device, thus not affecting the operating state of the first gate structure.

[0057] Furthermore, the third conductive structure is electrically connected to the second gate structure and the second well region, so that when a voltage is subsequently applied to the second gate structure, the second gate structure has better control over the second channel region, thereby better shutting off the path between the second gate structure and the substrate. This avoids leakage between the second gate structure and the substrate affecting the working state of the first gate structure when the first gate structure is working. Attached Figure Description

[0058] Figures 1 to 3 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of the protection circuit in an embodiment of the present invention;

[0060] Figure 5 This is a flowchart of the operation method of the protection circuit in an embodiment of the present invention. Detailed Implementation

[0061] As described in the background section, the leakage current from the gate to the substrate is a problem that needs to be addressed continuously.

[0062] Specifically, plasma processing is an essential process in semiconductor manufacturing. However, plasma processing causes a large amount of charge to accumulate in the gate dielectric layer. The charge accumulated in the gate dielectric layer increases the voltage between the gate and the substrate, generating a high tunneling current. This alters the breakdown voltage of the semiconductor device, making it more susceptible to leakage.

[0063] To mitigate the aforementioned problems, in one embodiment, a diode is added between the gate and the substrate to conduct away the charge accumulated on the gate dielectric layer. However, a large breakdown voltage is required to break down the diode in order to conduct the charge. This breakdown voltage exceeds the operating voltage of the semiconductor device, and the large breakdown voltage also leads to a large tunneling current between the gate and the substrate, thus affecting the semiconductor device voltage. Consequently, the protective effect of the diode is relatively weak.

[0064] In another embodiment, a MOSFET is added between the gate and the substrate to conduct away the charge accumulated on the gate dielectric layer. However, a large breakdown voltage is required to break down the MOSFET in order to conduct away the charge. The breakdown voltage of the MOSFET is greater than the operating voltage of the semiconductor device. This large breakdown voltage also leads to a large tunneling current between the gate and the substrate, thereby affecting the voltage of the semiconductor device. Therefore, the protective effect of the MOSFET is still relatively weak.

[0065] To address the aforementioned problems, the present invention provides a semiconductor structure, its formation method, circuit, and circuit operation method. A first gate structure and a first channel region are formed on a first well region. The first channel region is located within the first well region at the bottom of the first gate structure, and the conductivity type of the first channel region is the same as that of the first well region. A second gate structure, a second channel region, and a second source region and a second drain region are formed in a second well region on both sides of the second gate structure. The second channel region is located within the second well region at the bottom of the second gate structure and is situated between the second source region and the second drain region. The conductivity type of the second channel region is opposite to that of the second well region. The conductivity types of the second source region and the second drain region are the same as those of the second channel region. The second drain region is electrically interconnected with the first gate structure, and the second source region is electrically interconnected with the first well region. On the one hand, the conductivity type of the second channel region is opposite to that of the second well region, while the conductivity type of the second source region and the second drain region is the same as that of the second channel region. Therefore, the second source region and the second drain region are connected through the second channel region, allowing the charge within the first gate structure to be conducted to the first well region through the second drain region, the second channel region, and the second source region, thereby reducing charge accumulation within the first gate structure. Thus, the second gate structure can conduct away the charge within the first gate structure while having minimal impact on the first gate structure, providing good leakage protection.

[0066] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0067] Figures 1 to 3 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0068] Please refer to Figure 1 A substrate is provided, the substrate including a first well region 101 and a second well region 102.

[0069] The substrate includes a base (not shown) and a fin structure (not shown) located on the base, the fin structure including a first fin (not shown) located in a first well region 101 and a second fin (not shown) located in a second well region 102.

[0070] The first well region 101 has a conductivity type including N-type or P-type, and the second well region 102 has a conductivity type including N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0071] In this embodiment, the substrate is made of silicon, and the fin structure is also made of silicon.

[0072] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The fin structure material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0073] The conductivity type of the first well region 101 may be the same as or different from that of the second well region 102.

[0074] Please continue to refer to this. Figure 1 It also includes: injecting anti-penetration ions into the first fin, wherein the conductivity type of the anti-penetration ions is the same as the conductivity type of the first well region 101.

[0075] The conductivity type of the anti-penetration ion is the same as that of the first well region 101, that is, the conductivity type of the anti-penetration ion is the same as that of the first well region 101. Figure 2 The first source region 106 and the first drain region 105 shown have opposite conductivity types, thereby preventing punch-through between the first source region 106 and the first drain region 105.

[0076] The anti-penetration ions include N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions; the P-type ions include boron ions, boron-fluorine ions, or indium ions.

[0077] Please refer to Figure 2 A first gate structure 103 and a first channel region 104 are formed on the first well region 101. The first channel region 104 is located in the first well region 101 at the bottom of the first gate structure 103. The conductivity type of the first channel region 104 is the same as that of the first well region 101.

[0078] During the process of forming the first gate structure 103 on the first well region 101, the process also includes forming a first source region 106 and a first drain region 105 located in the first well regions 101 on both sides of the first gate structure 103, wherein the conductivity type of the first source region 106 and the first drain region 105 is opposite to the conductivity type of the first channel region 104.

[0079] In this embodiment, the first gate structure 103 spans the first fin. The first source region 106 and the first drain region 105 are located within the first fin on both sides of the first gate structure 103.

[0080] The first gate structure 103 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer. The material of the gate dielectric layer includes a high dielectric constant material with a dielectric constant greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide. The material of the gate layer includes a metal, and the metal includes tungsten.

[0081] In this embodiment, the first gate structure 103 further includes a work function layer (not shown), which is located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0082] Please continue to refer to this. Figure 2 A second gate structure 107, a second channel region 108, and a second source region 110 and a second drain region 109 are formed in the second well region 102 on both sides of the second gate structure 107. The second channel region 108 is located in the second well region 102 at the bottom of the second gate structure 107, and the second channel region 108 is located between the second source region 110 and the second drain region 109. The conductivity type of the second channel region 108 is opposite to that of the second well region 102, and the conductivity type of the second source region 110 and the second drain region 109 is the same as that of the second channel region 108.

[0083] In this embodiment, the second gate structure 107 spans the second fin. The second source region 110 and the second drain region 109 are located within the second fins on both sides of the second gate structure 107.

[0084] The material of the second gate structure 107 includes silicon.

[0085] In this embodiment, the second gate structure 107 contains doped ions, and the conductivity type of the doped ions is opposite to that of the second channel region 108. Therefore, when a voltage is applied to the second gate structure 107, the second gate structure 107 and the second well region 102 cannot conduct to form an effective device, thus not affecting the operating state of the first gate structure 103. Thus, the second gate structure 107 can conduct away the charge within the first gate structure 103 while having minimal impact on the first gate structure 103, providing good leakage protection.

[0086] In one embodiment, the conductivity type of the first well region 101 is the same as that of the second well region 102, that is, the conductivity type of the second source region 110 and the second drain region 109 is the same as that of the first source region 106 and the first drain region 105. Therefore, the second source region 110 and the second drain region 109 can be formed simultaneously with the first source region 106 and the first drain region 105. The process for forming the second source region 110 and the second drain region 109, as well as the first source region 106 and the first drain region 105, includes an ion implantation process. This saves on process steps.

[0087] In another embodiment, the conductivity type of the first well region 101 is opposite to that of the second well region 102, that is, the conductivity type of the second source region 110 and the second drain region 109 is opposite to that of the first source region 106 and the first drain region 105.

[0088] The conductivity type of the doped ions in the second gate structure 107 is opposite to that of the second channel region 108; that is, the conductivity type of the doped ions in the second gate structure 107 is the same as that of the first source region 106 and the first drain region 105. Therefore, the process of doping the second gate structure 107 with doped ions is a single process, which saves on process steps.

[0089] Please refer to Figure 3 The second drain region 109 and the first gate structure 103 are electrically interconnected, and the second source region 110 and the first well region 101 are electrically interconnected.

[0090] In this embodiment, a first conductive structure 111 and a second conductive structure 112 are formed on the substrate. The first conductive structure 111 electrically interconnects the second drain region 109 and the first gate structure 103, and the second conductive structure 112 electrically interconnects the second source region 110 and the first well region 101.

[0091] In this embodiment, the method further includes: forming a first connection region 120 on the surface of the first well region 101; the second conductive structure 112 electrically interconnects the second source region 110 and the first connection region 120; and the second source region 110 is electrically interconnected with the first well region 101 through the first connection region 120.

[0092] The process for forming the first connection region 120 includes an ion implantation process. The conductivity type of the first connection region 120 is the same as that of the first well region 101, and the ion concentration in the first connection region 120 is greater than that in the first well region 101. Therefore, when the second conductive structure 112 is connected to the first well region 101 through the first connection region 120, the contact resistance between the second conductive structure 112 and the first well region 101 is small. This allows the charge accumulated in the first gate structure 103 during manufacturing to be conducted to the first well region 101 through the second drain region 109, the second channel region 108, and the second source region 110, thereby reducing charge accumulation in the first gate structure 103.

[0093] In this embodiment, the second conductive structure 112 is also electrically connected to the first source region 106. The first source region 106 and the first well region 101 can be loaded with the same voltage.

[0094] In other embodiments, the second conductive structure is not electrically connected to the first source region.

[0095] In this embodiment, the method further includes forming a third conductive structure 113 on a substrate, wherein the third conductive structure 113 is electrically connected to the second gate structure 107 and the second well region 102.

[0096] In this embodiment, a second connection region 121 is formed on the surface of the second well region 102, and the second gate structure 107 is electrically connected to the second well region 102 through the second connection region 121.

[0097] The process for forming the second connection region 121 includes an ion implantation process. The conductivity type of the second connection region 121 is the same as that of the second well region 102, and the ion concentration in the second connection region 121 is greater than that in the second well region 102. Therefore, when the third conductive structure 113 is connected to the second well region 102 through the second connection region 121, the contact resistance between the third conductive structure 113 and the second well region 102 is relatively small, allowing it to enter the working state more effectively.

[0098] The method for forming the first conductive structure 111, the second conductive structure 112, and the third conductive structure 113 includes: forming a dielectric structure (not shown) on a substrate, wherein the first gate structure 103 and the second gate structure 107 are located within the dielectric structure; and forming the first conductive structure 111, the second conductive structure 112, and the third conductive structure 113 within the dielectric structure.

[0099] The first conductive structure 111 comprises a metal or a metal nitride, the second conductive structure 112 comprises a metal or a metal nitride, and the third conductive structure 113 comprises a metal or a metal nitride; the metal comprises one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride comprises one or more of tantalum nitride and titanium nitride.

[0100] Thus, in the formed semiconductor structure, the conductivity type of the second channel region 108 is opposite to that of the second well region 102, and the conductivity type of the second source region 110 and the second drain region 109 is the same as that of the second channel region 108. Therefore, the second source region 110 and the second drain region 109 are connected through the second channel region 108. The first conductive structure 111 is electrically connected to the first gate structure 103 and the second drain region 109, and the second conductive structure 112 is electrically interconnected with the second source region 110 and the first well region 101. On the one hand, the charge accumulated in the first gate structure 103 during the manufacturing process can be conducted to the first well region 101 through the second drain region 109, the second channel region 108, and the second source region 110, thereby reducing the accumulation of charge in the first gate structure 103. On the other hand, in the working state, the second gate structure can be in the off state, avoiding the situation where leakage current between the second gate structure 107 and the substrate affects the working state of the first gate structure 103.

[0101] Furthermore, the third conductive structure 113 is electrically connected to the second gate structure 107 and the second well region 102, so that when a voltage is subsequently applied to the second gate structure 107, the second gate structure 107 has better control over the second channel region 108, thereby better shutting off the path between the second gate structure 107 and the substrate. This avoids leakage between the second gate structure 107 and the substrate affecting the working state of the first gate structure 103 when the first gate structure 103 is working.

[0102] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 3 ,include:

[0103] The substrate includes a first well region 101 and a second well region 102;

[0104] A first gate structure 103 and a first channel region 104 are located on the first well region 101. The first channel region 104 is located in the first well region 101 at the bottom of the first gate structure 103. The conductivity type of the first channel region 104 is the same as that of the first well region 101.

[0105] The second gate structure 107, the second channel region 108, and the second source region 110 and the second drain region 109 located in the second well regions 102 on both sides of the second gate structure 107 are located in the second well region 102 at the bottom of the second gate structure 107. The second channel region 108 is located between the second source region 110 and the second drain region 109. The conductivity type of the second channel region 108 is opposite to that of the second well region 102. The conductivity type of the second source region 110 and the second drain region 109 is the same as that of the second channel region 108. The second drain region 109 is electrically interconnected with the first gate structure 103.

[0106] The first connection region 120 is located on the surface of the first well region 101, and the second source region 110 and the first well region 101 are electrically interconnected through the first connection region 120.

[0107] In this embodiment, it further includes a first source region 106 and a first drain region 105 located in the first well regions 101 on both sides of the first gate structure 103, wherein the conductivity type of the first source region 106 and the first drain region 105 is opposite to the conductivity type of the first channel region 104.

[0108] In this embodiment, the conductivity type of the first well region 101 is the same as that of the second well region 102; the conductivity type of the second source region 110 and the second drain region 109 is the same as that of the first source region 106 and the first drain region 105.

[0109] In this embodiment, the conductivity type of the first well region 101 is opposite to that of the second well region 102; the conductivity types of the second source region 110 and the second drain region 109 are opposite to those of the first source region 106 and the first drain region 105.

[0110] In this embodiment, the second gate structure 107 contains doped ions, and the conductivity type of the doped ions is opposite to that of the second channel region 108.

[0111] In this embodiment, the substrate includes a base and a fin structure located on the base, the fin structure including a first fin located in a first well region and a second fin located in a second well region; the first gate structure spans the first fin, and the second gate structure spans the second fin.

[0112] In this embodiment, the first fin contains anti-penetration ions, and the conductivity type of the anti-penetration ions is the same as that of the first well region 101.

[0113] In this embodiment, the conductivity type of the first connection region 120 is the same as that of the first well region 101, and the ion concentration in the first connection region 120 is greater than that in the first well region 101.

[0114] In this embodiment, it further includes: a first conductive structure 111 and a second conductive structure 112 located on the substrate, wherein the first conductive structure 111 electrically interconnects the second drain region 109 and the first gate structure 103, and the second conductive structure 112 electrically interconnects the second source region 110 and the first well region 101.

[0115] In this embodiment, the second conductive structure 112 is also electrically connected to the first source region 106.

[0116] In this embodiment, it further includes: a second connection region 121 located on the surface of the second well region 102; the second gate structure 107 and the second well region 102 are electrically connected through the second connection region 121.

[0117] In this embodiment, the conductivity type of the second connection region 121 is the same as that of the second well region 102, and the ion concentration in the second connection region 121 is greater than that in the second well region 102.

[0118] In this embodiment, a third conductive structure 113 located on the substrate is further included, wherein the third conductive structure 113 is electrically connected to the second gate structure 107 and the second well region 102.

[0119] In this embodiment, it further includes: a dielectric structure located on the substrate, wherein the first gate structure 103 and the second gate structure 107 are located within the dielectric structure, and the first conductive structure 111, the second conductive structure 112 and the third conductive structure 113 are located within the dielectric structure.

[0120] In this embodiment, the first gate structure 103 includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, the high dielectric constant material includes aluminum oxide or hafnium oxide, and the material of the gate layer includes a metal, the metal including tungsten.

[0121] In this embodiment, the first gate structure 103 further includes a work function layer, which is located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, wherein the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

[0122] In this embodiment, the material of the second gate structure 107 includes silicon.

[0123] In this embodiment, the first well region 101 has a conductivity type including N-type or P-type, and the second well region 102 has a conductivity type including N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0124] Figure 4 This is a schematic diagram of the protection circuit in an embodiment of the present invention.

[0125] Please refer to Figure 4 The protection circuit includes:

[0126] A first transistor T has a first gate, a second source, and a second drain, the second source and the second drain being coupled to a power supply voltage node VDD and a ground voltage node G, respectively.

[0127] The second transistor JT has a second gate, a first source and a first drain, the first drain being coupled to the first gate and the first source being coupled to the power supply voltage node VDD.

[0128] In this embodiment, the first transistor T is an N-type transistor; the second source is coupled to the ground voltage node G, and the second drain is coupled to the power supply voltage node VDD.

[0129] In another embodiment, the first transistor T is a P-type transistor; the second source is coupled to the power supply voltage node VDD, and the second drain is coupled to the ground voltage node G.

[0130] In this embodiment, the second transistor JT is a junction transistor. The junction transistor is either an N-type transistor or a P-type transistor.

[0131] The second transistor JT is a junction transistor. The first drain is coupled to the first gate. On the one hand, the charge accumulated in the first gate can be conducted away through the second drain, thereby reducing the accumulation of charge in the first gate. On the other hand, the second transistor JT is a junction transistor, so when a voltage is applied to the second gate, the second transistor JT can be in the off state, thus having less impact on the first gate and playing a good role in preventing leakage current.

[0132] Figure 5 This is a flowchart of the operation method of the protection circuit in an embodiment of the present invention.

[0133] Please refer to Figure 5 The steps of the protection circuit operation method include:

[0134] S100: Provides a protection circuit, the protection circuit including: a first transistor T, the first transistor T having a first gate, a second source and a second drain, the second source and the second drain being coupled to a power supply voltage node VDD and a ground voltage node G respectively; a second transistor JT, the second transistor JT having a second gate, a first source and a first drain, the first drain being coupled to the first gate, and the first source being coupled to the power supply voltage node VDD;

[0135] S101: Apply a first voltage V1 to the first gate;

[0136] S102: Apply a second voltage V2 to the second gate.

[0137] Execution step S100: Provide a protection circuit, the protection circuit as follows Figure 4 As stated above.

[0138] In this embodiment, the protection circuit further includes: the first transistor T is an N-type transistor; the second source is coupled to the ground voltage node G, and the second drain is coupled to the power supply voltage node VDD.

[0139] In this embodiment, the first transistor T is a P-type transistor; the second source is coupled to the power supply voltage node VDD, and the second drain is coupled to the ground voltage node G.

[0140] In this embodiment, the second transistor JT is a junction transistor. The junction transistor is either an N-type transistor or a P-type transistor.

[0141] Step S101: Apply a first voltage V1 to the first gate.

[0142] In this embodiment, when the second transistor is an N-type transistor, the range of the second voltage V2 is less than 0; when the second transistor is a P-type transistor, the range of the second voltage V2 is greater than the power supply voltage VDD.

[0143] Step S102: Apply a second voltage V2 to the second gate.

[0144] In this embodiment, the range of the first voltage V1 is between 0 and the power supply voltage VDD.

[0145] The second transistor JT is a junction transistor. The first drain is coupled to the first gate. On the one hand, the charge accumulated in the first gate can be conducted away through the second drain, thereby reducing the accumulation of charge in the first gate. On the other hand, the second transistor JT is a junction transistor, so when a voltage is applied to the second gate, the second transistor JT can be in the off state, thus having less impact on the first gate and playing a good role in preventing leakage current.

[0146] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first well region and a second well region; The first gate structure and the first channel region are located on the first well region, and the first source region and the first drain region are located in the first well regions on both sides of the first gate structure. The first channel region is located in the first well region at the bottom of the first gate structure. The conductivity type of the first channel region is the same as that of the first well region. The conductivity types of the first source region and the first drain region are opposite to those of the first well region. The first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer. The second gate structure, the second channel region, and the second source region and the second drain region located in the second well regions on both sides of the second gate structure are provided. The second channel region is located in the second well region at the bottom of the second gate structure and is located between the second source region and the second drain region. The conductivity type of the second channel region is opposite to that of the second well region. The conductivity type of the second source region and the second drain region is the same as that of the second channel region. The second drain region and the first gate structure are electrically interconnected. The second gate structure is in contact with the second channel region. The second gate structure contains doped ions, and the conductivity type of the doped ions is opposite to that of the second channel region. A first connection region is located on the surface of the first well region, and the second source region and the first well region are electrically interconnected through the first connection region.

2. The semiconductor structure as described in claim 1, characterized in that, The first well region has the same conductivity type as the second well region; the second source region and the second drain region have the same conductivity type as the first source region and the first drain region.

3. The semiconductor structure as described in claim 1, characterized in that, The conductivity type of the first well region is opposite to that of the second well region; the conductivity types of the second source region and the second drain region are opposite to those of the first source region and the first drain region.

4. The semiconductor structure as described in claim 1, characterized in that, The substrate includes: a base and a fin structure located on the base, the fin structure including a first fin located in a first well region and a second fin located in a second well region; a first gate structure spanning the first fin and a second gate structure spanning the second fin.

5. The semiconductor structure as described in claim 4, characterized in that, The first fin contains anti-penetration ions, and the conductivity type of the anti-penetration ions is the same as that of the first well region.

6. The semiconductor structure as described in claim 1, characterized in that, The first connection region has the same conductivity type as the first well region, and the ion concentration in the first connection region is greater than the ion concentration in the first well region.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first conductive structure and a second conductive structure are located on a substrate. The first conductive structure electrically interconnects the second drain region and the first gate structure, and the second conductive structure electrically interconnects the second source region and the first connection region.

8. The semiconductor structure as described in claim 7, characterized in that, The second conductive structure is also electrically connected to the first source region.

9. The semiconductor structure as described in claim 7, characterized in that, Also includes: A second connection region is located on the surface of the second well region; the second gate structure and the second well region are electrically connected through the second connection region.

10. The semiconductor structure as described in claim 9, characterized in that, The conductivity type of the second connection region is the same as that of the second well region, and the ion concentration in the second connection region is greater than that in the second well region.

11. The semiconductor structure as described in claim 9, characterized in that, Also includes: A third conductive structure located on the substrate, the third conductive structure being electrically connected to the second gate structure and the second connection region.

12. The semiconductor structure as claimed in claim 11, characterized in that, Also includes: A dielectric structure located on a substrate, wherein the first gate structure and the second gate structure are located within the dielectric structure, and the first conductive structure, the second conductive structure and the third conductive structure are located within the dielectric structure.

13. The semiconductor structure as claimed in claim 1, characterized in that, The gate dielectric layer is made of a high dielectric constant material, the high dielectric constant material having a dielectric constant greater than 3.9, the high dielectric constant material including alumina or hafnium oxide, and the gate layer is made of a metal, the metal including tungsten.

14. The semiconductor structure as described in claim 13, characterized in that, The first gate structure further includes a work function layer, which is located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, wherein the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

15. The semiconductor structure as claimed in claim 1, characterized in that, The material of the second gate structure includes silicon.

16. The semiconductor structure as claimed in claim 1, characterized in that, The first well region has a conductivity type of N-type or P-type, and the second well region has a conductivity type of N-type or P-type; ions with an N-type conductivity type include phosphorus ions, arsenic ions, or antimony ions; ions with a P-type conductivity type include boron ions, boron-fluorine ions, or indium ions.

17. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first well region and a second well region; A first gate structure and a first channel region are formed on a first well region. The first channel region is located in the first well region at the bottom of the first gate structure. The conductivity type of the first channel region is the same as that of the first well region. The first gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer. A second gate structure, a second channel region, and a second source region and a second drain region are formed in the second well region on both sides of the second gate structure. The second channel region is located in the second well region at the bottom of the second gate structure and is located between the second source region and the second drain region. The conductivity type of the second channel region is opposite to that of the second well region. The conductivity type of the second source region and the second drain region is the same as that of the second channel region. The second drain region and the first gate structure are electrically interconnected. The second gate structure is in contact with the second channel region. The second gate structure contains doped ions, and the conductivity type of the doped ions is opposite to that of the second channel region. A first connection region is formed on the surface of the first well region, and the second source region and the first well region are electrically interconnected through the first connection region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process of forming the first gate structure on the first well region also includes: forming a first source region and a first drain region located in the first well regions on both sides of the first gate structure, wherein the conductivity type of the first source region and the first drain region is opposite to the conductivity type of the first channel region.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The first well region has the same conductivity type as the second well region; the second source region and the second drain region have the same conductivity type as the first source region and the first drain region.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The second source region and the second drain region are formed simultaneously with the first source region and the first drain region.

21. The method for forming a semiconductor structure as described in claim 18, characterized in that, The conductivity type of the first well region is opposite to that of the second well region; the conductivity types of the second source region and the second drain region are opposite to those of the first source region and the first drain region.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The process of incorporating dopant ions into the second gate structure is a single process, which is the same as the process of forming the first source region and the first drain region.

23. The method for forming a semiconductor structure as described in claim 17, characterized in that, The substrate includes: a base and a fin structure located on the base, the fin structure including a first fin located on a first region and a second fin located on a second region; a first gate structure spanning the first fin, and a second gate structure spanning the second fin; a first well region located within the first fin, and a second well region located within the second fin.

24. The method for forming a semiconductor structure as described in claim 23, characterized in that, Before forming the first gate structure, the method further includes: implanting anti-penetration ions into the first fin, wherein the conductivity type of the anti-penetration ions is the same as that of the first well region.

25. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process for forming the first connection region includes an ion implantation process; the conductivity type of the first connection region is the same as that of the first well region, and the ion concentration in the first connection region is greater than that in the first well region.

26. The method for forming a semiconductor structure as described in claim 18, characterized in that, Also includes: A first conductive structure and a second conductive structure are formed on a substrate. The first conductive structure electrically interconnects the second drain region and the first gate structure, and the second conductive structure electrically interconnects the second source region and the first connection region.

27. The method for forming a semiconductor structure as described in claim 26, characterized in that, The second conductive structure is also electrically connected to the first source region.

28. The method for forming a semiconductor structure as described in claim 26, characterized in that, The method for forming the first conductive structure and the second conductive structure includes: forming a dielectric structure on a substrate, wherein the first gate structure and the second gate structure are located within the dielectric structure; and forming the first conductive structure and the second conductive structure within the dielectric structure.

29. The method for forming a semiconductor structure as described in claim 17, characterized in that, Also includes: A second connection region is formed on the surface of the second well region; the second gate structure and the second well region are electrically connected through the second connection region.

30. The method for forming a semiconductor structure as described in claim 29, characterized in that, The process for forming the second connection region includes an ion implantation process; the conductivity type of the second connection region is the same as that of the second well region, and the ion concentration in the second connection region is greater than that in the second well region.

31. The method for forming a semiconductor structure as described in claim 29, characterized in that, Also includes: A third conductive structure is formed on the substrate, the third conductive structure being electrically connected to the second gate structure and the second connection region.

32. The method for forming a semiconductor structure as described in claim 17, characterized in that, The gate dielectric layer is made of a high dielectric constant material, the high dielectric constant material having a dielectric constant greater than 3.9, the high dielectric constant material including alumina or hafnium oxide, and the gate layer is made of a metal, the metal including tungsten.

33. The method for forming a semiconductor structure as described in claim 32, characterized in that, The first gate structure further includes a work function layer, which is located between the gate dielectric layer and the gate layer; the material of the work function layer includes an N-type work function material or a P-type work function material, wherein the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.

34. The method for forming a semiconductor structure as described in claim 17, characterized in that, The material of the second gate structure includes silicon.

35. The method for forming a semiconductor structure as described in claim 17, characterized in that, The first well region has a conductivity type of N-type or P-type, and the second well region has a conductivity type of N-type or P-type; ions with an N-type conductivity type include phosphorus ions, arsenic ions, or antimony ions; ions with a P-type conductivity type include boron ions, boron-fluorine ions, or indium ions.

36. A protection circuit, characterized in that, include: The first transistor includes a first gate, a second source, a second drain, and a first well region. The second source and the second drain are respectively coupled to a power supply voltage node and a ground voltage node. The first gate includes a gate dielectric layer and a gate layer located on the gate dielectric layer. The second transistor includes a second gate, a first source, a first drain, and a second channel region. The first drain is coupled to the first gate. The first source and the first drain have the same conductivity type as the second channel region. The first source and the first well region are electrically interconnected through a first connection region. The first source is coupled to a power supply voltage node. The second transistor is a junction transistor.

37. The protection circuit as described in claim 36, characterized in that, The first transistor is an N-type transistor; the second source is coupled to the ground voltage node, and the second drain is coupled to the power supply voltage node.

38. The protection circuit as described in claim 36, characterized in that, The first transistor is a P-type transistor; the second source is coupled to the power supply voltage node, and the second drain is coupled to the ground voltage node.

39. The protection circuit as described in claim 36, characterized in that, The second transistor is an N-type transistor or a P-type transistor.

40. A method for operating a protection circuit, characterized in that, include: A protection circuit is provided, comprising: a first transistor, the first transistor including a first gate, a second source, a second drain and a first well region, the second source and the second drain being coupled to a power supply voltage node and a ground voltage node respectively, the first gate including a gate dielectric layer and a gate layer located on the gate dielectric layer; and a second transistor, the second transistor including a second gate, a first source, a first drain and a second channel region, the first drain being coupled to the first gate, the first source and the first drain having the same conductivity type as the second channel region, the first source and the first well region being electrically interconnected through a first connection region, the first source being coupled to the power supply voltage node, and the second transistor being a junction transistor; A first voltage is applied to the first gate; A second voltage is applied to the second gate.

41. The method of operating the protection circuit as described in claim 40, characterized in that, The protection circuit further includes: the first transistor is an N-type transistor; the second source is coupled to the ground voltage node, and the second drain is coupled to the power supply voltage node.

42. The operating method of the protection circuit as described in claim 40, characterized in that, The protection circuit further includes: the first transistor is a P-type transistor; the second source is coupled to the power supply voltage node, and the second drain is coupled to the ground voltage node.

43. The method of operating the protection circuit as described in claim 40, characterized in that, The second transistor is an N-type transistor or a P-type transistor.

44. The method of operating the protection circuit as described in claim 43, characterized in that, When the second transistor is an N-type transistor, the range of the second voltage is less than 0; when the second transistor is a P-type transistor, the range of the second voltage is greater than the power supply voltage.

45. The method of operating the protection circuit as described in claim 40, characterized in that, The first voltage ranges from 0 to the power supply voltage.

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