半导体结构与其形成方法
By increasing the dielectric constant and thickness of the top gate dielectric layer in the semiconductor structure, the leakage problem of the semiconductor structure is solved, and better electrical isolation is achieved.
CN115411096BActive Publication Date: 2026-07-17NAN YA TECH
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2021-06-24
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
With the high integration of DRAM, semiconductor structures are prone to leakage in the off state, such as gate-induced drain leakage (GIDL), which is difficult to solve effectively with existing technologies.
Method used
By designing the top gate dielectric layer in the semiconductor structure to have a higher dielectric constant than the bottom gate dielectric layer, and increasing the thickness of the top gate dielectric layer, better electrical barrier can be formed, reducing leakage current.
Benefits of technology
It effectively reduces leakage current in semiconductor structures without affecting structural performance.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN115411096B_ABST
Abstract
一种半导体结构包括基材、形成于基材内的底部栅极导电层、形成于基材内并堆叠在底部栅极导电层上的顶部栅极导电层、形成于底部栅极导电层与基材之间的底部栅极栅极介电层、形成于顶部栅极导电层与基材之间的顶部栅极介电层。顶部栅极介电层的厚度大于底部栅极介电层的厚度。半导体结构也包括数个源极 / 汲极区，形成于基材内并位于顶部栅极导电层的相对两侧。借由提升顶部栅极介电层的介电常数、增厚顶部栅极介电层的厚度、或上述两者的结合，以提供较好的电性阻隔，借此减少半导体结构产生漏电的现象。
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