A MOS radiation-hardened device with a leaky-end composite SBD structure and a preparation method thereof

Abstract

A MOS radiation-resistant device with a drain-end composite SBD structure and a preparation method thereof, comprising a single-crystal Si substrate. The surface of the Si substrate is a P-type Si layer. The side of the P-type Si layer is a trench filled with SiO2 material. The surface of the P-type Si layer is a gate oxide layer. The surface of the gate oxide layer is polysilicon. On the P-type Si layer on both sides of the gate oxide layer are lightly doped source and drain regions. At the P-type Si layer between the lightly doped source and drain regions and the SiO2 material is a heavily doped source and drain region. The surface of the heavily doped source and drain region is a metal wire layer. The surface of the lightly doped source and drain region is a Si sidewall. On both sides of the Si sidewall are SiO2 sidewalls. The surface of the Si sidewall is an aluminum metal layer. The surface of the aluminum metal layer is a metal wire layer. The surface of the metal wire layer is a SiN material for passivation dielectric. The present invention solves the influence of single-event effect on the logic state of the device from the device perspective, enables the integrated circuit built with this radiation-resistant MOS device as the basic unit to work stably in a high-radiation environment, and has a simple SBD process embedded at the drain end with low manufacturing cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a MOS radiation-resistant device with a drain-end composite SBD structure and a preparation method thereof. Background Art

[0002] Whether in the field of nuclear physics or for aerospace-grade integrated circuits, they are in a complex radiation environment. In space, due to the loss of the protection of the Earth's atmosphere, aerospace-grade integrated circuits are directly exposed to the radiation of cosmic rays and high-energy particles. These radiations can cause ordinary integrated circuits to be unable to work stably or even fail permanently. Therefore, it is necessary to improve the stability and reliability of integrated circuits to ensure that equipment operating in a high-radiation environment can operate correctly.

[0003] In the field of integrated circuit radiation-hardening in China's aerospace and nuclear physics at present, there is still a large room for improvement in some key technologies such as circuit hardening and packaging module. Due to the limitations of these technical problems, the development of aerospace and nuclear physics is hindered. Just because of this, it is necessary to increase the research and development of radiation-resistant integrated circuits in order to better promote the development of aerospace and nuclear physics.

[0004] The existing hardening technologies in China mainly break through from the following 4 aspects:

[0005] (1) Search for semiconductors with better radiation resistance. Since the radiation effect mainly bombards semiconductor materials to generate electron-hole pairs, thereby affecting the logic state of the circuit, finding a new type of composite semiconductor material with a lower carrier lifetime can weaken the adverse effects brought by irradiation;

[0006] (2) Starting from the circuit level, design a circuit structure with radiation resistance, such as dual-mode redundancy, dual-interlocked latch storage structure, etc.;

[0007] (3) Starting from the layout level, when performing layout design, adopt special structures such as a ring gate structure and a protected drain to weaken the influence of the ionization radiation effect;

[0008] (4) Starting from the process packaging perspective, use special ceramic packaging to strengthen the protection of the circuit and weaken the irradiation effect of high-energy particles on internal devices. These methods can weaken the single-event effect to a certain extent, but they have many disadvantages, such as it is difficult to find a new type of composite semiconductor material and it is not compatible with existing process technologies, it will generate an additional radiation-resistant circuit structure, it is necessary to specifically design the layout and it will increase the layout area, and using ceramic packaging makes the chip safety highly dependent on the packaging, etc. These aspects will increase the design cost and the reliability is highly dependent on ceramic packaging, which is not conducive to the production and application of radiation-resistant integrated circuit chips. Summary of the Invention

[0009] In order to overcome the deficiencies of the above-mentioned existing technologies, the object of the present invention is to provide a MOS radiation-resistant device with a drain-end composite SBD structure and a preparation method thereof, so as to solve the problems of logical level error flipping of semiconductor devices or permanent damage of devices caused by single-event effects. From the device perspective, the influence of single-event effects on the logical state of the device is solved, and it is realized that the integrated circuit built with this radiation-resistant MOS device as the basic unit can work stably in a high-radiation environment. An SBD is embedded at the drain end, and the process is simple and the manufacturing cost is low.

[0010] In order to achieve the above object, the technical solution adopted by the present invention is:

[0011] A MOS radiation-resistant device with a drain-end composite SBD structure includes a single-crystal Si substrate. The surface of the Si substrate is a P-type Si layer. The side of the P-type Si layer is a trench filled with SiO2 material. The surface of the P-type Si layer is a gate oxide layer. The surface of the gate oxide layer is polysilicon. On the P-type Si layer on both sides of the gate oxide layer are lightly doped source / drain regions. At the P-type Si layer between the lightly doped source / drain regions and the SiO2 material is a heavily doped source / drain region. The surface of the heavily doped source / drain region is a metal wire layer. The surface of the lightly doped source / drain region is a Si sidewall. On both sides of the Si sidewall are SiO2 sidewalls. The surface of the Si sidewall is an aluminum metal layer. The surface of the aluminum metal layer is a metal wire layer. The surface of the metal wire layer is SiN material for passivating the dielectric.

[0012] The surface of the gate oxide layer is polysilicon, and the outside is a SiO2 sidewall.

[0013] The metal wire layer is located in the metal contact hole on the BPSG formed dielectric layer.

[0014] A preparation method of a MOS radiation-resistant device with a drain-end composite SBD structure includes the following steps;

[0015] S101. Select a single-crystal Si substrate;

[0016] S102. Clean the Si substrate using the RCA method, and then clean it with 10% hydrofluoric acid to remove the Si surface oxide layer;

[0017] S103. Dope P-type impurities into the Si substrate, and the doping concentration is about 1.5×10 16 cm -3 to form a P-type Si substrate;

[0018] S104. At a certain temperature, deposit a P-type Si layer on the surface of the Si substrate using molecular beam epitaxy technology;

[0019] S105. Deposit a silicon dioxide protective layer; deposit a large SiO2 layer on the P-type Si layer using CVD technology;

[0020] S106. Deposit Si3N4 material with a thickness of about 100 nm on the surface of the SiO2 material using the CVD process. Since there is a large difference in the thermal expansion coefficients between silicon nitride and silicon, in order to prevent the silicon surface from being affected by thermal stress, the thin oxide layer SiO2 grown between the silicon nitride and the silicon plays a buffering role;

[0021] S107. Etch away the Si3N4 and SiO at the positions where the trench regions need to be formed on the Si3N4 material and the thin oxide layer SiO2; 2， Form rectangular trench windows required for shallow trench isolation on both sides of the device;

[0022] S108. Through the trench region window, use the dry etching process to etch a trench with a depth of about 300 nm in the P-type Si layer;

[0023] S109. Fill the trench obtained in S108 with SiO2 material using the CVD process;

[0024] S110. Use the CMP method to remove the excess silicon dioxide on the surface; Since silicon nitride has strong anti-polishing ability and acts as a polishing stop layer for the CMP process, all the SiO2 above the Si3N4 is polished away to obtain a flat surface;

[0025] S111. Etch the Si3N4 material and the thin oxide layer SiO2 between the SiO2 columns using H3PO4 and HF respectively, and make the surface of the P-type Si layer flat to obtain a flat surface for shallow trench isolation;

[0026] S112. Deposit a thin, dense, flat and defect-free gate oxide layer;

[0027] S113. Deposit a layer of polysilicon on the gate oxide layer as the gate electrode material;

[0028] S114. Perform etching to retain only the polysilicon used as the gate electrode and for interconnection;

[0029] S115. Coat the entire wafer surface with photoresist, etch a window for NMOS transistor source / drain doping on the photoresist, and use the ion implantation process to perform ion implantation on the NMOS active region to form lightly doped source / drain regions;

[0030] S116. Remove the photoresist applied in step S115, re-cover the NMOS transistor with photoresist, etch only a region with a width of about 16 nm on the gate and on both sides of the gate, and deposit SiO2 to produce sidewalls;

[0031] S117. Remove the photoresist coated in step S116, reuse the photoresist to cover the NMOS transistor, etch only the wide area additionally on the basis of both sides of the gate and the sidewall, deposit a lightly doped Si sidewall, and this Si is used to fabricate the semiconductor in the SBD;

[0032] S118. Remove the photoresist coated in step S117, reuse the photoresist to cover the NMOS transistor, etch windows that are 5 nm wider than the gate and both sidewalls on both sides, deposit SiO2 to produce sidewalls for isolating the source-drain and the SBD;

[0033] S119. Using the sidewall as a mask, form a heavily doped source-drain region by a self-alignment method to form the source-drain and complete the LDD region; the LDD region is LDD (lightly doped drain), LDS (lightly doped source);

[0034] S120. Use the CMP process to remove the excess SiO2 and make the silicon wafer surface flat;

[0035] S121. Use the CVD process to deposit BPSG on the entire silicon wafer surface to form a dielectric layer;

[0036] S122. Coat photoresist on the SiO2 surface and remove the photoresist above the Si sidewall to generate a window for depositing the SBD metal layer;

[0037] S123. Use the sputtering technique to deposit the aluminum metal layer in the SBD, and then remove the photoresist;

[0038] S124. Use the CVD process again to deposit a layer of BPSG on the silicon wafer surface to protect the SBD;

[0039] S125. Use nitric acid and hydrofluoric acid to etch BPSG to form a dielectric layer to form a metal contact hole;

[0040] S126. Use the electron beam evaporation process to deposit a metal wire layer 016 with a thickness of 15 nm on the entire substrate surface to form a metal electrode;

[0041] S127. Use the selective etching process to etch the metal of the metal wire layer between the metal contact holes, and use the CMP process for planarization;

[0042] S128. Use the CVD process to deposit SiN material on the entire substrate surface for passivation dielectric, and finally form the MOS radiation-resistant device with the leakage-end composite SBD structure.

[0043] The temperature in S104 is 500 - 600 °C, the thickness of the P-type Si layer is 300 nm, and the doping concentration is about 3×10 18 cm -3 ;

[0044] In S105, the thickness of the SiO2 layer is 20 - 30 nm.

[0045] In S112, the thickness of the gate oxide layer is about 2 - 3 nm; in S113, the thickness of the polysilicon is 10 nm and the width is about 7 nm;

[0046] In S115, the lightly doped source / drain region has a doping concentration of 3.0×10 17 cm -3 ; in S116, the deposited thickness of the SiO2 sidewall is 10 nm; in S117, the width of the lightly doped Si sidewall is 5 nm; the doping concentration of the lightly doped Si sidewall is 3.0×10 17 cm -3 , and for the semiconductor in the SBD, the thickness of the Si sidewall is 5 nm.

[0047] In S118, the deposited SiO2 forms a sidewall with a thickness of 10 nm; in S119, the doping concentration of the heavily doped source / drain region is about 4.02×10 20 cm -3 , forming the source / drain and completing the LDD region; in S121, the formed BPSG dielectric layer has a thickness of 15 nm; in S123, the thickness of the aluminum metal layer is 5 nm; in S128, the thickness of the SiN material is 20 - 30 nm.

[0048] Advantages of the present invention:

[0049] In the present invention, an SBD structure is added at the drain end, eliminating radiation effects such as single - event upset and single - event transient, enabling the MOS device to operate stably for a long time in a high - radiation environment, thus greatly improving the reliability of aerospace - grade equipment. Moreover, the present invention is based on a traditional MOS device, with an SBD embedded at the source and drain ends of the device, having good process compatibility with CMOS. Starting from the root of the device, the single - event effect is eliminated. Compared with other anti - radiation hardening technologies such as adding circuit structures and changing layout design methods, the design structure is simple, and the reliability of aerospace - grade equipment and the like is greatly improved. The aerospace - grade integrated circuit structure composed of this device does not require additional anti - radiation circuit structures and device layouts, can significantly reduce the manufacturing cost of aerospace - grade integrated circuits, and the anti - radiation performance is also significantly improved. Description of the Drawings

[0050] Figure 1 It is a schematic diagram of a single - crystal Si substrate.

[0051] Figure 2 It is a schematic diagram of depositing a P - type Si layer on the surface of the Si substrate.

[0052] Figure 3 It is a schematic diagram of depositing a silicon dioxide protective layer.

[0053] Figure 4 Schematic diagram for depositing a Si3N4 material with a thickness of approximately on the surface of the SiO2 material.

[0054] Figure 5 Schematic diagram for etching away the area where the trench region needs to be formed on the Si3N4 and SiO2 layers.

[0055] Figure 6 Schematic diagram for etching a trench in the silicon substrate.

[0056] Figure 7 Schematic diagram for filling the trench with SiO2 material.

[0057] Figure 8 Schematic diagram for removing the excess silicon dioxide on the surface.

[0058] Figure 9 Schematic diagram for etching the Si3N4 and SiO2 on the surface using H3PO4 and HF to obtain a flat surface for shallow trench isolation.

[0059] Figure 10 Schematic diagram for depositing a thin gate oxide layer.

[0060] Figure 11 Schematic diagram for depositing a layer of polysilicon on the gate oxide layer.

[0061] Figure 12 Schematic diagram for the polysilicon that serves as an interconnection.

[0062] Figure 13 Schematic diagram for etching a window on the photoresist for source / drain doping of the NMOS transistor.

[0063] Figure 14 Schematic diagram for depositing SiO2 to form sidewalls.

[0064] Figure 15 Schematic diagram for depositing a lightly doped Si sidewall.

[0065] Figure 16 Schematic diagram for depositing SiO2 to form sidewalls.

[0066] Figure 17 Schematic diagram for the heavily doped source / drain region.

[0067] Figure 18 Schematic diagram for planarizing the deposited SiO2 sidewalls.

[0068] Figure 19 Schematic diagram for depositing a BPSG with a thickness on the silicon wafer surface to form a dielectric layer.

[0069] Figure 20 Schematic diagram for generating the SBD metal layer to be deposited.

[0070] Figure 21 Schematic diagram of the metal layer in the SBD deposition.

[0071] Figure 22 Schematic diagram of the BPSG deposition.

[0072] Figure 23 Schematic diagram of forming a metal contact hole by etching BPSG with nitric acid and hydrofluoric acid.

[0073] Figure 24 Schematic diagram of forming a metal electrode from the metal wire layer.

[0074] Figure 25 Schematic diagram of etching the metal in the specified area by the selective etching process.

[0075] Figure 26 Schematic diagram of the MOS structure of the composite SBD at the drain end of the present invention.

[0076] Figure 27 Schematic diagram of the single event effect mechanism of the present invention. Detailed implementation manners

[0077] The present invention will be further described in detail below with reference to the accompanying drawings.

[0078] The present invention provides a method for manufacturing a MOS device with a composite SBD structure at the drain end, and the manufacturing method is as follows:

[0079] S101: As shown in Figure 1 , select a single crystal Si substrate 001;

[0080] S102: Clean the Si substrate using the RCA method, and then clean it with 10% hydrofluoric acid to remove the oxide layer on the Si surface;

[0081] S103: Dope P-type impurities into the substrate Si, and the doping concentration is about 1.5×10 16 cm -3 to form a P-type Si substrate;

[0082] S104: As shown in Figure 2 , at a temperature of 500 - 600 °C, deposit a P-type Si layer 002 with a thickness of 300 nm on the surface of the Si substrate by molecular beam epitaxy technology, and the doping concentration is about 3×10 18 cm -3 ;

[0083] S105: As shown in Figure 3 , deposit a silicon dioxide protective layer. Deposit a SiO2 layer 003 of about 20 - 30 nm on the Si substrate by CVD technology;

[0084] S106: As shown in Figure 4, using the CVD process, deposit Si3N4 material with a thickness of about 100 nm on the surface of the SiO2 material 004. Since there is a large difference in the thermal expansion coefficients between silicon nitride and silicon, in order to prevent the silicon surface from being affected by thermal stress, the thin oxide layer grown between the silicon nitride and the silicon plays a buffering role;

[0085] S107, such as Figure 5 , etch away the Si3N4 and SiO at the positions where the trench region needs to be formed on the Si3N4 and SiO2 layers 2， to form a trench region window;

[0086] S108, such as Figure 6 , through the trench region window, use the dry etching process to etch a trench with a depth of about 300 nm in the silicon substrate;

[0087] S109, such as Figure 7 , use the CVD process to fill the trench with SiO2 material 005;

[0088] S110, such as Figure 8 , use the CMP method to remove the excess silicon dioxide on the surface. Since silicon nitride has strong anti-polishing ability and acts as a polishing stop layer for the CMP process, all the SiO2 above the Si3N4 is polished and removed to obtain a flat surface;

[0089] S111, such as Figure 9 , respectively use H3PO4 and HF to etch the Si3N4 and SiO2 on the surface to obtain a flat surface of shallow trench isolation.

[0090] S110, such as Figure 10 , deposit a high-quality thin gate oxide layer 006 with a thickness of about 2 - 3 nm;

[0091] S111, such as Figure 11 , deposit a layer of polysilicon 007 on the gate oxide layer as the gate electrode material;

[0092] S112, such as Figure 12 , perform etching to retain only the polysilicon used as the gate electrode and for interconnection;

[0093] S113, such as Figure 13 , etch a window for NMOS transistor source / drain doping on the photoresist, and use the ion implantation process to perform ion implantation on the NMOS active region to form a lightly doped source / drain region 008 with a doping concentration of 3.0×10 17 cm -3 ;

[0094] S114, such as Figure 14, Remove the previous photoresist, reuse the photoresist to cover the NMOS transistor, etch out regions with a width of approximately 16 nm only at the gate and on both sides of the gate, deposit SiO2 to produce sidewall 009;

[0095] S115, As Figure 15 , Remove the previous photoresist, reuse the photoresist to cover the NMOS transistor, additionally etch a region with a width of 5 nm on the basis of both sides of the gate and the sidewalls, deposit lightly doped Si sidewall 010, and this Si is used to fabricate the semiconductor in the SBD;

[0096] S116, As Figure 16 , Remove the previous photoresist, reuse the photoresist to cover the NMOS transistor, etch out windows that are 5 nm wider than the gate and the sidewalls on both sides, deposit SiO2 to produce sidewall 011, which is used to isolate the source-drain and the SBD;

[0097] S117, As Figure 17 , Using the sidewall as a mask, form a heavily doped source-drain region 012 with a doping concentration of approximately 4.02×10 20 cm -3 , to form the source-drain and complete the LDD region;

[0098] S118, As Figure 18 , Use the CMP process to planarize the surface of the silicon wafer;

[0099] S119, As Figure 19 , Use the CVD process to deposit a BPSG layer with a thickness of 15 nm on the entire surface of the silicon wafer to form dielectric layer 013;

[0100] S120, As Figure 20 , Coat photoresist 014 on the SiO2 surface and generate a window for depositing the SBD metal layer;

[0101] S121, As Figure 21 , Use sputtering technology to deposit the metal layer 015 in the SBD, and then remove the photoresist;

[0102] S122, As Figure 22 , Use the CVD process again to deposit a layer of BPSG on the silicon wafer surface to protect the SBD;

[0103] S123, As Figure 23 , Use nitric acid and hydrofluoric acid to etch the BPSG to form metal contact holes;

[0104] S124, As Figure 24 , Use electron beam evaporation technology to deposit a metal wire layer 016 with a thickness of 15 nm on the entire surface of the substrate to form a metal electrode;

[0105] S125. As shown in Figure 25 , etch the metal in the specified area using a selective etching process, and perform planarization using a CMP process;

[0106] S126. As shown in Figure 26 , deposit a SiN material 017 with a thickness of 20 - 30 nm on the entire substrate surface using a CVD process for passivating the dielectric, and finally form the MOS radiation-hardened device with the drain-end composite SBD structure.

[0107] As shown in Figure 26 . When the pulse current caused by the single-event effect arrives, on the one hand, it can mitigate the lateral electric field, so as to avoid the avalanche effect of the generated electron-hole pairs as much as possible. On the other hand, it can collect charges through this branch of the SBD, allowing part of the pulse current to flow out of the working circuit, so that the single-event pulse current will not change the original logic state of the device. The mechanism is as shown in Figure 27 .

[0108] It should also be noted that since the SBD is embedded in the MOS structure, on the one hand, the metal in the SBD is grounded, and it has a strong shunting ability when the pulse current arrives. On the other hand, the influence of the SBD structure on the normal operation of the original device can be reduced by adjusting the thickness of the semiconductor in the SBD structure. After embedding the SBD, to a certain extent, the current during the normal operation of the original MOS will change. In order to weaken this influence without weakening the radiation-hardening characteristics of the device, but the radiation-hardening characteristics will be weakened as the thickness of the semiconductor in the SBD increases, so a compromise is needed. Through experiments and simulation analysis, it is finally determined that the thickness of the embedded SBD is 10 nm, and its MOS radiation-hardening characteristics are better.

Claims

1. A MOS radiation-resistant device with a leaky-end composite SBD structure, characterized in that It includes a single-crystal Si substrate (001), with a P-type Si layer (002) on the surface of the Si substrate (001). There are grooves on the sides of the P-type Si layer (002), and the grooves are filled with SiO2 material (005). On the surface of the P-type Si layer (002) is a gate oxide layer 006, and on the surface of the gate oxide layer (006) is polysilicon (007). On the P-type Si layer (002) on both sides of the gate oxide layer 006 are lightly doped source / drain regions (008). At the P-type Si layer (002) between the lightly doped source / drain regions (008) and the SiO2 material (005) is a heavily doped source / drain region (012). On the surface of the heavily doped source / drain region (012) is a metal wire layer (016). On the surface of the lightly doped source / drain regions (008) is deposited a lightly doped Si sidewall (010). On both sides of the deposited lightly doped Si sidewall (010) are SiO2 sidewalls (011). On the surface of the Si sidewall (010) is an aluminum metal layer (015). On the surface of the aluminum metal layer (015) is a metal wire layer (016). On the surface of the metal wire layer (016) is a SiN material (017) for passivation dielectric.

2. The MOS radiation-resistant device with a leaky-end composite SBD structure according to claim 1, characterized in that, On the surface of the gate oxide layer (006) is polysilicon (007), and on the outside is a SiO2 sidewall (009).

3. The MOS radiation-resistant device with a leaky-end composite SBD structure according to claim 1, characterized in that, The metal wire layer (016) is located in a metal contact hole on a BPSG formed dielectric layer (013).

4. A method for manufacturing a MOS radiation-resistant device with a drain-end composite SBD structure according to any one of claims 1-3, characterized in that, It includes the following steps; S101. Select a single-crystal Si substrate (001); S102. Clean the Si substrate using the RCA method, and then clean it with 10% hydrofluoric acid to remove the Si surface oxide layer; S103. Dope the Si substrate (001) with P-type impurities at a doping concentration of approximately 1.5×10 16 cm -3 , to form a P-type Si substrate; S104. At a certain temperature, deposit a P-type Si layer (002) on the surface of the Si substrate (001) using molecular beam epitaxy technology; S105. Deposit a silicon dioxide protection layer; Deposit a large SiO2 layer (003) on the P-type Si layer (002) using CVD technology; S106. Deposit a Si3N4 material (004) with a thickness of about 100 nm on the surface of the SiO2 material using CVD technology. The thin oxide layer SiO2 (003) grown between the silicon nitride and the silicon serves as a buffer; S107. Etch away Si3N4 and SiO at the positions where the trench region needs to be formed on the Si3N4 material (004) and the thin oxide layer SiO2 (003). 2， Form rectangular trench windows required for shallow trench isolation on both sides of the device. S108. Through the trench region window, use dry etching technology to etch a trench with a depth of about 300 nm in the P-type Si layer (002); S109. Fill the trench obtained in S108 with SiO2 material (005) using CVD technology; S110. Use the CMP method to remove the excess silicon dioxide on the surface; S111. Etch the Si3N4 material (004) and the thin oxide layer SiO2 (003) between the SiO2 columns (005) using H3PO4 and HF respectively, and make the surface of the P-type Si layer (002) flat to obtain a flat surface of shallow trench isolation; S112. Deposit a thin, dense, flat and defect-free gate oxide layer (006); S113. Deposit a layer of polysilicon (007) on the gate oxide layer 006 as the gate electrode material; S114. Perform etching to only retain the polysilicon (007) used as the gate electrode and for interconnection; S115. Apply photoresist on the entire wafer surface, etch a window for source-drain doping of NMOS transistors on the photoresist, and use the ion implantation process to perform ion implantation on the NMOS active region to form lightly doped source and drain regions (008). S116. Remove the photoresist applied in step S115, reuse the photoresist to cover the NMOS transistor, and only etch a region with a width of about 16 nm on the gate and both sides of the gate, and deposit SiO2 to produce sidewalls (009). S117. Remove the photoresist applied in step S116, reuse the photoresist to cover the NMOS transistor, and etch an additional wide region based on the gate and both sides of the sidewalls, and deposit lightly doped Si sidewalls (010). This Si is used to fabricate the semiconductor in the SBD. S118. Remove the photoresist applied in step S117, reuse the photoresist to cover the NMOS transistor, etch a window that is 5 nm wider than the gate and both sidewalls on each side, and deposit SiO2 to produce sidewalls (011) to isolate the source and drain from the SBD. S119. Using the sidewalls as a mask, form heavily doped source and drain regions (012) by a self-aligned method to form the source and drain and complete the LDD region; the LDD region is LDD (lightly doped drain), LDS (lightly doped source). S120. Use the CMP process to remove the excess SiO2 to make the silicon wafer surface flat. S121. Use the CVD process to deposit BPSG on the entire silicon wafer surface to form a dielectric layer (013). S122. Apply photoresist on the SiO2 surface (014), and remove the photoresist above the Si sidewalls (010) to generate a window for depositing the SBD metal layer. S123. Use sputtering technology to deposit the aluminum metal layer (015) in the SBD, and then remove the photoresist. S124. Use the CVD process again to deposit a layer of BPSG on the silicon wafer surface to protect the SBD. S125. Use nitric acid and hydrofluoric acid to etch BPSG to form a dielectric layer (013) to form metal contact holes. S126. Use the electron beam evaporation process to deposit a metal wire layer with a thickness of 15 nm on the entire substrate surface (016) to form metal electrodes. S127. Use the selective etching process to etch the metal in the metal wire layer between the metal contact holes, and use the CMP process for planarization. S128. Use the CVD process to deposit SiN material (017) on the entire substrate surface for passivation dielectric, and finally form the MOS radiation-resistant device with the leakage-end composite SBD structure.

5. The preparation method of a MOS radiation-resistant device with a leakage-end composite SBD structure according to claim 4, characterized in that, The temperature in S104 is 500 - 600 °C, the thickness of the P-type Si layer (002) is 300 nm, and the doping concentration is about 3×10 18 cm -3 ; In the above S105, the thickness of the SiO2 layer (003) is 20 - 30 nm.

6. The manufacturing method of a MOS radiation-resistant device with a leakage-end composite SBD structure according to claim 4, characterized in that In the above S112, the thickness of the gate oxide layer (006) is 2 - 3 nm; in S113, the thickness of the polysilicon (007) is 10 nm, and the width is about 7 nm. The lightly doped source / drain regions (008) in S115 have a doping concentration of 3.0×10 17 cm -3 ; the SiO2 sidewall (009) in S116 has a deposition thickness of 10 nm; the lightly doped Si sidewall (010) in S117 is 5 nm wide; the lightly doped Si sidewall (010) has a doping concentration of 3.0×10 17 cm -3 , and the semiconductor in the SBD, the Si sidewall (010) with a thickness of 5 nm.

7. The manufacturing method of a MOS radiation-resistant device with a drain-end composite SBD structure according to claim 4, characterized in that, In S118, SiO2 is deposited to form sidewalls (011) with a thickness of 10 nm; in S119, the doping concentration of the heavily doped source / drain regions (012) is approximately 4.02×10 20 cm -3 , forming the source / drain and completing the LDD region; in S121, BPSG forms a dielectric layer (013) with a thickness of 15 nm; in S123, the aluminum metal layer (015) has a thickness of 5 nm; in S128, the SiN material (017) has a thickness of 20 - 30 nm.

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