Method for manufacturing an antenna package and antenna package

Abstract

A manufacturing method of an antenna package includes the following steps: providing a first intermediate body, the first intermediate body includes a first circuit substrate, a feed line layer and a second circuit substrate which are arranged in a stack, the second circuit substrate is provided with a cavity on a surface thereof away from the feed line layer, and the first circuit substrate includes an antenna layer; providing a second intermediate body, the second intermediate body includes a third circuit substrate and a chip, and the chip is located on a surface of the third circuit substrate; arranging the chip corresponding to the cavity, and pressing the first intermediate body and the second intermediate body to form the antenna package. The application further provides an antenna package.

Description

Technical Field

[0001] The present application relates to the field of antenna packaging, and in particular to a method for manufacturing an antenna packaging body and the antenna packaging body. Background Art

[0002] With the advent of the 5G high-speed communications era, millimeter-wave communications are becoming a hot topic, and demand for millimeter-wave antenna design and application is growing rapidly. Because the length of the transmission path in the millimeter-wave band significantly affects signal amplitude loss, and millimeter-wave antennas require very high machining precision, packaged antenna technology with extremely short antenna feed paths and high machining precision has become one of the mainstream technologies in the millimeter-wave antenna field.

[0003] Conventional antenna packaging techniques involve first encapsulating the chip with a molding resin, then further processing the redistribution layer (RDL), or forming the RDL on a carrier and temporarily bonding it to the chip before compression molding. These methods typically require multiple wiring runs, increasing the risk of peeling or warping due to thermal effects. The temporary bonding material used must possess high viscosity, high temperature resistance, and high chemical resistance, increasing material usage and the bonding process. Summary of the Invention

[0004] In view of this, it is necessary to provide a method for manufacturing an antenna package that reduces the pressing process and reduces the cost, so as to solve the above problems.

[0005] In addition, it is necessary to provide an antenna package.

[0006] A method for manufacturing an antenna package includes the following steps: providing a first intermediate body, the first intermediate body including a first circuit substrate, a feeder layer, and a second circuit substrate arranged in a stacked manner, the second circuit substrate having a cavity defined on a surface facing away from the feeder layer, and the first circuit substrate including an antenna layer; providing a second intermediate body, the second intermediate body including a third circuit substrate and a chip, the chip being located on the surface of the third circuit substrate; arranging the chip corresponding to the cavity, and pressing the first intermediate body and the second intermediate body together to form the antenna package.

[0007] In some embodiments, the step of forming the second intermediate body includes: providing the third circuit substrate, the third circuit substrate including a third dielectric layer and a third circuit layer stacked together; and electrically connecting the chip on a surface of the third circuit substrate.

[0008] In some embodiments, the third circuit layer includes a copper layer, an area of ​​the copper layer along the stacking direction of the third circuit substrate is larger than an area of ​​the chip, and the chip is located within a projected area of ​​the copper layer.

[0009] In some embodiments, the third circuit substrate is away from the surface of the first intermediate body.

[0010] In some embodiments, the first circuit substrate and the feed line layer are electrically connected by conductive paste, and the conductive paste is overlapped in the stacking direction of the first intermediate body.

[0011] An antenna package includes a first circuit substrate, a feed line layer, a second circuit substrate, a third circuit substrate, and a chip. The first circuit substrate includes an antenna layer. The feed line layer is located on a surface of the first circuit substrate. The second circuit substrate is located on a surface of the feed line layer away from the first circuit substrate. The third circuit substrate is located on a surface of the second circuit substrate away from the feed line layer. The chip is embedded in the second circuit substrate and electrically connected to the third circuit substrate.

[0012] In some embodiments, the first circuit substrate further includes a first dielectric layer and a first circuit layer. The first dielectric layer and the first circuit layer are stacked. At least part of the antenna layer is located on a surface of the first dielectric layer away from the feed line layer.

[0013] In some embodiments, the antenna layer includes an excitation radiation patch and a main radiation patch. The excitation radiation patch is located on a surface of the first dielectric layer away from the feed line layer. The main radiation patch is embedded in the first dielectric layer.

[0014] In some embodiments, the feed line layer includes an intermediate dielectric layer and an intermediate circuit layer. The intermediate circuit layer is located on opposite surfaces of the intermediate dielectric layer and is electrically connected by a conductive hole penetrating the intermediate dielectric layer. The second circuit substrate includes a second dielectric layer and a second circuit layer stacked. The second circuit layer is electrically connected to the intermediate circuit layer.

[0015] In some embodiments, the first circuit substrate includes a first dielectric layer, the feed line layer includes an intermediate dielectric layer, and the second circuit substrate includes a second dielectric layer. The dielectric constant of the first dielectric layer and the second dielectric layer is less than the dielectric constant of the intermediate dielectric layer. The dielectric loss factor of the first dielectric layer and the second dielectric layer is less than the dielectric loss factor of the intermediate dielectric layer.

[0016] In some embodiments, the material of the first dielectric layer and the second dielectric layer is thermoplastic resin. The material of the intermediate dielectric layer is thermosetting resin.

[0017] In some embodiments, the third circuit substrate protrudes from the second circuit substrate.

[0018] The manufacturing method of the antenna package provided in the present application can form the antenna package by only one pressing, reducing the pressing process, saving costs, and reducing the risks brought by the pressing process, such as peeling or skewness of various parts of the antenna package; in addition, the manufacturing method of the present application does not require the use of temporary bonding materials, further simplifying the process and saving costs; furthermore, the present application integrates various components (including antenna layer, ground layer, circuit layer, chip, etc.) into the same antenna package, reducing the signal loss between various components in the antenna package. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic cross-sectional view of the first circuit substrate provided in an embodiment of the present application.

[0020] Figure 2 A cross-sectional schematic diagram of the feeder layer provided in an embodiment of the present application.

[0021] Figure 3 This is a schematic cross-sectional view of the second circuit substrate provided in an embodiment of the present application.

[0022] Figure 4 A cross-sectional schematic diagram of a first intermediate body provided in an embodiment of the present application, including a first circuit substrate, a feeder layer, and a second circuit substrate.

[0023] Figure 5 This is a cross-sectional schematic diagram of the second intermediate provided in an embodiment of the present application.

[0024] Figure 6 The pressing provided in the embodiment of the present application Figure 4 The first intermediate shown is Figure 5 A schematic cross-sectional view of the antenna package obtained from the second intermediate shown.

[0025] Description of main component symbols

[0026]

[0027]

[0028] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0029] In order to more clearly understand the above-mentioned objects, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. In the following description, many specific details are set forth to facilitate a full understanding of the present application. The embodiments described are only a part of the embodiments of the present application, rather than all of the embodiments.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] In the embodiments of the present application, for the purpose of facilitating the description but not limiting the present application, the term "connection" used in the patent application specification and claims of the present application is not limited to physical or mechanical connection, whether direct or indirect. "Up", "down", "above", "below", "left", "right", and the like are only used to indicate relative positional relationship, and when the absolute position of the described object is changed, the relative positional relationship is also changed accordingly.

[0032] Referring to Figures 1 to 6 , the present embodiment provides a manufacturing method of an antenna package 100, comprising the following steps:

[0033] Step S1: referring to Figures 1 to 4 , a first intermediate body 10 is provided, the first intermediate body 10 comprises a first circuit substrate 12, a feed line layer 14 and a second circuit substrate 16 which are stacked, and the second circuit substrate 16 is provided with a cavity 166 on the surface away from the feed line layer 14.

[0034] Referring to Figure 1 , the first circuit substrate 12 comprises an antenna layer 126, a first dielectric layer 122 and a first circuit layer 124. The first dielectric layer 122 and the first circuit layer 124 are stacked. At least part of the antenna layer 126 is located on the surface of the first dielectric layer 122 away from the feed line layer 14.

[0035] Referring to Figure 2 , the feed line layer 14 comprises an intermediate dielectric layer 142 and an intermediate circuit layer 144, the intermediate circuit layer 144 is located on the opposite surfaces of the intermediate dielectric layer 142 and is electrically connected by the conductive hole 143 penetrating through the intermediate dielectric layer 142. The intermediate circuit layer 144 is electrically connected with the first circuit layer 124.

[0036] Referring to Figure 3 , the second circuit substrate 16 comprises a second dielectric layer 162 and a second circuit layer 164 which are stacked, and the second circuit layer 164 is electrically connected with the intermediate circuit layer 144.

[0037] The cavity 166 penetrates at least a portion of the second dielectric layer 162. In this embodiment, the cavity 166 also penetrates at least a portion of the second circuit layer 164. The size of the cavity 166 can be set according to the volume and number of chips 24 to be subsequently accommodated.

[0038] The material of the first dielectric layer 122 and the second dielectric layer 162 is thermoplastic resin; the material of the intermediate dielectric layer 142 is thermosetting resin. k smaller than D of the intermediate dielectric layer 142 k , D of the first dielectric layer 122 and the second dielectric layer 162 f (Dielectric loss factor) is less than the D of the intermediate dielectric layer 142 f , which can reduce signal loss.

[0039] The modulus of the intermediate dielectric layer 142 after curing is greater than the modulus of the first dielectric layer 122 and the second dielectric layer 162 after curing. The intermediate dielectric layer 142 is cured before the subsequent lamination step, which can provide rigid support for the subsequent lamination process and ensure the flatness of the antenna package 100 obtained after the lamination process. In addition, the thickness of the intermediate dielectric layer 142 can be selected within a wide range. The thickness of the intermediate dielectric layer 142 can be adjusted according to the specific frequency band requirements of the antenna package 100, thereby reducing the number of stacked layers of the first circuit substrate 12 and reducing processing costs.

[0040] See also Figure 4 The first intermediate body 10 can be formed by sequentially stacking and laminating the first circuit substrate 12, the feeder layer 14, and the second circuit substrate 16. In some embodiments, the lamination of the first circuit substrate 12, the feeder layer 14, and the second circuit substrate 16 can also be performed simultaneously with the second intermediate body 20 to form the antenna package 100, i.e., the antenna package 100 is formed by a one-step lamination process.

[0041] Step S2: Please refer to Figure 5 , providing a second intermediate body 20 , the second intermediate body 20 includes a third circuit substrate 22 and a chip 24 , and the chip 24 is located on the surface of the third circuit substrate 22 .

[0042] The third circuit substrate 22 includes a stacked third dielectric layer 222 and a third circuit layer 224. The chip 24 is electrically connected to the third circuit substrate 22. The chip 24 protrudes from the surface of the third circuit substrate 22.

[0043] The material of the third dielectric layer 222 can be the same as that of the second dielectric layer 162 , for example, both can be thermoplastic resin.

[0044] The number of the chips 24 can be one or more. When the number of the chips 24 is more than one, the chips 24 are located on the same surface of the third circuit substrate 22.

[0045] In some embodiments, the second intermediate body 20 can be formed by the following steps:

[0046] Step S201: providing a third circuit substrate 22, the third circuit substrate 22 comprising a third dielectric layer 222 and a third circuit layer 224 which are stacked.

[0047] The number of the third dielectric layer 222 and the third circuit layer 224 is not limited. The third circuit substrate 22 is used for electrical connection with the first intermediate body 10 and external circuit. The length of the third circuit substrate 22 along the extension direction L2 (perpendicular to the stacking direction L1 of the third dielectric layer 222 and the third circuit layer 224) is greater than the length of the first intermediate body 10.

[0048] Step S202: electrically connecting a chip 24 on a surface of the third circuit substrate 22.

[0049] The chip 24 is electrically connected with the third circuit layer 224 through conductive paste 30. In the present embodiment, the conductive paste 30 penetrates through a layer of the third dielectric layer 222 on the surface of the third circuit substrate 22, thereby electrically connecting with the chip 24. The conductive paste 30 can be copper paste or tin paste.

[0050] Step S3: please refer to Figure 6 The chip 24 is arranged corresponding to the cavity 166, and the first intermediate body 10 and the second intermediate body 20 are pressed together to form the antenna package 100.

[0051] In some embodiments, the chip 24 is staggered with the regions with higher circuit density in the second circuit layer 164 and the third circuit layer 224, so as to prevent the chip 24 and the circuit layers (including the second circuit layer 164 and the third circuit layer 224) from being deviated during the pressing process. In addition, the intermediate circuit layer 144 and the third circuit layer 224 comprise a large-area copper layer 146, 2242 corresponding to the chip 24, wherein along the stacking direction L1, the area of the copper layer 146, 2242 is greater than the area of the chip 24. During the pressing process, the chip 24 is located within the projection area of the copper layer 146, 2242, so as to prevent the chip 24 and the circuit layers (including the second circuit layer 164 and the third circuit layer 224) from being deviated.

[0052] Please refer to Figure 6The application also provides an antenna package 100, comprising a first intermediate body 10 and a second intermediate body 20, the first intermediate body 10 and the second intermediate body 20 being stacked.

[0053] The first intermediate body 10 comprises a first circuit substrate 12, a feed line layer 14 and a second circuit substrate 16 which are stacked.

[0054] The first circuit substrate 12 comprises an antenna layer 126, a first dielectric layer 122 and a first circuit layer 124. The first dielectric layer 122 and the first circuit layer 124 are stacked. At least part of the antenna layer 126 is located on the surface of the first dielectric layer 122 away from the feed line layer 14.

[0055] In some embodiments, the antenna layer 126 comprises an excitation radiation patch 1262 and a main radiation patch 1264, the excitation radiation patch 1262 is located on the surface of the first dielectric layer 122 away from the feed line layer 14, the main radiation patch 1264 is embedded in the first dielectric layer 122, the main radiation patch 1264 is arranged away from the excitation radiation patch 1262, and the main radiation patch 1264 is electrically connected to the first circuit layer 124.

[0056] The feed line layer 14 comprises an intermediate dielectric layer 142 and an intermediate circuit layer 144 which is located on the opposite surfaces of the intermediate dielectric layer 142 and is electrically connected by a conductive hole 143 penetrating the intermediate dielectric layer 142. The intermediate circuit layer 144 is electrically connected to the first circuit layer 124. The intermediate circuit layer 144 comprises a ground layer 1442 which is located on the surface of the intermediate dielectric layer 142 away from the first circuit substrate 12.

[0057] In some embodiments, the distance between the main radiation patch 1264 and the excitation radiation patch 1262 can be 100-500 μm, and the distance between the excitation radiation patch 1262 and the ground layer 1442 can be 300-900 μm.

[0058] The second circuit substrate 16 comprises a second dielectric layer 162 and a second circuit layer 164 which are stacked, and the second circuit layer 164 is electrically connected to the intermediate circuit layer 144.

[0059] In some embodiments, the first circuit layer 124, the intermediate circuit layer 144 and the second circuit layer 164 are electrically connected by a conductive paste 30, and no other connector for electrical connection is needed, which can reduce signal loss. The conductive paste 30 can be copper paste or tin paste.

[0060] In some embodiments, the conductive paste 30 used to electrically connect the first circuit layer 124 and the intermediate circuit layer 144 is overlapped (i.e. in a manner of stacking holes) in the stacking direction L1, which can reduce the parasitic parameters of the first intermediate body 10.

[0061] The material of the first dielectric layer 122 and the second dielectric layer 162 is thermoplastic resin, and the material of the intermediate dielectric layer 142 is thermosetting resin. The D k is less than the D k of the intermediate dielectric layer 142, and the D f of the first dielectric layer 122 and the second dielectric layer 162 is less than the D f of the intermediate dielectric layer 142, which can reduce signal loss.

[0062] The modulus of the intermediate dielectric layer 142 after curing is greater than the modulus of the first dielectric layer 122 and the second dielectric layer 162 after curing. The intermediate dielectric layer 142 is cured before the subsequent lamination process, which can provide rigid support for the subsequent lamination process and ensure the flatness of the antenna package 100 after the lamination process. In addition, the thickness of the intermediate dielectric layer 142 has a wide selection range, which can be adjusted according to the needs of a specific frequency band of the antenna package 100, thereby reducing the number of layers of the first circuit substrate 12 and reducing the processing cost.

[0063] The second intermediate body 20 is adjacent to the second circuit substrate 16. The second intermediate body 20 includes a third circuit substrate 22 and a chip 24, and the chip 24 is located on the surface of the third circuit substrate 22 and embedded in the second circuit substrate 16.

[0064] The length of the third circuit substrate 22 in the extension direction L2 of the third circuit substrate 22 is greater than the length of the first intermediate body 10, i.e. the third circuit substrate 22 protrudes from the first intermediate body 10. The third circuit substrate 22 can be directly used for electrical connection with external circuits, without the need for additional connectors for electrical connection, which can reduce signal loss.

[0065] The third circuit layer 224 can be electrically connected to the chip 24 and the second circuit layer 164 through the conductive paste 30.

[0066] In some embodiments, the surface of the third circuit substrate 22 away from the first intermediate body 10 is the third dielectric layer 222, and the third dielectric layer 222 located at the outermost layer can serve as an insulating protective layer, which can reduce the step of forming other protective layers.

[0067] The manufacturing method of the antenna package 100 provided by the present application can form the antenna package 100 by only one pressing, reduce the pressing process, save the cost, and reduce the risk caused by the pressing process, such as the peeling or skewing of each part of the antenna package 100. In addition, the manufacturing method of the present application does not need to use a temporary bonding material, further simplifies the process, and saves the cost. Furthermore, the present application integrates each element (including the antenna layer 126, the ground layer 1442, the circuit layer, the chip 24, etc.) in the same antenna package 100, and reduces the signal loss between each element in the antenna package 100.

[0068] The above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the above preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for manufacturing an antenna package, characterized in that: The following steps are involved: A first intermediate body is provided, the first intermediate body comprising a first circuit substrate, a feeder layer, and a second circuit substrate arranged in a stacked manner, the first circuit substrate comprising an antenna layer and a first dielectric layer, the feeder layer comprising an intermediate dielectric layer and an intermediate circuit layer, the second circuit substrate comprising a second dielectric layer, the intermediate dielectric layer having a modulus after curing greater than that of the first dielectric layer and the second dielectric layer after curing, and a cavity being defined on a surface of the second circuit substrate facing away from the feeder layer; Providing a second intermediate body, the second intermediate body comprising a third circuit substrate and a chip, the chip being located on a surface of the third circuit substrate, and the third circuit substrate comprising a third circuit layer; as well as Arrange the chip corresponding to the cavity, and press the first intermediate body and the second intermediate body together to form the antenna package; The middle circuit layer and the third circuit layer both include copper layers, and the chip is located within a projection area of ​​the copper layers; the third circuit substrate covers the cavity and the second circuit substrate.

2. The method for manufacturing an antenna package according to claim 1, wherein: The step of forming the second intermediate comprises: Providing the third circuit substrate, the third circuit substrate comprising a third dielectric layer and the third circuit layer stacked together; and The chip is electrically connected to a surface of the third circuit substrate.

3. The method for manufacturing the antenna package according to claim 2, wherein: The surface of the third circuit substrate facing away from the first intermediate body is the third dielectric layer.

4. The method for manufacturing an antenna package according to claim 1, wherein: The first circuit substrate is electrically connected to the feeder layer via a conductive paste, and the conductive paste overlaps in a stacking direction of the first intermediate body.

5. An antenna package manufactured by the method for manufacturing an antenna package according to any one of claims 1 to 4, characterized in that: The antenna package comprises: A first circuit substrate, comprising an antenna layer and a first dielectric layer; A feeder layer is located on a surface of the first circuit substrate, and the feeder layer includes an intermediate dielectric layer and an intermediate circuit layer; a second circuit substrate, located on a surface of the feeder layer facing away from the first circuit substrate, the second circuit substrate comprising a second dielectric layer, the modulus of the intermediate dielectric layer being greater than the modulus of the first dielectric layer and the second dielectric layer; a third circuit substrate, located on a surface of the second circuit substrate away from the feeder layer and covering the second circuit substrate, the third circuit substrate including a third circuit layer; and A chip is embedded in the second circuit substrate and electrically connected to the third circuit substrate. The intermediate circuit layer and the third circuit layer both include copper layers, and the chip is located within a projected area of ​​the copper layers.

6. The antenna package according to claim 5, wherein: The first circuit substrate further includes a first circuit layer; the first dielectric layer and the first circuit layer are stacked, and at least a portion of the antenna layer is located on a surface of the first dielectric layer facing away from the feeder layer.

7. The antenna package according to claim 6, wherein: The antenna layer includes an excitation radiation patch and a main radiation patch. The excitation radiation patch is located on a surface of the first dielectric layer away from the feeder layer, and the main radiation patch is buried in the first dielectric layer.

8. The antenna package according to claim 5, wherein: The intermediate circuit layer is located on two opposite surfaces of the intermediate dielectric layer and is electrically connected through conductive holes penetrating the intermediate dielectric layer; the second circuit substrate further includes a stacked second dielectric layer and a second circuit layer, and the second circuit layer is electrically connected to the intermediate circuit layer.

9. The antenna package according to claim 5, wherein: The dielectric constants of the first dielectric layer and the second dielectric layer are smaller than the dielectric constant of the middle dielectric layer, and the dielectric loss factors of the first dielectric layer and the second dielectric layer are smaller than the dielectric loss factor of the middle dielectric layer.

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