Digital-to-analog converter with integrated 2:1 multiplexer

Abstract

The present application discloses an integrated 2:1 multiplexer digital-to-analog converter, comprising: a plurality of bit digital-to-analog conversion units and a differential signal input stage. Each digital-to-analog conversion unit includes: a current mirror, comprising first and second NMOS transistors, each with a gate coupled to a bias voltage and a source coupled to a first and second node, respectively; third to sixth NMOS transistors, wherein the drains of the third and fourth NMOS transistors are coupled to the first node, the drains of the fifth and sixth NMOS transistors are coupled to the second node, the gates of the third and fifth NMOS transistors are coupled to the first pair of differential signals, respectively, and the gates of the fourth and sixth NMOS transistors are coupled to the second pair of differential signals, respectively; and the differential signal input stage includes first to eighth NAND gates and first to fourth inverters. By adopting a four-phase clock, the present application addresses the clock speed requirements of conventional 2:1 multiplexers.

Description

Technical Field

[0001] The present invention generally relates to the technical field of integrated circuits, and more particularly to a digital-to-analog converter with an integrated 2:1 multiplexer. Background Art

[0002] In high-speed SerDes (SerDes) circuit applications based on DAC solutions, the performance of the final multiplexer directly impacts the DAC's output signal linearity and eye diagram quality. Current mainstream high-speed SerDes TX solutions based on DAC solutions typically adopt half-rate and quarter-rate architectures. The final multiplexer in the half-rate architecture is the 2:1 multiplexer. As SerDes application speeds continue to increase, the clock speed requirements of conventional 2:1 multiplexers have become difficult to meet, and conventional 2:1 multiplexers often face the impact of ISI (Inter-symbol interference) on their outputs. Here, we propose a new 2:1 multiplexer design to address these issues and effectively integrate it with the DAC. Summary of the Invention

[0003] The object of the present invention is to provide a digital-to-analog converter integrated with a 2:1 multiplexer, which adopts a 4-phase clock and solves the clock speed requirement of a traditional 2:1 multiplexer.

[0004] The present application discloses a digital-to-analog converter with an integrated 2:1 multiplexer, comprising:

[0005] Several bit digital-to-analog conversion units, each of which includes:

[0006] a current mirror comprising a first NMOS transistor and a second NMOS transistor, wherein gates of the first NMOS transistor and the second NMOS transistor are both coupled to a bias voltage, drains are both coupled to a voltage source, a source of the first NMOS transistor is coupled to a first node, and a source of the second NMOS transistor is coupled to a second node; and

[0007] third to sixth NMOS transistors, wherein the drains of the third and fourth NMOS transistors are coupled to the first node, the drains of the fifth and sixth NMOS transistors are coupled to the second node, the gates of the third and fifth NMOS transistors are respectively coupled to the first pair of differential signals, and the gates of the fourth and sixth NMOS transistors are respectively coupled to the second pair of differential signals;

[0008] A differential signal input stage includes first to eighth NAND gates and first to fourth inverters, wherein the output terminals of the first and second NAND gates are coupled to the input terminal of the first inverter through a first switch and a second switch, respectively, the output terminals of the fifth and sixth NAND gates are coupled to the input terminal of the third inverter through a fifth switch and a sixth switch, respectively, the output terminals of the first and third inverters respectively provide the first pair of differential signals, the output terminals of the third and fourth NAND gates are coupled to the input terminal of the third inverter through a third switch and a fourth switch, respectively, the output terminals of the seventh and eighth NAND gates are coupled to the input terminal of the fourth inverter through a seventh switch and an eighth switch, respectively, and the output terminals of the second and fourth inverters respectively provide the second pair of differential signals.

[0009] In a preferred embodiment, the first clock signal of the four clock signals with a phase difference of 90° is coupled to one input terminal of the fourth and eighth NAND gates, the second clock signal is coupled to one input terminal of the first and fifth NAND gates, the third clock signal is coupled to one input terminal of the third and seventh NAND gates, and the fourth clock signal is coupled to one input terminal of the second and sixth NAND gates; the rising edges of the four clock signals are sampled to obtain four pairs of differential clock sampling signals, the first pair of differential clock sampling signals is coupled to the other input terminal of the first and fifth NAND gates, the second pair of differential clock sampling signals is coupled to the other input terminal of the third and seventh NAND gates, the third pair of differential clock sampling signals is coupled to the other input terminal of the second and sixth NAND gates, and the fourth pair of differential clock sampling signals is coupled to the other input terminal of the fourth and eighth NAND gates; the first and fifth switches are controlled by the third clock signal, the second and sixth switches are controlled by the first clock signal, the third and seventh switches are controlled by the fourth clock signal, and the fourth and eighth switches are controlled by the second clock signal.

[0010] In a preferred example, the digital-to-analog converter further includes a first resistor and a second resistor, wherein the first resistor is connected in series between the drain of the first NMOS transistor of each digital-to-analog conversion unit and the power supply terminal, and the second resistor is connected in series between the drain of the second NMOS transistor of each digital-to-analog conversion unit and the power supply terminal.

[0011] In a preferred embodiment, the digital-to-analog converter is a tailless current-steering digital-to-analog converter.

[0012] In a preferred embodiment, the first pair of differential signals and the second pair of differential signals are return-to-zero codes.

[0013] In a preferred example, the digital-to-analog converter further includes: a bias voltage providing circuit, which includes: a current source, a seventh NMOS transistor and an eighth NMOS transistor, the drain and gate of the seventh NMOS transistor are connected to the current source and provide the bias voltage to the gates of the first NMOS transistor and the second NMOS transistor, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to the power supply terminal, and the source of the eighth NMOS transistor is connected to the ground terminal.

[0014] Compared with the prior art, this application has at least the following beneficial effects:

[0015] This paper proposes a novel tailless digital-to-analog converter (DAC) with two cascaded 2:1 multiplexers (MUX) structure.

[0016] First, the design of the 2:1 multiplexer disclosed herein is different from the traditional TX Half Rate structure and adopts a 4-phase clock, thereby solving the clock speed requirement of the traditional 2:1 multiplexer.

[0017] Second, the 2:1 multiplexer of the present disclosure outputs an RZ (Return to Zero) signal, which effectively avoids the influence of ISI.

[0018] Third, the disclosed 2:1 multiplexer can be effectively integrated with the switching transistors of a conventional tailless digital-to-analog converter to implement the ABABAB… operating principle in a ping-pong manner.

[0019] Fourth, traditionally, the final multiplexer and DAC stage are often accompanied by several stages of inverters (INVs). The integration of a 2:1 multiplexer and DAC eliminates these INVs, significantly increasing the bandwidth of the data signal link.

[0020] The specification of this application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too lengthy. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a circuit diagram of a digital-to-analog converter in one embodiment of the present application.

[0022] Figure 2 1 is a circuit diagram of a differential signal input stage in one embodiment of the present application.

[0023] Figure 3 It is a timing diagram of a digital-to-analog converter in one embodiment of the present application. DETAILED DESCRIPTION

[0024] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0025] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0026] The present application discloses a digital-to-analog converter with an integrated 2:1 multiplexer. The digital-to-analog converter includes: a plurality of bit digital-to-analog conversion units and a differential signal input stage. In one embodiment, the digital-to-analog converter DAC is a tailless current-steering digital-to-analog converter. Figure 1 A novel tailless digital-to-analog converter (DAC) having two cascaded 2:1 multiplexer (MUX) structures in one embodiment is disclosed.

[0027] Each digital-to-analog conversion unit includes a current mirror and third to sixth NMOS transistors. The current mirror includes a first NMOS transistor N1 and a second NMOS transistor N2. The gates of the first NMOS transistor N1 and the drains of the second NMOS transistor N2 are both coupled to a bias voltage VBS, and the drains are both coupled to a voltage source. The source of the first NMOS transistor N1 is coupled to a first node T1, and the source of the second NMOS transistor N2 is coupled to a second node T2.

[0028] In one embodiment, the digital-to-analog converter further includes a first resistor R1 and a second resistor R2, wherein the first resistor R1 is connected in series between the drain of the first NMOS transistor N1 of each digital-to-analog conversion unit and the power supply terminal, and the second resistor R2 is connected in series between the drain of the second NMOS transistor N2 of each digital-to-analog conversion unit and the power supply terminal.

[0029] The drains of the third NMOS transistor N3 and the fourth NMOS transistor N4 are coupled to the first node T1, the drains of the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are coupled to the second node T2, the gates of the third NMOS transistor N3 and the fifth NMOS transistor N5 are coupled to the first pair of differential signals A, Ab, respectively, and the gates of the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are coupled to the second pair of differential signals B, Bb, respectively.

[0030] The digital-to-analog converter further includes a bias voltage supply circuit, comprising a current source I, a seventh NMOS transistor N7, an eighth NMOS transistor N8, and a capacitor C. The drain and gate of the seventh NMOS transistor N7 are connected to the current source I and provide a bias voltage VBS to the gates of the first NMOS transistor N1 and the second NMOS transistor N2. The source of the seventh NMOS transistor N7 is connected to the drain of the eighth NMOS transistor N8, the gate of the eighth NMOS transistor N8 is connected to a power supply terminal, and the source of the eighth NMOS transistor N8 is connected to a ground terminal. The capacitor C is connected to the gates of the first NMOS transistor N1 and the second NMOS transistor N2.

[0031] Figure 2FIG2 is a schematic diagram of a differential signal input stage according to an embodiment. The differential signal input stage includes a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a sixth NAND gate NAND6, a seventh NAND gate NAND7, an eighth NAND gate NAND8, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV1. The output ends of the first NAND gate NAND1 and the second NAND gate NAND2 are coupled to the input end of the first inverter INV1 through the first switch S1 and the second switch S2, respectively. The output ends of the fifth NAND gate NAND5 and the sixth NAND gate NAND6 are coupled to the input end of the third inverter INV3 through the fifth switch S5 and the sixth switch S6, respectively. The output ends of the first inverter INV1 and the third inverter INV3 provide a first pair of differential signals A, Ab, respectively. The output ends of the third NAND gate NAND3 and the fourth NAND gate NAND4 are coupled to the input end of the third inverter INV3 through the third switch S3 and the fourth switch S4, respectively. The output ends of the seventh NAND gate NAND7 and the eighth NAND gate NAND8 are coupled to the input end of the fourth inverter INV4 through the seventh switch S7 and the eighth switch S8, respectively. The output ends of the second inverter INV2 and the fourth inverter INV4 provide a second pair of differential signals B, Bb, respectively.

[0032] In one embodiment, the first clock signal Q1 of the four clock signals Q1 / Q2 / Q3 / Q4, which are sequentially phase-shifted by 90°, is coupled to one input of the fourth NAND gate NAND4 and the eighth NAND gate NAND8. The second clock signal Q2 is coupled to one input of the first NAND gate NAND1 and the fifth NAND gate NAND5. The third clock signal Q3 is coupled to one input of the third NAND gate NAND3 and the seventh NAND gate NAND7. The fourth clock signal Q4 is coupled to one input of the second NAND gate NAND2 and the sixth NAND gate NAND6. The rising edges of the four clock signals Q1 / Q2 / Q3 / Q4 are sampled to obtain four pairs of differential clock sampling signals D1 / D2 / D3 / D4 / DB1 / DB2 / DB3 / DB4. The first pair of differential clock sampling signals D1 / DB1 is coupled to the other input terminal of the first NAND gate NAND1 and the fifth NAND gate NAND. The second pair of differential clock sampling signals D2 / DB2 is coupled to the other input terminal of the third NAND gate NAND3 and the seventh NAND gate NAND7. The third pair of differential clock sampling signals D3 / DB3 is coupled to the other input terminal of the second NAND gate NAND2 and the sixth NAND gate NAND6. The fourth pair of differential clock sampling signals D4 / DB4 is coupled to the other input terminal of the fourth NAND gate NAND4 and the eighth NAND gate NAND8. The first switch S1 and the fifth switch S5 are controlled by the third clock signal Q3, the second switch S2 and the sixth switch S6 are controlled by the first clock signal Q1, the third switch S3 and the seventh switch S7 are controlled by the fourth clock signal Q4, and the fourth switch S4 and the eighth switch S8 are controlled by the second clock signal Q2. By adopting a four-phase clock, this application solves the clock speed requirements of traditional 2:1 multiplexers.

[0033] The first pair of differential signals A, Ab and the second pair of differential signals B, Bb are return-to-zero (RZ) codes, which effectively avoid the influence of ISI.

[0034] Figure 3 The timing diagram of a digital-to-analog converter in one embodiment is shown. Assume that the rising edge of Q1 generates data D1, the rising edge of Q2 generates D2, and so on. Output data A multiplexes data D1 and D3. When Q1 = 0, Q2 = Q3 = 1 (high voltage), and Q4 = 0, A = D1; when Q1 = 0, Q2 = 0, Q3 = 1, and Q4 = 1, A = 0; when Q1 = 1, Q2 = 0, Q3 = 0, and Q4 = 1, A = D3; when Q1 = 1, Q2 = 1, Q3 = 0, and Q4 = 0, A = 0. The same applies to B's multiplexing of data D2 and D3.

[0035] The disclosed 2:1 multiplexer can be effectively integrated with the switching transistors of a conventional tailless digital-to-analog converter, achieving a ping-pong-style ABABAB… operating principle. Traditionally, the final multiplexer and digital-to-analog converter stage often involve several stages of inverters (INV). The integration of a 2:1 multiplexer and digital-to-analog converter eliminates these INV stages, significantly increasing the bandwidth of the data signal link.

[0036] It should be noted that in this patent application, relational terms such as first and second, etc., are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element specified by the phrase "comprising a" does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element. In this patent application, reference to performing an action in accordance with an element means performing the action in accordance with at least that element, including two situations: performing the action in accordance with that element alone, and performing the action in accordance with that element and other elements. Expressions such as "plurality," "multiple times," and "many" include "two," "twice," "two kinds," and "more than two," "more than two times," and "more than two kinds."

[0037] This specification includes combinations of the various embodiments described herein. Separate references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as such or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0038] All documents mentioned in this specification are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above description is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

Claims

1. A digital-to-analog converter with an integrated 2:1 multiplexer, characterized in that: include: Several bit digital-to-analog conversion units, each of which includes: a current mirror comprising a first NMOS transistor and a second NMOS transistor, wherein gates of the first NMOS transistor and the second NMOS transistor are both coupled to a bias voltage, drains are both coupled to a voltage source, a source of the first NMOS transistor is coupled to a first node, and a source of the second NMOS transistor is coupled to a second node; and third to sixth NMOS transistors, wherein the drains of the third and fourth NMOS transistors are coupled to the first node, the drains of the fifth and sixth NMOS transistors are coupled to the second node, the gates of the third and fifth NMOS transistors are respectively coupled to the first pair of differential signals, and the gates of the fourth and sixth NMOS transistors are respectively coupled to the second pair of differential signals; a differential signal input stage, the differential signal input stage comprising first to eighth NAND gates and first to fourth inverters, wherein the outputs of the first and second NAND gates are coupled to the input of the first inverter via a first switch and a second switch, respectively, the outputs of the fifth and sixth NAND gates are coupled to the input of the third inverter via a fifth switch and a sixth switch, respectively, the outputs of the first and third inverters respectively provide the first pair of differential signals, the outputs of the third and fourth NAND gates are coupled to the input of the second inverter via a third switch and a fourth switch, respectively, the outputs of the seventh and eighth NAND gates are coupled to the input of the fourth inverter via a seventh switch and an eighth switch, respectively, and the outputs of the second and fourth inverters respectively provide the second pair of differential signals; Among the four clock signals with phases differing by 90°, a first clock signal is coupled to one input terminal of the fourth and eighth NAND gates, a second clock signal is coupled to one input terminal of the first and fifth NAND gates, a third clock signal is coupled to one input terminal of the third and seventh NAND gates, and a fourth clock signal is coupled to one input terminal of the second and sixth NAND gates. Rising edges of the four clock signals are sampled to obtain four pairs of differential clock sampling signals. The first pair of differential clock sampling signals is coupled to the other input terminal of the first and fifth NAND gates, the second pair of differential clock sampling signals is coupled to the other input terminal of the third and seventh NAND gates, the third pair of differential clock sampling signals is coupled to the other input terminal of the second and sixth NAND gates, and the fourth pair of differential clock sampling signals is coupled to the other input terminal of the fourth and eighth NAND gates. The first and fifth switches are controlled by the third clock signal, the second and sixth switches are controlled by the first clock signal, the third and seventh switches are controlled by the fourth clock signal, and the fourth and eighth switches are controlled by the second clock signal.

2. The digital-to-analog converter with an integrated 2:1 multiplexer according to claim 1, wherein: The digital-to-analog converter also includes a first resistor and a second resistor, the first resistor is connected in series between the drain of the first NMOS transistor of each digital-to-analog conversion unit and the power supply terminal, and the second resistor is connected in series between the drain of the second NMOS transistor of each digital-to-analog conversion unit and the power supply terminal.

3. The digital-to-analog converter with an integrated 2:1 multiplexer according to claim 1, wherein: The digital-to-analog converter is a tailless current-steering digital-to-analog converter.

4. The digital-to-analog converter with an integrated 2:1 multiplexer according to claim 1, wherein: The first pair of differential signals and the second pair of differential signals are return-to-zero codes.

5. The digital-to-analog converter with an integrated 2:1 multiplexer according to claim 1, wherein: Also includes: A bias voltage providing circuit includes: a current source, a seventh NMOS transistor, and an eighth NMOS transistor, wherein the drain and gate of the seventh NMOS transistor are connected to the current source and provide the bias voltage to the gates of the first and second NMOS transistors, the source of the seventh NMOS transistor is connected to the drain of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to a power supply terminal, and the source of the eighth NMOS transistor is connected to a ground terminal.

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