Accelerometer based on silicon nanowire array and preparation method thereof

Abstract

The application relates to a silicon nanowire array-based accelerometer and a preparation method thereof. The silicon nanowire array-based accelerometer comprises a silicon nanowire sensitive unit, a silicon nitride film, a mass block, a gold electrode and a silicon substrate. A plurality of silicon nanowires are arranged in parallel between two electrodes, and the device as a whole presents a comb-tooth shape. When the silicon nanowire array-based accelerometer works, the signals on the plurality of silicon nanowires are superimposed on each other, so that the output signal is stronger and more stable. The application adopts single-crystal silicon nanowires to replace traditional piezoresistors as the sensitive unit, and the piezoresistance coefficient of the silicon nanowires is higher than that of the piezoresistors, so that the accelerometer has higher sensitivity. In addition, the preparation process is simple, the cost is low, and large-scale production can be realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of MEMS sensors, and particularly relates to a silicon nanowire array-based accelerometer and a preparation method thereof. BACKGROUND

[0002] Micro-electrical mechanical system (MEMS) is also called micro-electronic mechanical system or micro system, and is a micro system integrating micro structures, micro sensors, micro actuators, control processing circuits and the like by using micro mechanical processing technology and integrated circuit manufacturing technology. The micro-electrical mechanical system has the advantages of miniaturization, integration, cost reduction, high performance and mass production, and is widely applied to the fields of automobile electronics, consumer electronics, aerospace and geological exploration.

[0003] The silicon nanowire is a very small conductive channel, and a slight external force can cause the silicon nanowire to deform, thereby changing the conductance of the silicon nanowire. Therefore, the accelerometer prepared by using the silicon nanowire has high sensitivity.

[0004] However, the current signal generated by the silicon nanowire device is mostly in the nano-ampere level, and effective acquisition of the signal is a big problem. SUMMARY

[0005] The application aims to solve the above problems, and provides a silicon nanowire array-based accelerometer and a preparation method thereof. A plurality of silicon nanowires are connected in parallel between two electrodes, and the signals on the plurality of silicon nanowires are superimposed on each other, so that the output signal is stronger and more stable.

[0006] In order to achieve the above purpose, the application adopts the following technical scheme:

[0007] A preparation method of a silicon nanowire array-based accelerometer, characterized by comprising the following steps:

[0008] S1, a silicon nitride film is prepared on the top surface of an SOI silicon wafer to form a dielectric mask layer;

[0009] S2, a small triangle array pattern is transferred on the dielectric mask layer, and the silicon nitride at the triangle is etched to form a small triangle array window; then, dry etching is performed on the top layer of silicon at the small triangle array window to obtain vertical small triangle grooves with the same depth, so as to form a small triangle array groove, and then the photoresist is removed;

[0010] S3, the small triangle array groove is oxidized based on a self-limiting thermal oxidation process;

[0011] S4, transfer a large triangle array pattern on the medium mask layer, etch the silicon nitride at the triangle to form a large triangle array window; then dry etch the top layer of silicon at the large triangle array window to obtain vertical large triangle grooves with the same depth, to form a large triangle array groove, and then remove the photoresist;

[0012] The small triangle array groove and the large triangle array groove form an array structure with a vertical small triangle groove in the middle of the area surrounded by three vertical large triangle grooves as an array unit.

[0013] S5, perform anisotropic wet etching on each vertical large triangle groove of the large triangle array groove to form a hexagonal etching groove array; wherein a single crystal silicon thin wall structure is formed between two adjacent hexagonal etching grooves; a relative cone structure, i.e. a mass block, appears in the middle of the three hexagonal etching grooves of the same array unit.

[0014] S6, after the silicon wafer is oxidized based on a self-limiting thermal oxidation process, a single crystal silicon nanowire is formed at the top central position of all single crystal silicon thin wall structures.

[0015] S7, etch the silicon nitride at a proper position of the silicon wafer to form a square window, perform boron ion implantation on the square window and then perform annealing, and then make positive and negative electrodes.

[0016] S8, make an isolation trench at a proper position of the silicon wafer to physically isolate the positive and negative electrodes.

[0017] S9, remove the oxidized single crystal silicon thin wall structure to release the entire structure.

[0018] As a preferred solution, the three vertical large triangle grooves in the array unit are distributed with two in the same row and the remaining one in another row.

[0019] As a preferred solution, two vertical large triangle grooves are shared by adjacent array units, and the four vertical large triangle grooves are distributed with two in the same row and the other two in another row.

[0020] As a preferred solution, the silicon nitride thin film is made by using a low-stress CVD thin film growth technology.

[0021] As a preferred solution, the small triangle window is replaced by a circular or square window.

[0022] As a preferred solution, the wet etching solution is a 10-100℃, 10-80wt% KOH solution, and the wet etching time is 5 minutes-10 hours.

[0023] As a preferred solution, the preset width of the single crystal silicon thin wall structure is less than 1μm.

[0024] Preferably, the single-crystal silicon nanowire has a width of 10-800 nm.

[0025] Preferably, the ion implantation process parameters include an ion implantation energy of 5-100 KeV, an ion implantation dose of 0.1E15 cm -2 -10E15 cm -2 , an annealing temperature of 200-4000℃, and an annealing time of 5 minutes-10 hours.

[0026] The application also provides a silicon nanowire array-based accelerometer prepared by the preparation method.

[0027] Compared with the prior art, the application has the following advantages:

[0028] The application arranges a plurality of silicon nanowires in parallel between two electrodes, and the device as a whole has a comb-tooth shape. When the silicon nanowire array accelerometer is in operation, the signals on the plurality of silicon nanowires are superimposed on each other, so that the output signal is stronger and more stable.

[0029] The core structure of the silicon nanowire array-based accelerometer of the application is composed of a plurality of mass blocks supported by a silicon nitride film and a plurality of silicon nanowires. The application not only realizes the innovation of the device structure, but also solves the problem that the current silicon nanowire structure device lacks protection measures for the silicon nanowires and the silicon nanowires are prone to breakage, so that the device lacks long-term stability. In addition, the application ingeniously retains the silicon nitride film, so that the silicon nitride film can protect the silicon nanowires and prevent the silicon nanowires from breaking due to various reasons, thereby greatly improving the yield of the device.

[0030] The silicon nanowire accelerometer of the application can still work normally under the condition of a large acceleration value due to the special design of the silicon nanowire and mass block structure, and can realize the preparation of an ultra-large range accelerometer.

[0031] The application uses single-crystal silicon nanowires to replace traditional piezoresistors as a sensitive unit. Since the piezoresistance coefficient of the silicon nanowires is higher than that of the piezoresistors, the accelerometer of the application has higher sensitivity. In addition, the preparation process of the application is simple, the cost is low, and large-scale production can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1A is a schematic diagram of manufacturing a silicon nitride film on a top layer of silicon;

[0033] Figure 1B is a schematic diagram of manufacturing large and small triangular etching grooves on a silicon wafer;

[0034] Figure 1C is a schematic diagram of forming an inclined hexagonal etching groove by wet etching a large triangular array groove;

[0035] Figure 1D is a schematic diagram of silicon nanowire formed by silicon nano thin wall thermal oxidation;

[0036] Figure 1E is a side view schematic diagram of the silicon nanowire supporting mass block after releasing the whole structure;

[0037] Figure 1F is a schematic diagram of a silicon nanowire array accelerometer based on example one;

[0038] Figure 2 is a schematic diagram of a silicon nanowire array accelerometer based on example two;

[0039] Figure 3 is a schematic diagram of a silicon nanowire array accelerometer based on example three;

[0040] Figure 4A 、 Figure 4B 、 Figure 5 and Figure 6 are photos after wet etching of large triangle grooves. DETAILED DESCRIPTION

[0041] In order to more clearly illustrate the embodiments of the present application, the specific embodiments of the present application will be described below with reference to the drawings. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings and other embodiments can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0042] The silicon nanowire array based accelerometer of the present application comprises silicon nanowires, silicon nitride film, mass blocks, gold electrodes, isolation trenches and SOI silicon substrate.

[0043] The core structure of the silicon nanowire array based accelerometer of the present application is composed of multiple mass blocks supported by silicon nitride film and multiple silicon nanowires.

[0044] When the accelerometer is subjected to external acceleration, the mass blocks will move up and down to produce displacement, and the movement of the mass blocks will cause the silicon nanowires to deform, which will change the electrical conductivity of the silicon nanowires, and further cause the change of the signal, and the signal is output through the gold electrodes.

[0045] The preparation method of the silicon nanowire array based accelerometer of the present application comprises the following steps:

[0046] S1. Select a (111) type SOI silicon wafer, prepare a layer of silicon nitride film on the top surface of the silicon, form a dense dielectric mask layer, transfer multiple small triangle patterns by photolithography process, and perform RIE process at the same time to etch the silicon nitride at the small triangle pattern to form a small triangle array window.

[0047] S2. Dry etching the silicon at the small triangle array window of step S1 to produce a plurality of vertical triangle grooves with uniform depth, forming a small triangle array groove, and then removing the photoresist.

[0048] S3. Oxidizing the small triangle array groove of step S2 based on a self-limiting thermal oxidation process.

[0049] S4. Forming a large triangle array window in the dielectric mask layer generated in step S1 again through a photolithography process.

[0050] S5. Dry etching the silicon at the large triangle array window of step S4 until the oxide layer of the SOI silicon wafer, to produce a vertical triangle array groove with uniform depth.

[0051] S6. Removing the photoresist, and then performing an anisotropic wet etching on the large triangle array groove in step S5 to form a hexagonal array etching groove with each sidewall belonging to the {111} crystal plane family, a single-crystal silicon thin wall structure between two adjacent hexagonal etching grooves, and a relative cone-like structure between every three adjacent hexagonal etching grooves.

[0052] S7. After oxidizing the silicon wafer based on a self-limiting thermal oxidation process, a single-crystal silicon nanowire is formed at the top central position of all single-crystal silicon nanowall.

[0053] S8. Etching silicon nitride at a proper position of the chip to form a square window, implanting boron ions into the square window and then performing annealing, and then making a gold electrode in the region.

[0054] S9. Making an isolation trench at a proper position of the silicon wafer to realize physical isolation of the positive and negative electrodes of the device.

[0055] S10. Removing the single-crystal silicon nanowall oxidized in step S7 with BOE (buffer oxide etching solution) to release the entire structure.

[0056] In step S1, the silicon nitride thin film is prepared by a low-stress CVD thin film growth technology, and the thickness of the silicon nitride thin film is 50 nm-5 μm.

[0057] In step S1, the side length of the small triangle window is 1-50 μm, and the window can also be a pattern such as a circle, a square, etc.

[0058] In step S2, the vertical small triangle groove has a depth of 1-100 μm.

[0059] In step S3, the oxidation depth is 100 nm-20 μm.

[0060] The large triangle array in step S4 is composed of two basic units, the first basic unit is one triangle on top and two triangles on bottom; the second basic unit is two triangles on top and one triangle on bottom. The two basic units are arranged in sequence, and 1-1000 such arrangements form the large triangle array. It should also be pointed out that the large triangle array can also be composed of any one of the basic units alone.

[0061] The depth of the vertical large triangle array groove in step S5 is consistent and is 1-100 μm.

[0062] The solution for wet etching in step S6 is a 10-100 ℃, 10-80 wt% KOH solution, and the wet etching time is 5 minutes-10 hours.

[0063] The preset width of the single crystal silicon thin wall structure formed in step S6 is less than 1 μm.

[0064] The width of the single crystal silicon nanowire formed in step S7 is 10-800 nm.

[0065] The ion implantation process in step S8 has an ion implantation energy of 5-100 KeV, an ion implantation dose of 0.1E15 cm -2 -10E15 cm -2 , an annealing temperature of 200-4000 ℃, and an annealing time of 5 minutes-10 hours.

[0066] The isolation trench in step S9 is made by etching the silicon wafer to the bottom layer of silicon.

[0067] The single crystal silicon nanowire released in step S10 has a special protective structure of the silicon nitride film generated in step S1.

[0068] The above scheme is described in detail by listing three specific embodiments as follows:

[0069] Embodiment 1:

[0070] The preparation method of the accelerometer based on the silicon nanowire array of the embodiment includes the following steps:

[0071] 1. First, select a bottom layer of silicon as a (111) type SOI silicon wafer, and prepare a 50 nm-5 μm thick silicon nitride film 1 on the top surface of the silicon wafer 2 using a low-stress CVD thin film growth technology to form a dense dielectric mask layer, such as Figure 1AThe small triangle pattern array 14 is transferred by a photoetching process, and the small triangle pattern array 14 is subjected to a RIE process to etch the silicon nitride at the pattern to form a small triangle array window, the side length of the single triangle window is 1-50 μm, the silicon at the small triangle array window is subjected to dry etching to prepare vertical triangle array grooves with a uniform depth of 1-100 μm. The photoresist is removed, and the vertical triangle array grooves are oxidized by 100 nm-20 μm based on a self-limiting thermal oxidation process. As shown in Figure 1B .

[0072] 2. A large triangle array window 5 is formed in the silicon nitride layer 1 by a photoetching process, the large triangle array is composed of two basic units, the first basic unit is one triangle above and two triangles below; the second basic unit is two triangles below and one triangle above, and the two basic units are placed in turn to form the large triangle array in the present example. The large triangle array 5 window is subjected to dry etching to uniformly etch the silicon oxide layer 3 of the silicon wafer to prepare vertical large triangle grooves with a uniform depth of 1-100 μm, and the photoresist is removed. As shown in Figure 1B , Figure 4A and Figure 4B .

[0073] 3. The silicon wafer is subjected to anisotropic wet etching in a 10-100 ℃, 10-80 wt% KOH solution for 5 minutes-10 hours, and the large triangle array 5 groove in step 2 is etched into a hexagonal etching groove 6 with each side wall belonging to the {111} crystal plane family, a single crystal silicon thin wall structure 7 with a preset width of less than 1 μm is formed between two adjacent hexagonal etching grooves 6, and two opposite cone-like structures appear in the middle of every three adjacent etching grooves, and the upper cone-like structure is a mass 9 of a silicon nanowire array accelerometer (wherein the suspension of the mass requires two processes, one is the small triangle breaking, and the other is the subsequent BOE removal of the oxidized single crystal silicon thin wall structure to completely break and achieve the suspension of the mass), as shown in Figure 1C and Figure 1E .

[0074] 4. After the silicon wafer is oxidized based on a self-limiting thermal oxidation process, a single crystal silicon nanowire 8 is formed at the top center of all single crystal silicon nanowall 7. As shown in Figure 1D .

[0075] 5. Square windows are etched in the silicon nitride layer 1 at the upper left corner and the lower right corner of the chip, boron ions are implanted in the square windows and then annealed, the ion implantation energy is 5-100 KeV, the ion implantation dose is 0.1E15 cm -2 -10E15 cm -2, the annealing temperature is 200-4000C, the annealing time is 5 minutes-10 hours, and then gold electrode 12 is made in the region. The silicon wafer is etched to the oxide layer at appropriate positions of the silicon wafer to make device isolation channel 11, so as to realize physical isolation of the positive and negative electrodes of the device. As shown in Figure 1F .

[0076] 6. The oxidized single crystal silicon nanowall in step 3 is removed by BOE (buffer oxide etching solution) to release the whole structure.

[0077] Example 2:

[0078] The difference between the preparation method of this example and that of example 1 is that:

[0079] The preparation process is basically the same, but the device structure is slightly different, as shown in Figure 2 and Figure 5 . The triangular array formed in step 2 is different from that of example 1. The triangular array of this example is taken as one basic unit with one triangle on top and two triangles on bottom, and the triangular array of this example is composed of several such basic units; in addition, the isolation channel is made between the basic units and inside the basic units, and the isolation channel is made between the right lower corner triangle and the left lower corner triangle of every two adjacent basic units, and the isolation channel is made between the upper triangle and the right lower triangle inside every basic unit;

[0080] Other aspects can refer to example 1.

[0081] Example 3:

[0082] The difference between the preparation method of this example and that of example 1 is that:

[0083] The preparation process is basically the same, but the device structure is different, as shown in Figure 3 and Figure 6 . The triangular array formed in step 2 is different from that of example 1. The triangular array of this example is taken as one basic unit with two triangles on top and one triangle on bottom, and the triangular array of this example is composed of several such basic units; in addition, the isolation channel is made between the basic units and inside the basic units, and the isolation channel is made between the right upper corner triangle and the left upper corner triangle of every two adjacent basic units, and the isolation channel is made between the lower triangle and the right upper triangle inside every basic unit;

[0084] Other aspects can refer to example 1.

[0085] The above merely describes the preferred embodiments and principles of the present application in detail, and for those skilled in the art, according to the ideas provided by the present application, there will be changes in the specific implementation manner, and these changes should also be considered as the protection scope of the present application.

Claims

1. A method for fabricating a silicon nanowire array based accelerometer, comprising: The method comprises the following steps: S1, preparing a silicon nitride film on the top layer of an SOI silicon wafer to form a dielectric mask layer; S2, transferring a small triangle array pattern to the dielectric mask layer and etching the silicon nitride at the triangle to form a small triangle array window; then performing dry etching on the top layer of silicon at the small triangle array window to form vertical small triangle grooves with the same depth to form a small triangle array groove, and then removing the photoresist; S3, oxidizing the small triangle array groove based on a self-limiting thermal oxidation process; S4, transferring a large triangle array pattern to the dielectric mask layer and etching the silicon nitride at the triangle to form a large triangle array window; then performing dry etching on the top layer of silicon at the large triangle array window to form vertical large triangle grooves with the same depth to form a large triangle array groove, and then removing the photoresist; The small triangle array groove and the large triangle array groove form an array structure in which the middle of the area surrounded by three vertical large triangle grooves has a vertical small triangle groove as an array unit; S5, performing anisotropic wet etching on each vertical large triangle groove of the large triangle array groove to form a hexagonal etching groove array; wherein a single crystal silicon thin wall structure is formed between two adjacent hexagonal etching grooves; a relative cone structure, i.e. a mass block, appears in the middle of the three hexagonal etching grooves of the same array unit; S6, after the silicon wafer is oxidized based on the self-limiting thermal oxidation process, a single crystal silicon nanowire is formed at the top central position of all single crystal silicon thin wall structures; S7, etching silicon nitride at a proper position of the silicon wafer to form a square window, performing boron ion implantation on the square window and then performing annealing, and then manufacturing positive and negative electrodes; S8, manufacturing an isolation channel at a proper position of the silicon wafer to realize physical isolation of the positive and negative electrodes; S9, removing the oxidized single crystal silicon thin wall structure to release the whole structure; The core structure of the accelerometer is composed of a silicon nitride film and a plurality of mass blocks supported by a plurality of silicon nanowires, and the whole structure presents a comb-tooth type. When the accelerometer is subjected to external acceleration, the mass blocks will move up and down to produce displacement, the movement of the mass blocks will cause the silicon nanowires to deform, the deformation will change the electrical conductivity of the silicon nanowires, and then cause the signal to change.

2. The production method according to claim 1, wherein The distribution of the three vertical large triangle grooves in the array unit is that two are located in the same row and the remaining one is located in another row.

3. The production method according to claim 1, wherein The adjacent array units share two vertical large triangle grooves, and the distribution of the four vertical large triangle grooves is that two are located in the same row and the other two are located in another row.

4. The production method according to claim 1, wherein The silicon nitride film is prepared by a low-stress CVD thin film growth technology.

5. The production method according to claim 1, wherein The solution for wet etching is a 10-100℃, 10-80wt% KOH solution, and the wet etching time is 5 minutes-10 hours.

6. The production method according to claim 1, wherein The preset width of the single crystal silicon thin wall structure is less than 1μm.

7. The production method according to claim 1, wherein The width of the single crystal silicon nanowire is 10-800nm.

8. The production method according to claim 1, wherein The process parameters of the ion implantation include ion implantation energy of 5-100 KeV, ion implantation dose of 0.1E15 cm -2 -10E15 cm -2 .

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