A method, apparatus and storage medium for testing a circuit

Abstract

The present disclosure provides a test method, device and storage medium of a circuit. The test method comprises: performing simulation test on a to-be-tested circuit in a first preset stage, obtaining a first test voltage of a first network corresponding to a first power bus of each circuit module in the to-be-tested circuit and a second test voltage of a second network corresponding to a second power bus of each circuit module in the to-be-tested circuit; determining a first voltage drop according to the first test voltage and a first preset voltage, wherein the first preset voltage comprises a preset voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit in the first preset stage; determining a second voltage drop according to the second test voltage and a second preset voltage, wherein the second preset voltage comprises a preset voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit in the first preset stage; and determining a state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a test method, device and storage medium of a circuit. BACKGROUND

[0002] In the process of chip design, the power bus in the circuit of the designed chip needs to be evaluated, for example, the voltage drop of the power bus under the maximum current consumption state of the circuit is evaluated to determine whether the voltage drop meets the preset voltage drop, whether the circuit can work normally under the maximum current consumption state, and further determine the state of the chip design. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0004] The present disclosure provides a test method, device and storage medium of a circuit.

[0005] The first aspect of the present disclosure provides a test method of a circuit, the test method comprising:

[0006] performing simulation testing on the to-be-tested circuit in a first preset phase, and obtaining a first test voltage of a first network corresponding to a first power bus of each circuit module in the to-be-tested circuit and a second test voltage of a second network corresponding to a second power bus of each circuit module in the to-be-tested circuit;

[0007] determining a first voltage drop according to the first test voltage and a first preset voltage, wherein the first preset voltage comprises a preset voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit in the first preset phase;

[0008] determining a second voltage drop according to the second test voltage and a second preset voltage, wherein the second preset voltage comprises a preset voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit in the first preset phase;

[0009] determining the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop.

[0010] According to some exemplary embodiments of the present disclosure, determining the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop comprises:

[0011] determining the state of the to-be-tested circuit according to whether the first voltage drop meets a first preset voltage drop and / or whether the second voltage drop meets a second preset voltage drop.

[0012] According to some example embodiments of the present disclosure, the test method further comprises:

[0013] The first preset voltage drop is determined according to a third voltage drop determined by performing a simulation test on the to-be-tested circuit in a second preset stage; the third voltage drop comprises a voltage drop of a first network corresponding to the first power bus in the second preset stage;

[0014] The second preset voltage drop is determined according to a fourth voltage drop determined by performing a simulation test on the to-be-tested circuit in a second preset stage; the fourth voltage drop comprises a voltage drop of a second network corresponding to the second power bus in the second preset stage.

[0015] According to some example embodiments of the present disclosure, the first preset stage comprises a stage before the first power bus and the second power bus are integrated; and the second preset stage comprises a stage after the first power bus and the second power bus are integrated.

[0016] According to some example embodiments of the present disclosure, the simulation test comprises:

[0017] The preset test operation comprises a single test operation or a plurality of continuous single test operations within a preset time length.

[0018] According to some example embodiments of the present disclosure, the first voltage drop comprises an average voltage difference and / or a peak voltage difference of a first network corresponding to the first power bus of the to-be-tested circuit in a first preset stage under the preset test operation;

[0019] The second voltage drop comprises an average voltage difference and / or a peak voltage difference of a second network corresponding to the second power bus of the to-be-tested circuit in a first preset stage under the preset test operation;

[0020] The third voltage drop comprises an average voltage difference and / or a peak voltage difference of a first network corresponding to the first power bus of the to-be-tested circuit in a second preset stage under the preset test operation;

[0021] The fourth voltage drop comprises an average voltage difference and / or a peak voltage difference of a second network corresponding to the second power bus of the to-be-tested circuit in a second preset stage under the preset test operation.

[0022] According to some example embodiments of the present disclosure, the test method further comprises:

[0023] obtaining a first connection relationship table and a second connection relationship table of the to-be-tested circuit in the first preset stage, the first connection relationship table representing a connection relationship between a first power bus in the to-be-tested circuit and each circuit module in the to-be-tested circuit in the first preset stage, and recording a first preset voltage of a first network of the circuit module corresponding to the first power bus; the second connection relationship table representing a connection relationship between a second power bus in the to-be-tested circuit and the circuit module in the first preset stage, and recording a second preset voltage of a second network of the circuit module corresponding to the second power bus.

[0024] According to some example embodiments of the present disclosure, the test method further comprises:

[0025] performing simulation testing on the to-be-tested circuit in the second preset stage, obtaining a third test voltage of a first network of each circuit module in the to-be-tested circuit corresponding to the first power bus, and a fourth test voltage of a second network of each circuit module in the to-be-tested circuit corresponding to the second power bus;

[0026] determining a third voltage drop according to the third test voltage and a third preset voltage, wherein the third preset voltage comprises a preset voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus in the second preset stage;

[0027] determining a fourth voltage drop according to the fourth test voltage and a fourth preset voltage, wherein the fourth preset voltage comprises a preset voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus in the second preset stage.

[0028] According to some example embodiments of the present disclosure, the first power bus comprises a power bus of the to-be-tested circuit, and the second power bus comprises a ground bus of the to-be-tested circuit.

[0029] According to some example embodiments of the present disclosure, the test method further comprises:

[0030] determining a state of a driving time delay of the circuit module according to the first voltage drop and / or the second voltage drop under a plurality of preset test operations.

[0031] A second aspect of the present disclosure provides a test device for a circuit, the test device comprising:

[0032] The acquisition module is configured to perform simulation test on the to-be-tested circuit in the first preset stage, and acquire a first test voltage of a first network corresponding to the first power bus of each circuit module in the to-be-tested circuit and a second test voltage of a second network corresponding to the second power bus of each circuit module in the to-be-tested circuit.

[0033] The first determination module is configured to determine a first voltage drop according to the first test voltage and a first preset voltage, and determine a second voltage drop according to the second test voltage and a second preset voltage, wherein the first preset voltage includes a preset voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit in the first preset stage, and the second preset voltage includes a preset voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit in the first preset stage.

[0034] The second determination module is configured to determine the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop.

[0035] The third aspect of the present disclosure provides a test device of a circuit, the test device comprising:

[0036] a processor;

[0037] a memory for storing processor-executable instructions;

[0038] The processor is configured to perform the test method provided by the exemplary embodiments of the present disclosure.

[0039] The fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by the processor of the device, the device can perform the test method provided by the exemplary embodiments of the present disclosure.

[0040] The test method of the circuit provided by the embodiments of the present disclosure can perform simulation test on the to-be-tested circuit in the first preset stage, acquire a first test voltage of a first network corresponding to the first power bus of each circuit module in the to-be-tested circuit and a second test voltage of a second network corresponding to the second power bus of each circuit module in the to-be-tested circuit, determine a first voltage drop according to the first test voltage and a first preset voltage, determine a second voltage drop according to the second test voltage and a second preset voltage, and finally determine the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop. Based on the state of the to-be-tested circuit determined by the above test process, voltage drop analysis of the circuit of the chip in the first stage can be realized, and the test method of the circuit can efficiently and accurately evaluate the quality of the circuit of the chip.

[0041] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings, like reference numerals are used to represent like elements throughout. The accompanying drawings are of some embodiments of the present disclosure, and not all embodiments of the present disclosure. Other embodiments of the present disclosure, upon which modifications can be made, will be apparent to persons skilled in the art from the drawings, described below.

[0043] Figure 1 is a flow chart of a test method of a circuit according to an exemplary embodiment;

[0044] Figure 2 is a flow chart of a determination method of a first preset voltage drop and a second preset voltage drop according to an exemplary embodiment;

[0045] Figure 3 is a flow chart of a determination method of a first preset voltage drop and a second preset voltage drop according to an exemplary embodiment;

[0046] Figure 4 is a flow chart of a determination method of a third voltage drop and a fourth voltage drop according to an exemplary embodiment;

[0047] Figure 5 is a structural schematic diagram of a test device of a circuit according to an exemplary embodiment;

[0048] Figure 6 is a structural schematic diagram of a test device of a circuit according to an exemplary embodiment. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without creative work fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0050] In the related art, since the chip is affected by objective factors such as power bus during operation, some defect problems are generated, and therefore the influence caused by the power bus of the chip needs to be tested and analyzed.

[0051] Based on this, the embodiment of the present disclosure provides a test method of a circuit, which can efficiently and accurately test the circuit, determine the state of the to-be-tested circuit, and thus analyze the to-be-tested circuit and determine whether the to-be-tested circuit is qualified. If the determination result is unqualified, the analysis of the state of the to-be-tested circuit can be based on this to provide corresponding data support for the optimization of the circuit of the chip.

[0052] An example embodiment of the present disclosure provides a test method of a circuit, as shown in Figure 1 Figure 1 is a flowchart of a test method of a circuit according to an example embodiment. The test method of the circuit includes:

[0053] Step S101, performing simulation testing on the to-be-tested circuit in the first preset stage to obtain a first test voltage of a first network corresponding to a first power bus in each circuit module of the to-be-tested circuit and a second test voltage of a second network corresponding to a second power bus in each circuit module of the to-be-tested circuit;

[0054] Step S102, determining a first voltage drop according to the first test voltage and a first preset voltage; wherein the first preset voltage includes a preset voltage of the first network corresponding to the first power bus in each circuit module of the to-be-tested circuit in the first preset stage;

[0055] Step S103, determining a second voltage drop according to the second test voltage and a second preset voltage; wherein the second preset voltage includes a preset voltage of the second network corresponding to the second power bus in each circuit module of the to-be-tested circuit in the first preset stage;

[0056] Step S104, determining the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop.

[0057] In the example embodiment, the state of the to-be-tested circuit is determined by the first voltage drop and / or the second voltage drop through the obtained first voltage drop and second voltage drop corresponding to the first power bus and the second power bus in the first preset stage, and then whether the to-be-tested circuit is qualified is determined.

[0058] When the corresponding test voltage is obtained, the test method of the circuit is that: for the to-be-tested circuit in the first preset stage in the process of running the chip, simulation testing is performed, and the first test voltage in the first network corresponding to the first power bus in each circuit module of the to-be-tested circuit and the second test voltage of the second network corresponding to the second power bus in each circuit module of the to-be-tested circuit are obtained.

[0059] ​In the process of comparing the test voltage with the corresponding preset voltage to determine the voltage drop information of the power bus, it is considered that the circuit of the chip can include multiple power buses, for example, a high-level power bus and a low-level power bus need to be included. Therefore, the test method of the circuit tests the to-be-tested circuit with different power buses. That is, the voltage drops in different power buses are obtained corresponding to different power buses, including: for the voltage drop in the first power bus, the first voltage drop is determined according to the first test voltage and the first preset voltage; for the voltage drop in the second power bus, the second voltage drop is determined according to the second test voltage and the second preset voltage.

[0060] In the present exemplary embodiment, in order to determine the voltage drops of different power buses, the test power of different power buses is compared with the corresponding preset voltage to obtain the voltage drop of the corresponding power bus. The preset voltage includes the ideal voltage of the power network corresponding to the power bus of each circuit module in the to-be-tested circuit during the running of the chip. The power network includes the power connection relationship of the circuit module corresponding to the power bus. The corresponding preset voltage is different at different chip running stages, and therefore, the preset voltage of the circuit module corresponding to different power buses can be for different design stages.

[0061] Exemplarily, the first preset voltage includes the preset voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit at the first preset stage; and the second preset voltage includes the preset voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit at the first preset stage. The first network can also be referred to as the first power network, and the second network can also be referred to as the second power network. By simulating and testing the circuit at different design stages, obtaining the test voltage for different power buses, and comparing it with the corresponding preset voltage, the voltage drop can be accurately determined, so that the state of the to-be-tested circuit can be more accurately determined.

[0062] In the present exemplary embodiment, after the state of the to-be-tested circuit is determined, the state of the to-be-tested circuit is analyzed based on the state of the to-be-tested circuit, and it can be judged whether the to-be-tested circuit is qualified. The test method of the circuit realizes efficient and accurate testing of the to-be-tested circuit. In addition, based on the test method of the circuit, defects in the to-be-tested circuit can be found early. If the judgment result is unqualified, the state of the to-be-tested circuit can be analyzed based on this, and corresponding data support can be provided for the optimization and adjustment of the to-be-tested circuit.

[0063] In some exemplary embodiments, the state of the to-be-tested circuit is determined according to the first voltage drop and / or the second voltage drop, including: determining the state of the to-be-tested circuit according to whether the first voltage drop conforms to the first preset voltage drop and / or whether the second voltage drop conforms to the second preset voltage drop.

[0064] In the example embodiment, the first voltage drop corresponding to the first power bus is determined according to the first test voltage and the first preset voltage, and the second voltage drop corresponding to the second power bus is determined according to the second test voltage and the second preset voltage. By judging whether the first voltage drop meets the first preset voltage drop, the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus is judged to be qualified or not. By judging whether the second voltage drop meets the second preset voltage drop, the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus is judged to be qualified or not. By determining whether the first network and / or the second network is qualified, the state of the to-be-tested circuit is determined.

[0065] In some example embodiments, in order to accurately determine the state of the to-be-tested circuit, the preset voltage drops corresponding to different power buses need to be reasonably set. That is, the range interval of the first preset voltage drop serving as the reference standard of the first voltage drop can meet the normal working voltage requirement of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus, and the range interval of the second preset voltage drop serving as the reference standard of the second voltage drop can meet the normal working voltage requirement of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus. At this time, when setting the first preset voltage drop and the second preset voltage drop, a certain number of to-be-tested circuits of the same kind as the to-be-tested circuit in the first preset stage can be used as reference circuits, and the data obtained by simulating the reference circuits are counted to set the first preset voltage drop and the second preset voltage drop. Alternatively, a certain number of to-be-tested circuits of the same kind as the to-be-tested circuit in the second preset stage can be used as reference circuits, and the data obtained by simulating the reference circuits are counted to set the first preset voltage drop and the second preset voltage drop.

[0066] In the example embodiment, the first preset stage includes a stage before the first power bus and the second power bus are integrated, and the second preset stage includes a stage after the first power bus and the second power bus are integrated. The stage before the first power bus and the second power bus are integrated belongs to the early stage of chip design, at which time the architecture of the chip has been determined, and the circuit of the entire chip is basically completed, but the circuit layout of the chip is still in the planning stage and has not entered the large-scale layout stage. Since the to-be-tested circuit in the first preset stage has a first power bus and a second power bus that are not interlaced together but separated, the state of the to-be-tested circuit in the first preset stage can be determined relatively quickly. In addition, since the layout of the to-be-tested circuit in the first preset stage has not been completed, if the voltage drop result does not meet the requirement after the voltage drop analysis of the to-be-tested circuit, there is no need to modify the layout, which can further save time for the circuit design process of the chip and improve the circuit design efficiency of the chip.

[0067] In the exemplary embodiment of the present disclosure, the first preset voltage in the first preset stage can be determined according to the voltage drop determined by the simulation test on the to-be-tested circuit in the second preset stage. For example, as shown in Figure 2 Figure 2 is a flowchart of a method for determining the first preset voltage drop and the second preset voltage drop according to an exemplary embodiment. The test method further includes:

[0068] In step S201, the first preset voltage drop is determined according to the third voltage drop determined by the simulation test on the to-be-tested circuit in the second preset stage; the third voltage drop includes the voltage drop of the first network corresponding to the first power bus in the second preset stage;

[0069] In step S202, the second preset voltage drop is determined according to the fourth voltage drop determined by the simulation test on the to-be-tested circuit in the second preset stage; the fourth voltage drop includes the voltage drop of the second network corresponding to the second power bus in the second preset stage.

[0070] Considering that the other reference circuits of the same type as the to-be-tested circuit in the second preset stage have completed integration, at this time in the middle and late stages of chip design, the layout of each circuit module in the reference circuit has been basically determined and no longer needs to be adjusted in a large range. Therefore, after the voltage drops measured by the reference circuit in the second preset stage are counted, the first preset voltage drop and the second preset voltage drop determined can accurately reflect the working voltage drop required by the circuit module.

[0071] In the exemplary embodiment, the first preset voltage drop is determined according to the third voltage drop determined by the simulation test on the to-be-tested circuit in the second preset stage. In the case that the to-be-tested circuit is effectively running, the first preset voltage drop determined can accurately reflect the working voltage drop required by the first network corresponding to the first power bus in each circuit module of the to-be-tested circuit. The second preset voltage drop is determined according to the fourth voltage drop determined by the simulation test on the to-be-tested circuit in the second preset stage. In the case that the to-be-tested circuit is effectively running, the second preset voltage drop determined can accurately reflect the working voltage drop required by the second network corresponding to the second power bus in each circuit module of the to-be-tested circuit.

[0072] In the exemplary embodiment of the present disclosure, the first preset voltage in the first preset stage can be determined according to the voltage drop determined by the simulation test on the to-be-tested circuit in the first preset stage. For example, as shown in Figure 3 Figure 3 is a flowchart of a method for determining the first preset voltage drop and the second preset voltage drop according to an exemplary embodiment. The test method further includes:

[0073] ​​In step S301, the first preset voltage drop is determined according to the fifth voltage drop determined by the simulation test on the to-be-tested circuit in the first preset stage; the fifth voltage drop includes the voltage drop of the first network corresponding to the first power bus in the first preset stage.

[0074] In step S302, the second preset voltage drop is determined according to the sixth voltage drop determined by the simulation test on the to-be-tested circuit in the first preset stage; the sixth voltage drop includes the voltage drop of the second network corresponding to the second power bus in the first preset stage.

[0075] Since the other reference circuits of the same type as the to-be-tested circuit in the first preset stage have not been integrated, the layout of each circuit module in the reference circuit may need to be adjusted in a small range when the layout is re-integrated. However, the first preset voltage drop and the second preset voltage drop determined based on the voltage drop measured by the reference circuit in the first preset stage can accurately reflect the working voltage drop information of the circuit of the chip in the same stage at the initial design stage. The first preset voltage drop and the second preset voltage drop determined based on the test and statistics in the first preset stage can also achieve the test and evaluation of the circuit of the chip.

[0076] In the present exemplary embodiment, the first preset voltage drop determined according to the fifth voltage drop determined by the simulation test on the to-be-tested circuit in the first preset stage can accurately reflect the working voltage drop required by the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit; the second preset voltage drop determined according to the sixth voltage drop determined by the simulation test on the to-be-tested circuit in the first preset stage can accurately reflect the working voltage drop required by the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit.

[0077] In some exemplary embodiments, the simulation test includes: performing a preset test operation on the to-be-tested circuit, and the preset test operation includes a single test operation or a plurality of continuous single test operations within a preset time period. The single test operation includes reading test, writing test, and refresh test, etc. It can be understood that in the plurality of continuous single test operations within the preset time period, one of the single test operations such as reading mode, writing mode, and refresh test can be repeatedly tested, or each of the single test operations such as reading mode, writing mode, and refresh test can be tested one by one after combination.

[0078] Because in the early stage of chip design, the architecture of the chip has been determined, and the circuit of the whole chip is basically completed, but the circuit layout of the chip is still in the planning stage and has not entered the large-scale layout stage, after the comprehensive test based on the above-mentioned multiple test operations, the defects of the to-be-tested circuit are found, and then the optimization is carried out, without the need to modify the layout, a long time is saved, and the design efficiency of the chip is improved.

[0079] In some exemplary embodiments, the first voltage drop includes the average voltage difference and / or the peak voltage difference of the first network corresponding to the first power bus under the preset test operation of the to-be-tested circuit in the first preset stage; the second voltage drop includes the average voltage difference and / or the peak voltage difference of the second network corresponding to the second power bus under the preset test operation of the to-be-tested circuit in the first preset stage; the third voltage drop includes the average voltage difference and / or the peak voltage difference of the first network corresponding to the first power bus under the preset test operation of the to-be-tested circuit in the second preset stage; the fourth voltage drop includes the average voltage difference and / or the peak voltage difference of the second network corresponding to the second power bus under the preset test operation of the to-be-tested circuit in the second preset stage; the fifth voltage drop includes the average voltage difference and / or the peak voltage difference of the first network corresponding to the first power bus under the preset test operation of the to-be-tested circuit (corresponding to multiple other to-be-tested circuits and serving as a reference circuit) in the first preset stage; and the sixth voltage drop includes the average voltage difference and / or the peak voltage difference of the second network corresponding to the second power bus under the preset test operation of the to-be-tested circuit (corresponding to multiple other to-be-tested circuits and serving as a reference circuit) in the first preset stage.

[0080] In the present exemplary embodiments, when analyzing the voltage drop, multiple aspects such as the average voltage drop and the peak voltage drop can be combined for analysis. Therefore, when obtaining the first voltage drop, the second voltage drop, the third voltage drop, the fourth voltage drop, the fifth voltage drop and the sixth voltage drop, the voltage drop of the power supply network corresponding to the corresponding power bus (the first power bus and the second power bus) in the corresponding preset stage (the first preset stage and the second preset stage) is tested, based on which, comprehensive analysis of the voltage drop information in the to-be-tested circuit is realized, and the accuracy of the analysis result is ensured.

[0081] In some exemplary embodiments, after applying the test voltage to the to-be-tested circuit, the simulation test is performed on the to-be-tested circuit in the first preset stage, the first test voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit and the second test voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit are obtained; the first voltage drop is determined according to the first test voltage and the first preset voltage, and the second voltage drop is determined according to the second test voltage and the second preset voltage.

[0082] After the first voltage drop and the second voltage drop are determined, the state of the circuit under test is determined according to whether the first voltage drop meets the first preset voltage drop and / or whether the second voltage drop meets the second preset voltage drop. The first preset voltage drop can be determined according to a third voltage drop determined by performing simulation test on the circuit under test in the second preset stage, and the second preset voltage drop can be determined according to a fourth voltage drop determined by performing simulation test on the circuit under test in the second preset stage.

[0083] According to the test results, the voltage drops of the same power bus in different test stages can be compared. It should be noted that in the case where the operation test includes multiple, comparing the voltage drops in different test stages includes comparing the voltage drops of the same operation test in different test stages and comparing the overall results of all operation tests in different test stages. For example, assuming that the operation test includes read operation test and write operation test, the peak voltage drop in the first test stage can occur in the read operation test, and the peak voltage drop in the second test stage can occur in the write operation test. At this time, the peak voltage drops in different test stages can be compared from the overall perspective.

[0084] Further, if the circuit under test includes multiple, comparing the voltage drops in different test stages also includes comparing the voltage drops of the same circuit under test in different test stages and comparing the overall test results of all circuits under test in different test stages. Comparing the overall results of multiple test circuits has the same meaning as comparing the overall results of multiple operation tests, which will not be repeated here. However, it can be understood that at least two variables are included in different test stages when overall comparison is performed, i.e., different circuits under test and different operation tests.

[0085] Still further, since the voltage drop includes average voltage difference and peak voltage difference, and the voltage difference has polarity, comparing the voltage drops in different test stages also includes comparing the absolute values of the average voltage difference and the peak voltage difference, comparing the absolute values of the peak voltage difference, comparing the polarities included in the average voltage difference and the peak voltage difference (for example, the average voltage differences in the first test stage and the second test stage can be equal, but the voltage differences in the first test stage have both positive and negative, while the voltage differences in the second test stage have only positive or negative, or the absolute values of the peak voltage differences are equal, but the polarities are different), and comparing the operation tests and the circuits under test to which the peak voltage differences belong. Comparing the absolute values includes analyzing the difference of the absolute values and analyzing the multiple of the absolute values.

[0086] According to the above test results, the circuit under test with defects can be re-adjusted according to the design needs.

[0087] In some example embodiments, to determine the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus and the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus, a connection relationship table can be obtained in combination with simulation processing of the to-be-tested circuit. For example, the test method further includes: obtaining a first connection relationship table and a second connection relationship table of the to-be-tested circuit in the first preset stage, the first connection relationship table representing the connection relationship between the first power bus and each circuit module in the to-be-tested circuit in the first preset stage, and recording the first preset voltage of the first network of the circuit module corresponding to the first power bus; the second connection relationship table representing the connection relationship between the second power bus and the circuit module in the to-be-tested circuit in the first preset stage, and recording the second preset voltage of the second network of the circuit module corresponding to the second power bus.

[0088] In the example embodiment, for the to-be-tested circuit in the first preset stage, after obtaining the first connection relationship table, the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus and the corresponding first preset voltage can be determined based on the first connection relationship table; after obtaining the second connection relationship table, the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus and the corresponding second preset voltage can be determined based on the second connection relationship table, thereby providing a reference basis for determining the first voltage drop and the second voltage drop.

[0089] In some example embodiments, as shown in Figure 4 Figure 4 is a flowchart of a method for determining the third voltage drop and the fourth voltage drop according to an example embodiment. The test method further includes:

[0090] Step S401, performing simulation testing on the to-be-tested circuit in the second preset stage to obtain the third test voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus and the fourth test voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus;

[0091] Step S402, determining the third voltage drop according to the third test voltage and the third preset voltage; wherein the third preset voltage includes the preset voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus in the second preset stage;

[0092] Step S403, determining the fourth voltage drop according to the fourth test voltage and the fourth preset voltage, wherein the fourth preset voltage includes the preset voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus in the second preset stage.

[0093] ​In the present exemplary embodiment, the determination process of the third voltage drop and the fourth voltage drop is determined based on simulation results of the multiple to-be-tested circuits in the second preset stage as reference circuits. It should be noted that the determination process of the third voltage drop and the fourth voltage drop of the multiple to-be-tested circuits as reference circuits is similar to the test process of the to-be-tested circuit.

[0094] In addition, the fifth voltage drop and the sixth voltage drop can also be determined based on simulation results of the multiple to-be-tested circuits in the first preset stage as reference circuits by using a similar determination process of the third voltage drop and the fourth voltage drop, and the specific process is not described herein.

[0095] In some exemplary embodiments, for the to-be-tested circuit in the second preset stage, the connection relationship of each circuit module in the to-be-tested circuit in the second preset stage needs to be determined in the process of determining the third preset voltage drop and the fourth preset voltage drop. For example, the connection relationship table can be obtained by simulation processing, and then the determination is performed; or the superposition result of the first connection relationship table and the second connection relationship table can also be used to determine the connection relationship.

[0096] Exemplarily, the determination method of obtaining the connection relationship table by simulation processing can further include: obtaining a third connection relationship table and a fourth connection relationship table of the to-be-tested circuit in the second preset stage, the third connection relationship table representing the connection relationship between the first power bus in the to-be-tested circuit in the second preset stage and each circuit module in the to-be-tested circuit, and recording the third preset voltage of the circuit module related to the first power bus; the fourth connection relationship table representing the connection relationship between the second power bus in the to-be-tested circuit in the second preset stage and the circuit module, and recording the fourth preset voltage of the circuit module related to the second power bus. Similar to the determination method of the third voltage drop and the fourth voltage drop, the determination process of the third preset voltage drop and the fourth preset voltage drop is not described herein.

[0097] In some example embodiments, the first power bus includes a power supply bus of the circuit under test, and the second power bus includes a ground bus of the circuit under test. Since the power supply bus and the ground bus are designed independently in the early stage of the circuit layout of the chip, and then integrated, after obtaining the test results of the first test stage and the second test stage in multiple circuit design processes, the derivation process of the test results of the second test stage based on the test results of the first test stage can be obtained by comparing and summarizing the test results of different test stages. In the subsequent circuit design process, the state of the integrated power supply bus and ground bus can be quickly evaluated by testing the power supply bus and the ground bus before integration, which saves a lot of time for the overall process design of the circuit of the chip and improves the overall design efficiency of the circuit of the chip.

[0098] In some example embodiments, the test method further includes determining the state of the driving delay of the circuit module according to the first voltage drop and / or the second voltage drop under the plurality of preset test operations. After determining the state of the driving delay of the circuit module, the first network or the second network corresponding to the circuit module with a large driving delay can be adjusted and optimized, thereby improving the performance of the circuit under test.

[0099] An example embodiment of the present disclosure provides a test device for a circuit, as shown in Figure 5 Figure 5 is a structural schematic diagram of a test device for a circuit provided according to an example embodiment. The test device 500 includes:

[0100] The acquisition module 501 is configured to perform simulation testing on the circuit under test in the first preset stage, and acquire the first test voltage of the first network corresponding to the first power bus of each circuit module in the circuit under test and the second test voltage of the second network corresponding to the second power bus of each circuit module in the circuit under test;

[0101] The first determination module 502 is configured to determine the first voltage drop according to the first test voltage and the first preset voltage, wherein the first preset voltage includes the preset voltage of the first network corresponding to the first power bus of each circuit module in the circuit under test in the first preset stage; and determine the second voltage drop according to the second test voltage and the second preset voltage, wherein the second preset voltage includes the preset voltage of the second network corresponding to the second power bus of each circuit module in the circuit under test in the first preset stage;

[0102] The second determination module 503 is configured to determine the state of the circuit under test according to the first voltage drop and / or the second voltage drop.

[0103] ​An example embodiment of the present disclosure provides a testing device of a circuit, such as Figure 6 as shown, Figure 6 FIG. 6 is a structural schematic diagram of a testing device of a circuit provided according to an example embodiment of the present disclosure. The testing device 600 includes:

[0104] a processor 601;

[0105] a memory 602 for storing instructions executable by the processor 601;

[0106] The processor 601 is configured to perform the testing method of the circuit provided according to the example embodiment of the present disclosure.

[0107] An example embodiment of the present disclosure provides a non-transitory computer readable storage medium, when the instructions in the storage medium are executed by the processor of the device, the device can perform the testing method of the circuit provided by the example embodiment of the present disclosure.

[0108] In the description of the present disclosure, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between embodiments can be referred to each other.

[0109] In the description of the present disclosure, the description of the terms "embodiment", "example embodiment", "some implementations", "illustrative implementation", "example" and the like means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure.

[0110] In the present disclosure, the illustrative description of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0111] In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0112] It can be understood that the terms "first", "second" and the like used in the present disclosure can be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish the first structure from another structure.

[0113] In one or more drawings, like reference numerals designate identical elements throughout the several views. For the sake of clarity, not every portion of the drawings can be shown to scale. Also, certain portions of the drawings can be exaggerated, including the size of structures, for purposes of illustration. Where appropriate, like reference numerals designate corresponding parts throughout the written description. For the purposes of the present disclosure, the term "or" as used herein means "any one of A or B." Additionally, the term "comprising" is used throughout to mean including possibly one more of the recited elements thereof. Also, the term "coupled" as used herein means connected, whether directly or indirectly, whether electrically, mechanically or otherwise, and the term "coupling" refers to the action of connecting, whether directly or indirectly, whether electrically, mechanically or otherwise.

[0114] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present disclosure, but not to limit the present disclosure; although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method of testing a circuit, characterized by, The test method comprises: performing simulation test on the to-be-tested circuit in a first preset stage to obtain a first test voltage of a first network corresponding to a first power bus of each circuit module in the to-be-tested circuit and a second test voltage of a second network corresponding to a second power bus of each circuit module in the to-be-tested circuit; determining a first voltage drop according to the first test voltage and a first preset voltage, wherein the first preset voltage comprises a preset voltage of the first network corresponding to the first power bus of each circuit module in the to-be-tested circuit in the first preset stage; determining a second voltage drop according to the second test voltage and a second preset voltage, wherein the second preset voltage comprises a preset voltage of the second network corresponding to the second power bus of each circuit module in the to-be-tested circuit in the first preset stage; determining a state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop; determining a state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop, comprising: determining the state of the to-be-tested circuit according to whether the first voltage drop conforms to a first preset voltage drop and / or whether the second voltage drop conforms to a second preset voltage drop; The test method further comprises: determining the first preset voltage drop according to a third voltage drop determined by performing simulation test on the to-be-tested circuit in a second preset stage; the third voltage drop comprises a voltage drop of the first network corresponding to the first power bus in the second preset stage; determining the second preset voltage drop according to a fourth voltage drop determined by performing simulation test on the to-be-tested circuit in the second preset stage; the fourth voltage drop comprises a voltage drop of the second network corresponding to the second power bus in the second preset stage.

2. The method of testing a circuit of claim 1, wherein, The first preset stage comprises a stage before the first power bus and the second power bus are integrated; and the second preset stage comprises a stage after the first power bus and the second power bus are integrated.

3. A method of testing a circuit as claimed in any one of claims 1 or 2, characterised in that, The simulation test comprises: performing a preset test operation on the to-be-tested circuit, wherein the preset test operation comprises a single test operation or a plurality of continuous single test operations within a preset time length.

4. The method of testing a circuit of claim 3, wherein, The first voltage drop comprises an average voltage difference and / or a peak voltage difference of the first network corresponding to the first power bus of the to-be-tested circuit in the first preset stage under the preset test operation; The second voltage drop comprises an average voltage difference and / or a peak voltage difference of the second network corresponding to the second power bus of the to-be-tested circuit in the first preset stage under the preset test operation; The third voltage drop comprises an average voltage difference and / or a peak voltage difference of the first network corresponding to the first power bus of the to-be-tested circuit in the second preset stage under the preset test operation; The fourth voltage drop comprises an average voltage difference and / or a peak voltage difference of the second network corresponding to the second power bus of the to-be-tested circuit in the second preset stage under the preset test operation.

5. The method of testing a circuit of claim 1, wherein, The test method further comprises: The first connection relationship table and the second connection relationship table of the to-be-tested circuit in the first preset stage are acquired, the first connection relationship table represents the connection relationship between a first power bus in the to-be-tested circuit in the first preset stage and each circuit module in the to-be-tested circuit, and records the first preset voltage of a first network of the circuit module corresponding to the first power bus; and the second connection relationship table represents the connection relationship between a second power bus in the to-be-tested circuit in the first preset stage and the circuit module, and records the second preset voltage of a second network of the circuit module corresponding to the second power bus.

6. The method of testing a circuit of claim 1, wherein, The test method further comprises: performing simulation testing on the to-be-tested circuit in the second preset stage, acquiring the third test voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus, and the fourth test voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus; determining a third voltage drop according to the third test voltage and a third preset voltage, wherein the third preset voltage comprises the preset voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus in the second preset stage; determining a fourth voltage drop according to the fourth test voltage and a fourth preset voltage, wherein the fourth preset voltage comprises the preset voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus in the second preset stage.

7. The method of testing a circuit of claim 1, wherein, The first power bus comprises a power bus of the to-be-tested circuit, and the second power bus comprises a ground bus of the to-be-tested circuit.

8. The method of testing a circuit of claim 3, wherein, The test method further comprises: determining the state of the driving time delay of the circuit module according to the first voltage drop and / or the second voltage drop under a plurality of preset test operations.

9. A test apparatus for a circuit, characterized by The test device comprises: an acquisition module configured to perform simulation testing on a to-be-tested circuit in a first preset stage, acquire the first test voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus, and acquire the second test voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus; a first determination module configured to determine a first voltage drop according to the first test voltage and a first preset voltage, wherein the first preset voltage comprises the preset voltage of the first network of each circuit module in the to-be-tested circuit corresponding to the first power bus in the first preset stage, and determine a second voltage drop according to the second test voltage and a second preset voltage, wherein the second preset voltage comprises the preset voltage of the second network of each circuit module in the to-be-tested circuit corresponding to the second power bus in the first preset stage; a second determination module configured to determine the state of the to-be-tested circuit according to the first voltage drop and / or the second voltage drop; the second determination module is configured to: determining the first preset voltage drop according to a third voltage drop determined by performing simulation test on the to-be-tested circuit in the second preset stage; the third voltage drop comprises a voltage drop of a first network corresponding to the first power bus in the second preset stage; determining the second preset voltage drop according to a fourth voltage drop determined by performing simulation test on the to-be-tested circuit in the second preset stage; the fourth voltage drop comprises a voltage drop of a second network corresponding to the second power bus in the second preset stage; determining the state of the to-be-tested circuit according to whether the first voltage drop meets the first preset voltage drop and / or whether the second voltage drop meets the second preset voltage drop.

10. A test apparatus for a circuit, characterized by The test device comprises: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to perform the method of any one of claims 1-8. 11.A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an apparatus, enabling the apparatus to perform the method of any one of claims 1-8.

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