Display panel and manufacturing method thereof, and display device

Abstract

The embodiment of the present invention provides a display panel and a manufacturing method thereof, and a display device, which relate to the field of display technology and are used to enable an optical component setting area to have both better imaging quality and display effect. The display panel includes: a first display area, the first display area includes a first scan line and a first data line, the first scan line and the first data line define a first sub-pixel area, the first sub-pixel area includes a first common electrode and a first pixel electrode; a substrate; a planarization layer; a first light-transmitting conductive layer, located on the side of the planarization layer facing away from the substrate, the first common electrode is located on the first light-transmitting conductive layer; a second light-transmitting conductive layer, located on the side of the first light-transmitting conductive layer facing away from the substrate, the first pixel electrode is located on the second light-transmitting conductive layer; the first data line is formed of a light-transmitting conductive material, located on the side of the planarization layer facing the substrate, and / or the first scan line is formed of a light-transmitting conductive material, located on the side of the planarization layer facing the substrate.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. [Background technology]

[0002] For a display panel with a camera function, in order to increase the screen-to-body ratio of the panel, an optical component setting area is usually provided in the display area of ​​the panel, and a camera assembly is provided in the optical component setting area.

[0003] In the prior art, in order to solve the problem of insufficient light transmittance when taking pictures in the optical component setting area, the signal line in the optical component setting area is usually formed of a light-transmitting conductive material, and the black matrix above the signal line is removed at the same time. However, although the above design can improve the light transmittance of the optical component setting area, it will have an adverse effect on the display of the optical component setting area, making it difficult for the optical component setting area to have both good imaging quality and display effect. [Summary of the invention]

[0004] In view of this, an embodiment of the present invention provides a display panel and a display device, so that the optical component arrangement area has both better imaging quality and display effect.

[0005] In one aspect, an embodiment of the present invention provides a display panel, including:

[0006] A first display area, the first display area includes a first scan line and a first data line, the first scan line and the first data line define a plurality of first sub-pixel areas, the first sub-pixel areas include a first common electrode and a first pixel electrode;

[0007] substrate substrate;

[0008] A planarization layer, the planarization layer is located on the substrate;

[0009] a first light-transmitting conductive layer, wherein the first light-transmitting conductive layer is located on a side of the planarization layer facing away from the base substrate, and the first common electrode is located on the first light-transmitting conductive layer;

[0010] a second light-transmitting conductive layer, wherein the second light-transmitting conductive layer is located on a side of the first light-transmitting conductive layer facing away from the base substrate, and the first pixel electrode is located on the second light-transmitting conductive layer;

[0011] Wherein, the first data line is formed of a light-transmitting conductive material, and the first data line is located on a side of the planarization layer facing the base substrate, and / or the first scan line is formed of a light-transmitting conductive material, and the first scan line is located on a side of the planarization layer facing the base substrate.

[0012] On the other hand, an embodiment of the present invention provides a method for manufacturing a display panel, comprising:

[0013] forming a first data line and / or a first scan line in a first display area of ​​the base substrate, wherein the first data line and / or the first scan line are formed of a light-transmitting conductive material;

[0014] forming a planarization layer on a side of the first data line and / or the first scan line facing away from the substrate;

[0015] forming a first light-transmitting conductive layer on a side of the planarization layer facing away from the base substrate, wherein the first light-transmitting conductive layer comprises a first common electrode;

[0016] A second light-transmitting conductive layer is formed on a side of the first light-transmitting conductive layer facing away from the base substrate, and the second light-transmitting conductive layer includes a first pixel electrode.

[0017] In yet another aspect, an embodiment of the present invention provides a display device, comprising the above-mentioned display panel.

[0018] The above technical solution has the following beneficial effects:

[0019] In an embodiment of the present invention, by arranging the first data line and / or the first scan line on the side of the planarization layer facing the base substrate, the planarization layer can be used to increase the spacing between the first data line and / or the first scan line and the liquid crystal molecules, so that the first data line and the first scan line are far away from the liquid crystal molecules. In this way, even if the voltage on the first data line and the first scan line jumps, it is difficult to affect the liquid crystal molecules, effectively reducing the display abnormality problem of the first display area caused by the jump of the data signal and the scan signal, and weakening or even eliminating the dark line phenomenon. On the other hand, the first common electrode receives a fixed common voltage signal, and can also shield the influence of the interference electric field generated by the voltage jump on the first data line and the first scan line below it on the liquid crystal molecules, thereby reducing the risk of display abnormality in the first display area to a greater extent.

[0020] In addition, in the embodiment of the present invention, the first data line and / or the first scan line are located on the side of the planarization layer facing the base substrate. Based on this structure, in the process flow of the panel, the first data line and / or the first scan line are first formed, and then the planarization layer is formed. The first data line and the first scan line do not need to be deposited on the planarization layer. Therefore, the problem of easy peeling of the first data line and the first scan line caused by the poor adhesion between the resin material forming the planarization layer and the indium tin oxide (Indium Tin Oxides, ITO) material forming the first data line and the first scan line is avoided, thereby improving the stability of the first data line and the first scan line in the panel, thereby improving the reliability of data signal and scan signal transmission.

Brief Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A top view of an optical component arrangement area of ​​a display panel in the prior art;

[0023] Figure 2 for Figure 1 Cross-sectional view along the A1'-A2' direction;

[0024] Figure 3 A top view of a display panel provided by an embodiment of the present invention;

[0025] Figure 4 A schematic diagram of the arrangement positions of the first data line and the first scan line provided by an embodiment of the present invention;

[0026] Figure 5 A schematic diagram of a dark line at a data line position in an optical component setting area in the prior art;

[0027] Figure 6 A schematic diagram of a dark line at a first data line position in a first display area provided by an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of a connection between a first data line and a first scan line provided by an embodiment of the present invention;

[0029] Figure 8 for Figure 7 Cross-sectional view along the A1-A2 direction;

[0030] Fig. 9 Another connection diagram of the first data line and the first scan line provided by the embodiment of the present invention;

[0031] Fig.10 for Fig. 9 Cross-sectional view along the B1-B2 direction;

[0032] Fig.11 A schematic diagram of the dimensions of via holes in the first passivation layer and the second interlayer insulating layer provided in an embodiment of the present invention;

[0033] Fig.12 A schematic diagram of another arrangement position of the first data line and the first scan line provided in an embodiment of the present invention;

[0034] Fig.13A schematic diagram of another arrangement position of the first data line and the first scan line provided by an embodiment of the present invention;

[0035] Fig.14 for Fig.12 A schematic diagram of the connection between the corresponding first data line and the first scan line;

[0036] Fig.15 for Fig.13 A schematic diagram of the connection between the corresponding first data line and the first scan line;

[0037] Fig.16 for Fig.12 Another connection diagram of the corresponding first data line and the first scan line;

[0038] Fig.17 for Fig.13 Another connection diagram of the corresponding first data line and the first scan line;

[0039] Fig.18 A schematic diagram of another arrangement position of the first data line and the first scan line provided by an embodiment of the present invention;

[0040] Fig.19 A schematic diagram of another arrangement position of the first data line and the first scan line provided by an embodiment of the present invention;

[0041] Fig. 20 for Fig.18 A schematic diagram of the connection between the corresponding first data line and the first scan line;

[0042] Fig.21 for Fig.19 A schematic diagram of the connection between the corresponding first data line and the first scan line;

[0043] Fig. 22 for Fig.18 Another connection diagram of the corresponding first data line and the first scan line;

[0044] Fig.23 for Fig.19 Another connection diagram of the corresponding first data line and the first scan line;

[0045] Fig.24 for Fig.18 Another connection diagram of the corresponding first data line and the first scan line;

[0046] Fig.25 for Fig.19 Another connection diagram of the corresponding first data line and the first scan line;

[0047] Fig.26 A schematic structural diagram of a fourth passivation layer provided in an embodiment of the present invention;

[0048] Fig. 27 A schematic diagram of the structure of a fifth passivation layer provided in an embodiment of the present invention;

[0049] Fig.28 A schematic diagram of another arrangement position of the first data line and the first scan line provided by an embodiment of the present invention;

[0050] Fig.29 for Fig.28 A schematic diagram of the connection between the corresponding first data line and the first scan line;

[0051] Fig.30 for Fig.28 Another connection diagram of the corresponding first data line and the first scan line;

[0052] Fig.31 for Fig.28 Another connection diagram of the corresponding first data line and the first scan line;

[0053] Fig.32 A schematic diagram of the sizes of the first scan line and the first data line provided by an embodiment of the present invention;

[0054] Fig.33 A schematic diagram of the dimensions of a driving transistor provided in an embodiment of the present invention;

[0055] Fig.34 Another schematic diagram of the size of the driving transistor provided by the embodiment of the present invention;

[0056] Fig.35 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0057] Fig.36 A schematic diagram of the structure of a light shielding portion provided by an embodiment of the present invention;

[0058] Fig.37 A schematic diagram of the dimensions of a light shielding portion provided in an embodiment of the present invention;

[0059] Fig.38 A schematic diagram of the location of the touch layer provided in an embodiment of the present invention;

[0060] Fig.39 A schematic diagram of another arrangement position of the touch layer provided in an embodiment of the present invention;

[0061] Fig.40 A schematic diagram of another arrangement position of the touch layer provided in an embodiment of the present invention;

[0062] Fig.41 for Fig.40 Cross-sectional view along the C1-C2 direction;

[0063] Fig.42 A schematic diagram of the structure of the second display area provided by an embodiment of the present invention;

[0064] Fig.43 A flow chart of a method for manufacturing a display panel provided by an embodiment of the present invention;

[0065] Fig.44 Another flow chart of the method for manufacturing a display panel provided by an embodiment of the present invention;

[0066] Fig.45 A schematic diagram of the structure of a first passivation layer and a second passivation layer provided in an embodiment of the present invention;

[0067] Fig.46 Another schematic diagram of the structure of the first passivation layer and the second passivation layer provided in an embodiment of the present invention;

[0068] Fig.47 A schematic diagram of another structure of the first passivation layer and the second passivation layer provided in an embodiment of the present invention;

[0069] Fig.48 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. [Specific implementation method]

[0070] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0071] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0072] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0073] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0074] It should be understood that, although the terms first, second, third, etc. may be used to describe the light-transmitting conductive layer in the embodiments of the present invention, these light-transmitting conductive layers should not be limited to these terms. These terms are only used to distinguish the light-transmitting conductive layers from each other. For example, without departing from the scope of the embodiments of the present invention, the first light-transmitting conductive layer may also be referred to as the second light-transmitting conductive layer, and similarly, the second light-transmitting conductive layer may also be referred to as the first light-transmitting conductive layer.

[0075] Before describing the technical solutions provided by the embodiments of the present invention, the present invention first describes the problems existing in the prior art.

[0076] The display panel includes scan lines and data lines, which intersect to define a plurality of sub-pixel regions. Each sub-pixel region includes a common electrode and a pixel electrode, which are usually formed of light-transmitting conductive materials such as indium tin oxide (ITO).

[0077] Combined with the analysis in the background technology, for a display panel with a camera function, the display area of ​​the display panel includes an optical component setting area. In order to solve the problem of insufficient light transmittance in the optical component setting area during camera shooting, Figure 1 and Figure 2 As shown, Figure 1 It is a top view of the optical component setting area of ​​the display panel in the prior art, Figure 2 for Figure 1 In the cross-sectional view along the A1'-A2' direction, the scanning line Gate' and the data line Data' in the optical component setting area are arranged in the same layer and with the same material as the common electrode 1', and the scanning line Gate' and the data line Data' are not covered with a black matrix.

[0078] However, in order to drive the display panel to work properly, the voltages on the scan lines and data lines in the panel need to jump continuously. Taking the data lines as an example, as the scan lines scan row by row, when the i-th scan line outputs a scan signal to the i-th row sub-pixel, the j-th data line transmits the data voltage required to be received by the i-th row and j-th column sub-pixel, and when the i+1-th scan line outputs a scan signal to the i+1-th row sub-pixel, the voltage on the j-th data line jumps to the data voltage required by the i+1-th row and j-th column sub-pixel.

[0079] The voltage on the scan line and the data line is constantly changing, which will cause the liquid crystal molecules 2' on the upper side of the scan line and the data line to rotate continuously. Since there is no black matrix blocking the scan line Gate' and the data line Data' in the optical component setting area, the continuous rotation of the liquid crystal molecules 2' will cause the image displayed at the location of the scan line Gate' and the data line Data' to flicker continuously, and the continuous flickering of the image will cause the visual brightness of this part of the area to be significantly darker, which will cause obvious dark lines to appear at the location of the scan line Gate' and the data line Data'.

[0080] Also, see again Figure 2 When the scanning line Gate' and the data line Data' are arranged in the same layer as the common electrode 1', the scanning line Gate' and the data line Data' will be formed above the planarization layer 3'. The planarization layer 3' is usually formed of organic materials such as resin, and the resin material has poor adhesion to the indium tin oxide (ITO) material forming the scanning line Gate' and the data line Data', which makes the indium tin oxide material easy to peel off. In particular, the scanning line Gate' and the data line Data' are in a thin line structure, and the risk of peeling off is greater, and the risk of display abnormality in the optical component setting area is also greater.

[0081] To this end, an embodiment of the present invention provides a display panel that can solve the problem of insufficient light transmittance in the optical component setting area while avoiding adverse effects on the display in the optical component setting area, so that the optical component setting area has both better imaging quality and display effect.

[0082] like Figure 3 and Figure 4 As shown, Figure 3 A top view of a display panel provided by an embodiment of the present invention, Figure 4 The schematic diagram of the arrangement position of the first data line and the first scan line provided in the embodiment of the present invention, the display panel provided in the embodiment of the present invention includes a first display area 1, the first display area 1 can be the above-mentioned optical component arrangement area, and the first display area 1 is provided with a camera assembly for realizing the camera function. The first display area 1 includes a first scan line Gate1 and a first data line Data1, the first scan line Gate1 and the first data line Data1 define a plurality of first sub-pixel areas 3, and the first sub-pixel area 3 includes a first common electrode 4 and a first pixel electrode 5.

[0083] In addition, the display panel further includes: a base substrate 6, a planarization layer 7, a first light-transmitting conductive layer 8, and a second light-transmitting conductive layer 9. The planarization layer 7 is located on the base substrate 6; the first light-transmitting conductive layer 8 is located on the side of the planarization layer 7 that is not facing the base substrate 6; the first common electrode 4 is located on the first light-transmitting conductive layer 8; the second light-transmitting conductive layer 9 is located on the side of the first light-transmitting conductive layer 8 that is not facing the base substrate 6; and the first pixel electrode 5 is located on the second light-transmitting conductive layer 9. The first light-transmitting conductive layer 8 and the second light-transmitting conductive layer 9 can be specifically formed of a light-transmitting conductive material such as indium tin oxide.

[0084] Among them, the first data line Data1 is formed of a light-transmitting conductive material such as indium tin oxide, and the first data line Data1 is located on the side of the planarization layer 7 facing the base substrate 6, and / or the first scan line Gate1 is formed of a light-transmitting conductive material such as indium tin oxide, and the first scan line Gate1 is located on the side of the planarization layer 7 facing the base substrate 6.

[0085] It should be noted that, in order to achieve the planarization of the film layer, the film thickness of the planarization layer 7 in the direction perpendicular to the plane where the base substrate 6 is located is usually much greater than the film thickness of other film layers in the panel in the direction perpendicular to the plane where the base substrate 6 is located. In the embodiment of the present invention, by setting the first data line Data1 and / or the first scan line Gate1 on the side of the planarization layer 7 facing the base substrate 6, the planarization layer 7 can be used to increase the distance between the first data line Data1 and / or the first scan line Gate1 and the liquid crystal molecules, so that the first data line Data1 and the first scan line Gate1 are far away from the liquid crystal molecules. In this way, even if the voltage on the first data line Data1 and the first scan line Gate1 jumps, it is difficult to affect the liquid crystal molecules, effectively reducing the display abnormality of the first display area 1 caused by the jump of the data signal and the scan signal, and weakening or even eliminating the dark line phenomenon. On the other hand, the first common electrode 4 receives a fixed common voltage signal, and can also shield the influence of the interference electric field generated by the voltage jump on the first data line Data1 and the first scan line Gate1 below it on the liquid crystal molecules, thereby reducing the risk of display abnormality in the first display area 1 to a greater extent.

[0086] Moreover, the inventor has also verified this, such as Figure 5 and Figure 6 As shown, Figure 5 It is a schematic diagram of dark lines at the position of the data line Data' in the optical component setting area in the prior art. Figure 6 This is a schematic diagram of dark lines at the position of the first data line Data1 in the first display area 1 provided by an embodiment of the present invention, wherein the horizontal and vertical coordinates represent the position points in the X direction and the Y direction respectively. Figure 5 and Figure 6It can be seen that based on the structure provided by the embodiment of the present invention, the dark lines in the first display area are significantly weakened and difficult to be recognized by the human eye.

[0087] In addition, in the embodiment of the present invention, the first data line Data1 and / or the first scan line Gate1 are located on the side of the planarization layer 7 facing the base substrate 6. Based on this structure, in the process flow of the panel, the first data line Data1 and / or the first scan line Gate1 are first formed, and then the planarization layer 7 is formed. The first data line Data1 and the first scan line Gate1 do not need to be deposited on the planarization layer 7. Therefore, the problem of easy peeling of the first data line Data1 and the first scan line Gate1 caused by the poor adhesion between the resin material and the indium tin oxide material is avoided, and the stability of the first data line Data1 and the first scan line Gate1 in the panel is improved, thereby improving the reliability of data signal and scan signal transmission.

[0088] In one embodiment, see again Figure 3 and Figure 4 The first sub-pixel area 3 also includes a driving transistor 10, a gate 11 of the driving transistor 10 is electrically connected to the first scan line Gate1, a first electrode 12 of the driving transistor 10 is electrically connected to the first data line Data1, and a second electrode 13 of the driving transistor 10 is electrically connected to the first pixel electrode 5 in the first sub-pixel area 3.

[0089] Based on this, the display panel also includes: a semiconductor layer 14, the semiconductor layer 14 is located on the side of the planarization layer 7 facing the base substrate 6, and the active layer 15 of the driving transistor 10 is located in the semiconductor layer 14; a first interlayer insulating layer 16, the first interlayer insulating layer 16 is located on the side of the semiconductor layer 14 facing away from the base substrate 6; a first metal layer 17, the first metal layer 17 is located on the side of the first interlayer insulating layer 16 facing away from the base substrate 6, and the gate 11 of the driving transistor 10 is located in the first metal layer 17; a second interlayer insulating layer 18, the second interlayer insulating layer 18 is located on the side of the first metal layer 17 facing away from the base substrate 6; a second metal layer 19, the second metal layer 19 is located between the second interlayer insulating layer 18 and the planarization layer 7, and the first electrode 12 and the second electrode 13 of the driving transistor 10 are located in the second metal layer 19.

[0090] When the display panel displays an image, the first scan line Gate1 provides a scan signal to the gate 11 of the driving transistor 10 to control the driving transistor 10 to be turned on. The display data voltage provided by the first data line Data1 is transmitted to the first pixel electrode 5 electrically connected thereto through the turned-on driving transistor 10. The liquid crystal molecules rotate under the action of the electric field formed by the first pixel electrode 5 and the first common electrode 4 to achieve normal image display. When the display panel takes an image, the first scan line Gate1 provides a scan signal to the gate 11 of the driving transistor 10 to control the driving transistor 10 to be turned on. The image data voltage provided by the first data line Data1, such as the white state voltage corresponding to the 255 grayscale, is transmitted to the first pixel electrode 5 electrically connected thereto through the turned-on driving transistor 10. The liquid crystal molecules rotate under the action of the electric field formed by the first pixel electrode 5 and the first common electrode 4. The external ambient light penetrates the liquid crystal molecules and enters the camera component to achieve imaging.

[0091] In one embodiment, see again Figure 4 The display panel also includes a third light-transmitting conductive layer 20, and the first data line Data1 and the first scanning line Gate1 are both located in the third light-transmitting conductive layer 20. At this time, the first data line Data1 and the first scanning line Gate1 are arranged in the same layer, and the two parts of the wiring only need to occupy the thickness of one film layer, which is more conducive to the lightweight design of the panel.

[0092] Specifically, when the first data line Data1 and the first scan line Gate1 are both located in the third light-transmitting conductive layer 20 , the embodiment of the present invention takes the following three configurations as examples to illustrate the structure of the panel.

[0093] The first setting method:

[0094] Please see again Figure 4 The display panel further includes a first passivation layer 21 , the first passivation layer 21 is located between the second metal layer 19 and the planarization layer 7 , and the third light-transmitting conductive layer 20 is located between the first passivation layer 21 and the planarization layer 7 .

[0095] In this configuration, the third light-transmitting conductive layer 20 will not change the original process flow of the driving transistor 10. It is only necessary to add the process flow of the third light-transmitting conductive layer 20 after forming the driving transistor 10, and the manufacturing process of the panel is simpler. In addition, the etching of light-transmitting conductive materials such as indium tin oxide mostly adopts a wet etching process. By adding a first passivation layer 21 between the third light-transmitting conductive layer 20 and the second metal layer 19, the first passivation layer 21 can be used to protect the second metal layer 19, so as to prevent the third light-transmitting conductive layer 20 from etching away the metal in the second metal layer 19 by the wet etching process, thereby improving the reliability of signal transmission in the second metal layer 19.

[0096] Furthermore, if Figure 7and Figure 8 As shown, Figure 7 A connection diagram of the first data line Data1 and the first scan line Gate1 provided in an embodiment of the present invention is shown in FIG. Figure 8 for Figure 7 In the cross-sectional view along the A1-A2 direction, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, and the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, the first end 22 is electrically connected to the first scan line segment Gate11, and the second end 23 is electrically connected to the second scan line segment Gate12.

[0097] The first data line Data1 includes a first data line segment Data11 and a second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, the first passivation layer 21 includes a first via 26 and a second via 27, the first data line segment Data11 is electrically connected to the third end 24 through the first via 26, the second data line segment Data12 is electrically connected to the fourth end 25 through the second via 27, and the third end 24 is also electrically connected to the active layer 15 of the driving transistor 10.

[0098] In the above structure, the first data line Data1 and the first scan line Gate1 are both designed with a broken line at the overlapping position, and the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first data line segment Data11 and the second data line segment Data12, and the gate 11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, which not only ensures the effective electrical connection between the first data line segment Data11 and the second data line segment Data12, and between the first scan line segment Gate11 and the second scan line segment Gate12, but also does not need to set up an additional bridge structure, thereby simplifying the process. Moreover, compared with light-transmitting conductive materials such as indium tin oxide, the load of metal materials is smaller, so the above design can use the metal bridge to reduce the overall load of the first data line Data1 and the first scan line Gate1, thereby reducing the attenuation of the data signal and the scan signal during the transmission process.

[0099] Also, see again Figure 7 The length of the first electrode 12 of the driving transistor 10 in its extension direction is K. To ensure that the first electrode 12 of the driving transistor 10 has sufficient length so that there is a larger overlapping area between the first electrode 12 and the first data line segment Data11 and the second data line segment Data12, thereby improving the reliability of the connection, K can satisfy: 15μm≤K≤25μm.

[0100] Or, in another embodiment, Fig. 9 and Fig.10As shown, Fig. 9 Another connection diagram of the first data line Data1 and the first scan line Gate1 provided by an embodiment of the present invention is shown in FIG. Fig.10 for Fig. 9 In the cross-sectional view along the B1-B2 direction, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, and the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, the first end 22 is electrically connected to the first scan line segment Gate11, and the second end 23 is electrically connected to the second scan line segment Gate12. In a direction perpendicular to the plane where the base substrate 6 is located, the projection of the first data line Data1 overlaps with the projection of the gate 11 of the driving transistor 10, and the first passivation layer 21 includes a third via hole 28, and the first data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 through the third via hole 28, and the first electrode 12 of the driving transistor 10 is also electrically connected to the active layer 15 of the driving transistor 10.

[0101] In the above structure, the gate 11 of the driving transistor 10 is used as a metal bridge between the first scanning line segment Gate11 and the second scanning line segment Gate12. Since the gate 11 of the driving transistor 10 and the first data line Data1 are arranged in different layers, even if the first data line Data1 is designed to be a continuous line and overlaps the gate 11 of the driving transistor 10, it will not cause signal interference. Moreover, when the first data line Data1 is a continuous line, the first electrode 12 of the driving transistor 10 does not need to act as a metal bridge. Therefore, the shielding of the metal to the external ambient light can be reduced by reducing the size of the first electrode 12 of the driving transistor 10, so that more external ambient light can be transmitted through the first display area 1 and enter the camera component, effectively improving the imaging quality.

[0102] Based on the above Figure 7 and Fig. 9 In one embodiment, please refer to the structure shown in Figure 7 and Fig. 9 The second metal layer 19 also includes a first auxiliary connection portion 29 and a second auxiliary connection portion 30, the first auxiliary connection portion 29 is electrically connected between the first scanning line segment Gate11 and the first end 22, and the second auxiliary connection portion 30 is electrically connected between the second scanning line segment Gate12 and the second end 23.

[0103] When the third light-transmitting conductive layer 20 is located on the side of the second metal layer 19 facing away from the base substrate 6, the first scan line Gate1 is far away from the gate 11 of the driving transistor 10. The first scan line Gate1 needs to have at least a connection via that penetrates the first passivation layer 21 and the second interlayer insulating layer 18 to be electrically connected to the gate 11 of the driving transistor 10. Due to the large depth of the via, the metal material deposited in the via may be discontinuous, resulting in a disconnection between the first scan line Gate1 and the gate 11 of the driving transistor 10. In the embodiment of the present invention, an auxiliary connection portion is provided in the second metal layer 19, and the auxiliary connection portion can be used as an auxiliary connection layer between the first scan line Gate1 and the gate 11 of the driving transistor 10. The first scan line Gate1 only needs to be electrically connected to the auxiliary connection portion through the connection via that penetrates the first passivation layer 21, and then the auxiliary connection portion is electrically connected to the gate 11 of the driving transistor 10 through the connection via that penetrates the second interlayer insulating layer 18, which effectively improves the connection reliability between the first scan line Gate1 and the gate 11 of the driving transistor 10.

[0104] Furthermore, if Fig.11 As shown, Fig.11 The schematic diagram of the dimensions of the vias in the first passivation layer and the second interlayer insulating layer 18 provided in the embodiment of the present invention, the second interlayer insulating layer 18 includes the fifteenth via 31 and the sixteenth via 32, and the first passivation layer 21 includes the seventeenth via 33 and the eighteenth via 34. The first scanning line segment Gate11 is electrically connected to the first auxiliary connection portion 29 through the seventeenth via 33, and the first auxiliary connection portion 29 is further electrically connected to the first end 22 through the fifteenth via 31, and the second scanning line segment Gate12 is electrically connected to the second auxiliary connection portion 30 through the eighteenth via 34, and the second auxiliary connection portion 30 is further electrically connected to the second end 23 through the sixteenth via 32.

[0105] In a direction perpendicular to the plane where the base substrate 6 is located, the first auxiliary connection portion 29 covers the fifteenth via hole 31, and the distance between the edge of the projection of the first auxiliary connection portion 29 and the edge of the projection of the fifteenth via hole 31 is H1, 0.5μm≤H1≤2.0μm; in a direction perpendicular to the plane where the base substrate 6 is located, the second auxiliary connection portion 30 covers the sixteenth via hole 32, and the distance between the edge of the projection of the second auxiliary connection portion 30 and the edge of the projection of the sixteenth via hole 32 is H2, 0.5μm≤H2≤2.0μm; In the direction perpendicular to the plane of the base substrate 6, the first auxiliary connection portion 29 covers the seventeenth via 33, and the distance between the edge of the projection of the first auxiliary connection portion 29 and the edge of the projection of the seventeenth via 33 is P1, 0.5μm≤P1≤1.5μm; in the direction perpendicular to the plane of the base substrate 6, the second auxiliary connection portion 30 covers the eighteenth via 34, and the distance between the edge of the projection of the second auxiliary connection portion 30 and the edge of the projection of the eighteenth via 34 is P2, 0.5μm≤P2≤1.5μm.

[0106] At this time, the first auxiliary connection part 29 expands outward to the fifteenth via hole 31 in the second interlayer insulating layer 18, and the second auxiliary connection part 30 expands outward to the sixteenth via hole 32 in the second interlayer insulating layer 18. In the process of the panel, even if the film position of the auxiliary connection part is offset due to factors such as positioning errors, it can be ensured that the auxiliary connection part overlaps with the first scan line Gate1, thereby improving the connection reliability between the first scan line Gate1 and the auxiliary connection part. At the same time, the first auxiliary connection part 29 also expands outward to the seventeenth via hole 33 in the first passivation layer 21, and the second auxiliary connection part 30 also expands outward to the eighteenth via hole 34 in the first passivation layer 21. The connection reliability between the auxiliary connection part and the gate 11 of the driving transistor 10 is also higher.

[0107] In one embodiment, see again Fig.11 The thickness of the first passivation layer 21 on the plane perpendicular to the substrate 6 is D. Set the minimum value of D to The first passivation layer 21 can be prevented from being too thin. When the third light-transmitting conductive layer 20 is subjected to a wet etching process, the first passivation layer 21 can effectively protect the metal in the second metal layer 19 from being etched away, and the maximum value of D is further set to The first passivation layer 21 can be prevented from being too thick, thereby avoiding affecting the overall thickness of the panel.

[0108] The second setting method:

[0109] like Fig.12 and Fig.13 As shown, Fig.12This is a schematic diagram of another arrangement position of the first data line Data1 and the first scan line Gate1 provided in an embodiment of the present invention. Fig.13 A schematic diagram of another setting position of the first data line Data1 and the first scanning line Gate1 provided in an embodiment of the present invention, in a direction perpendicular to the plane where the base substrate 6 is located, the third light-transmitting conductive layer 20 is adjacent to the first metal layer 17, and the projection of the first scanning line Gate1 overlaps with the projection of the gate 11 of the driving transistor 10, and the first data line Data1 is electrically insulated from the gate 11 of the driving transistor 10.

[0110] That is to say, in this configuration, no insulating layer is provided between the third light-transmitting conductive layer 20 and the first metal layer 17, and the first scanning line Gate1 and the gate 11 of the driving transistor 10 are electrically connected by direct contact. Compared with connection through vias, on the one hand, the contact area between the two can be increased, and the connection is more stable. On the other hand, the risk of circuit breakage caused by discontinuity of the metal material deposited in the vias can be avoided. Moreover, this structure only requires the addition of a third light-transmitting conductive layer 20 in the panel, without the need for an additional insulating layer, which is more conducive to the thin and light design of the panel.

[0111] Further, please see again Fig.13 The first scanning line Gate1 is adjacent to the lower surface of the gate electrode 11 of the driving transistor 10 facing the base substrate 6 .

[0112] Compared with the first scan line Gate1 being located on the upper side of the gate 11 of the driving transistor 10, the first scan line Gate1 is located on the lower side of the gate 11 of the driving transistor 10. On the one hand, the distance between the first data line Data1, the first scan line Gate1 and the liquid crystal molecules can be increased to a greater extent, thereby reducing the influence of the voltage jump on the first data line Data1 and the first scan line Gate1 on the picture displayed in the first display area 1 to a greater extent; on the other hand, when the first scan line Gate1 is located on the lower side of the gate 11 of the driving transistor 10, in the process of the display panel, the third light-transmitting conductive layer 20 is first formed, and then the first metal layer 17 is formed, which can avoid the etching of the metal in the first metal layer 17 by the wet etching process of the third light-transmitting conductive layer 20.

[0113] It should be noted that metal etching usually adopts dry etching process, which has little effect on light-transmitting conductive materials such as indium tin oxide. Therefore, the dry etching process of the first metal layer 17 will not etch the third light-transmitting conductive layer 20 underneath.

[0114] Based on the above Fig.12 and Fig.13 The structure shown, in one embodiment, as Fig.14 and Fig.15As shown, Fig.14 for Fig.12 The corresponding connection diagram of the first data line Data1 and the first scan line Gate1, Fig.15 for Fig.13 Schematic diagram of the connection between the corresponding first data line Data1 and the first scan line Gate1, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, in a direction perpendicular to the plane where the substrate 6 is located, the projection of the first scan line segment Gate11 overlaps with the projection of the first end 22, and the projection of the second scan line segment Gate12 overlaps with the projection of the second end 23; the first data line Data1 includes a first data line segment Da ta11 and the second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, the second interlayer insulating layer 18 includes a fourth via 35 and a fifth via 36, ​​the third end 24 is electrically connected to the first data line segment Data11 through the fourth via 35, the fourth end 25 is electrically connected to the second data line segment Data12 through the fifth via 36, ​​the first interlayer insulating layer 16 also includes a sixth via 37, and the first data line segment Data11 is also electrically connected to the active layer 15 of the driving transistor 10 through the sixth via 37.

[0115] In the above structure, the first data line Data1 and the first scan line Gate1 are both designed with a broken line at the overlapping position, and the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first data line segment Data11 and the second data line segment Data12, and the gate 11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, which not only ensures the effective electrical connection between the first data line segment Data11 and the second data line segment Data12, and between the first scan line segment Gate11 and the second scan line segment Gate12, but also does not need to set up an additional bridge structure, thereby simplifying the process. Moreover, compared with light-transmitting conductive materials such as indium tin oxide, the load of metal materials is smaller, so the above design can use the metal bridge to reduce the overall load of the first data line Data1 and the first scan line Gate1, thereby reducing the attenuation of the data signal and the scan signal during the transmission process.

[0116] Or, in another embodiment, Fig.16 and Fig.17 As shown, Fig.16 for Fig.12 Another connection diagram of the corresponding first data line Data1 and the first scan line Gate1, Fig.17 for Fig.13Another connection schematic diagram of the corresponding first data line Data1 and the first scanning line Gate1, the first data line Data1 includes a first data line segment Data11 and a second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, the second interlayer insulating layer 18 includes a seventh via 38 and an eighth via 39, the third end 24 is electrically connected to the first data line segment Data11 through the seventh via 38, the fourth end 25 is connected to the second data line segment Data12 through the eighth via 39, the first interlayer insulating layer 16 also includes a ninth via 40, and the first data line segment Data11 is also electrically connected to the active layer 15 of the driving transistor 10 through the ninth via 40.

[0117] In the above structure, the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first data line segment Data11 and the second data line segment Data12. Since the first electrode 12 of the driving transistor 10 and the first scan line Gate1 are arranged in different layers, even if the first scan line Gate1 is designed to be a continuous line and overlap the first electrode 12 of the driving transistor 10, it will not cause signal interference. Moreover, when the first scan line Gate1 is a continuous line, there is a large overlapping area between the first scan line Gate1 and the gate 11 of the driving transistor 10. Even if the setting position of the first scan line Gate1 or the gate 11 of the driving transistor 10 deviates due to process error factors, it can still be ensured that the first scan line Gate1 contacts the gate 11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the gate 11 of the driving transistor 10 is high.

[0118] The third setting method:

[0119] like Fig.18 and Fig.19 As shown, Fig.18 This is another schematic diagram of the arrangement position of the first data line Data1 and the first scan line Gate1 provided in an embodiment of the present invention. Fig.19 A schematic diagram of another setting position of the first data line Data1 and the first scanning line Gate1 provided in an embodiment of the present invention, in a direction perpendicular to the plane where the base substrate 6 is located, the third light-transmitting conductive layer 20 is adjacent to the second metal layer 19, and in a direction perpendicular to the plane where the base substrate 6 is located, the projection of the first data line Data1 overlaps with the projection of the first electrode 12 of the driving transistor 10, the first data line Data1 is electrically insulated from the second electrode 13 of the driving transistor 10, and the first scanning line Gate1 is electrically insulated from the first electrode 12 and the second electrode 13 of the driving transistor 10, respectively.

[0120] That is to say, in this configuration, no insulating layer is provided between the third light-transmitting conductive layer 20 and the second metal layer 19, and the first data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 by direct contact. Compared with connection through a via hole, on the one hand, the contact area between the two can be increased, and the connection is more stable. On the other hand, the risk of circuit breakage caused by discontinuity of the metal material deposited in the via hole can be avoided. Moreover, this structure only requires the addition of a third light-transmitting conductive layer 20 in the panel, without the need for an additional insulating layer, which is more conducive to the thin and light design of the panel.

[0121] Further, please see again Fig.19 The first data line Data1 is adjacent to the lower surface of the first electrode 12 of the driving transistor 10 facing the base substrate 6 .

[0122] Compared with the first data line Data1 being located on the upper side of the driving transistor 10, the first data line Data1 is located on the lower side of the first electrode 12 of the driving transistor 10. On the one hand, the spacing between the first data line Data1, the first scanning line Gate1 and the liquid crystal molecules can be increased to a greater extent, thereby reducing the influence of the voltage jump on the first data line Data1 and the first scanning line Gate1 on the picture displayed in the first display area 1 to a greater extent; on the other hand, when the first data line Data1 is located on the lower side of the first electrode 12 of the driving transistor 10, in the process of the display panel, the third light-transmitting conductive layer 20 is first formed, and then the second metal layer 19 is formed, which can prevent the third light-transmitting conductive layer 20 from being etched away by the wet etching process. In addition, although the third light-transmitting conductive layer 20 is located on the side of the first metal layer 17 away from the base substrate 6, since the second interlayer insulating layer 18 is also separated between the third light-transmitting conductive layer 20 and the first metal layer 17, the wet etching process of the third light-transmitting conductive layer 20 will not etch away the metal in the first metal layer 17.

[0123] In addition, it should be noted that metal etching usually adopts dry etching process, which has little effect on transparent conductive materials such as indium tin oxide. Therefore, the dry etching process of the second metal layer 19 will not etch the third transparent conductive layer 20 underneath.

[0124] Based on the above Fig.18 and Fig.19 The structure shown, in one embodiment, as Fig. 20 and Fig.21 As shown, Fig. 20 for Fig.18 The corresponding connection diagram of the first data line Data1 and the first scan line Gate1, Fig.21 for Fig.19A schematic diagram of the connection between the corresponding first data line Data1 and the first scan line Gate1, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, the second interlayer insulating layer 18 includes a tenth via hole 41 and an eleventh via hole 42, the first scan line segment Gate11 is electrically connected to the first end 22 through the tenth via hole 41, and the second scan line segment Gate12 is electrically connected to the second end 23 through the eleventh via hole 42; the first data line Data1 includes a first data line segment Data11 and a second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, in a direction perpendicular to the plane where the substrate 6 is located, the projection of the third end 24 overlaps with the projection of the first data line segment Data11, the projection of the fourth end 25 overlaps with the projection of the second data line segment Data12, and the third end 24 is also electrically connected to the active layer 15 of the driving transistor 10.

[0125] In the above structure, the first data line Data1 and the first scan line Gate1 are both designed with a broken line at the overlapping position, and the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first data line segment Data11 and the second data line segment Data12, and the gate 11 of the driving transistor 10 is used as a metal bridge between the first scan line segment Gate11 and the second scan line segment Gate12, which not only ensures the effective electrical connection between the first data line segment Data11 and the second data line segment Data12, and between the first scan line segment Gate11 and the second scan line segment Gate12, but also does not need to set up an additional bridge structure, thereby simplifying the process. Moreover, compared with light-transmitting conductive materials such as indium tin oxide, the load of metal materials is smaller, so the above design can use the metal bridge to reduce the overall load of the first data line Data1 and the first scan line Gate1, thereby reducing the attenuation of the data signal and the scan signal during the transmission process.

[0126] Or, in another embodiment, Fig. 22 and Fig.23 As shown, Fig. 22 for Fig.18 Another connection diagram of the corresponding first data line Data1 and the first scan line Gate1, Fig.23 for Fig.19Another connection schematic diagram of the corresponding first data line Data1 and the first scan line Gate1, in the direction perpendicular to the plane where the substrate 6 is located, the projection of the first scan line Gate1 overlaps with the projection of the gate 11 of the driving transistor 10, the second interlayer insulating layer 18 includes a twelfth via 43, and the first scan line Gate1 is electrically connected to the gate 11 of the driving transistor 10 through the twelfth via 43; the first data line Data1 includes a first data line segment Data11 and a second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, in the direction perpendicular to the plane where the substrate 6 is located, the projection of the third end 24 overlaps with the projection of the first data line segment Data11, the projection of the fourth end 25 overlaps with the projection of the second data line segment Data12, and the third end 24 is also electrically connected to the active layer 15 of the driving transistor 10.

[0127] In the above structure, the first electrode 12 of the driving transistor 10 is used as a metal bridge between the first data line segment Data11 and the second data line segment Data12. Since the first electrode 12 of the driving transistor 10 and the first scan line Gate1 are arranged in different layers, even if the first scan line Gate1 is designed to be a continuous line and overlap the first electrode 12 of the driving transistor 10, it will not cause signal interference. Moreover, when the first scan line Gate1 is a continuous line, there is a large overlapping area between the first scan line Gate1 and the gate 11 of the driving transistor 10. Even if the setting position of the first scan line Gate1 or the gate 11 of the driving transistor 10 deviates due to process error factors, it can still be ensured that the first scan line Gate1 contacts the gate 11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the gate 11 of the driving transistor 10 is high.

[0128] Alternatively, in another embodiment, Fig.24 and Fig.25 As shown, Fig.24 for Fig.18 Another connection diagram of the corresponding first data line Data1 and the first scan line Gate1, Fig.25 for Fig.19Another connection diagram of the corresponding first data line Data1 and the first scan line Gate1, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, the second interlayer insulating layer 18 includes a thirteenth via hole 44 and a fourteenth via hole 45, the first scan line segment Gate11 is electrically connected to the first end 22 through the thirteenth via hole 44, and the second scan line segment Gate12 is electrically connected to the second end 23 through the fourteenth via hole 45. In the direction perpendicular to the plane where the base substrate 6 is located, the projection of the first data line Data1 overlaps with the projection of the first electrode 12 of the driving transistor 10, and the first electrode 12 of the driving transistor 10 is also electrically connected to the active layer 15 of the driving transistor 10.

[0129] In the above structure, the gate 11 of the driving transistor 10 is used as a metal bridge between the first scanning line segment Gate11 and the second scanning line segment Gate12. Since the gate 11 of the driving transistor 10 and the first data line Data1 are arranged in different layers, even if the first data line Data1 is designed to be a continuous line and overlap the gate 11 of the driving transistor 10, it will not cause signal interference. Moreover, when the first data line Data1 is a continuous line, there is a large overlapping area between the first data line Data1 and the first electrode 12 of the driving transistor 10. Even if the setting position of the first data line Data1 or the first electrode 12 of the driving transistor 10 deviates due to process error factors, it can still be ensured that the first data line Data1 is in contact with the first electrode 12 of the driving transistor 10, and the connection reliability between the first data line Data1 and the first electrode 12 of the driving transistor 10 is high.

[0130] It should be noted that, in other optional embodiments of the present invention, a passivation layer may be provided between the third light-transmitting conductive layer 20 and the first metal layer 17 or the second metal layer 19. Fig.26 As shown, Fig.26 This is a schematic diagram of the structure of the fourth passivation layer 81 provided in an embodiment of the present invention. When the third light-transmitting conductive layer 20 is located between the planarization layer 7 and the second interlayer insulating layer 18, a fourth passivation layer 81 may be further provided between the third light-transmitting conductive layer 20 and the second metal layer 19. In this way, when the third light-transmitting conductive layer 20 is located on the side of the second metal layer 19 facing away from the base substrate 6, the fourth passivation layer 81 may be used to protect the second metal layer 19 from being affected by the wet etching process of the third light-transmitting conductive layer 20. Alternatively, as Fig. 27 As shown, Fig. 27The schematic diagram of the structure of the fifth passivation layer 82 provided in the embodiment of the present invention, when the third light-transmitting conductive layer 20 is located between the first interlayer insulating layer 16 and the second interlayer insulating layer 18, a fifth passivation layer 82 may be further spaced between the third light-transmitting conductive layer 20 and the first metal layer 17. With this arrangement, when the third light-transmitting conductive layer 20 is located on the side of the first metal layer 17 facing away from the base substrate 6, the fifth passivation layer 82 may be used to protect the first metal layer 17 from being affected by the wet etching process of the third light-transmitting conductive layer 20.

[0131] In one embodiment, if Fig.28 As shown, Fig.28 This is another schematic diagram of the setting position of the first data line Data1 and the first scan line Gate1 provided in an embodiment of the present invention. The display panel also includes a fourth light-transmitting conductive layer 46 and a fifth light-transmitting conductive layer 47 arranged in different layers. The first data line Data1 is located in the fourth light-transmitting conductive layer 46, and the first scan line Gate1 is located in the fifth light-transmitting conductive layer 47.

[0132] When the first scan line Gate1 and the first data line Data1 are arranged in different layers, the arrangement positions of the first scan line Gate1 and the first data line Data1 are more flexible. Fig.28 The fifth light-transmitting conductive layer 47 can be disposed adjacent to the first metal layer 17, thereby making it easier to achieve electrical connection between the first scan line Gate1 and the gate electrode 11 of the driving transistor 10, and the fourth light-transmitting conductive layer 46 can be disposed adjacent to the second metal layer 19, thereby making it easier to achieve electrical connection between the first data line Data1 and the first electrode 12 of the driving transistor 10.

[0133] In one embodiment, see again Fig.28 In a direction perpendicular to the plane where the base substrate 6 is located, the fourth light-transmitting conductive layer 46 is adjacent to the second metal layer 19, and the projection of the first data line Data1 overlaps with the projection of the first electrode 12 of the driving transistor 10; in a direction perpendicular to the plane where the base substrate 6 is located, the fifth light-transmitting conductive layer 47 is adjacent to the first metal layer 17, and the projection of the first scanning line Gate1 overlaps with the projection of the gate 11 of the driving transistor 10.

[0134] Taking the fourth light-transmitting conductive layer 46 and the second metal layer 19 as an example, there is no insulating layer between the fourth light-transmitting conductive layer 46 and the second metal layer 19, and the first data line Data1 and the first electrode 12 of the driving transistor 10 are electrically connected by direct contact. Compared with the connection through a via hole, on the one hand, the contact area between the two can be increased, and the connection is more stable. On the other hand, the risk of disconnection caused by the discontinuity of the metal material deposited in the via hole can be avoided. Moreover, this structure can also reduce the number of insulating layers set in the panel, which is more conducive to the thin and light design of the panel.

[0135] Furthermore, if Fig.29 As shown, Fig.29 for Fig.28 The corresponding connection diagram of the first data line Data1 and the first scan line Gate1 shows that in the direction perpendicular to the plane of the substrate 6, the projection of the first data line Data1 overlaps with the projection of the first scan line Gate1. At this time, the first data line Data1 and the first scan line Gate1 are continuous wiring structures, and there is no need to set a metal bridge, which makes the process simpler.

[0136] Or, if Fig.30 As shown, Fig.30 for Fig.28 Another connection schematic diagram of the corresponding first data line Data1 and the first scan line Gate1, the first scan line Gate1 includes a first scan line segment Gate11 and a second scan line segment Gate12, the gate 11 of the driving transistor 10 includes a first end 22 and a second end 23, in a direction perpendicular to the plane where the substrate 6 is located, the projection of the first scan line segment Gate11 overlaps with the projection of the first end 22, and the projection of the second scan line segment Gate12 overlaps with the projection of the second end 23; in a direction perpendicular to the plane where the substrate 6 is located, the projection of the first data line Data1 overlaps with the projection of the gate 11 of the driving transistor 10.

[0137] At this time, the first data line Data1 is a continuous line, and there is a large overlapping area between the first data line Data1 and the first electrode 12 of the driving transistor 10. Even if the setting position of the first data line Data1 or the first electrode 12 of the driving transistor 10 deviates due to process error factors, it can still be ensured that the first data line Data1 is in contact with the first electrode 12 of the driving transistor 10, and the connection reliability between the first data line Data1 and the first electrode 12 of the driving transistor 10 is relatively high.

[0138] Or, if Fig.31 As shown, Fig.31 for Fig.28Another connection schematic diagram of the corresponding first data line Data1 and the first scan line Gate1, in the direction perpendicular to the plane where the substrate substrate 6 is located, the projection of the first scan line Gate1 overlaps with the projection of the first electrode 12 of the driving transistor 10; the first data line Data1 includes a first data line segment Data11 and a second data line segment Data12, the first electrode 12 of the driving transistor 10 includes a third end 24 and a fourth end 25, in the direction perpendicular to the plane where the substrate substrate 6 is located, the projection of the third end 24 overlaps with the projection of the first data line segment Data11, and the projection of the fourth end 25 overlaps with the projection of the second data line segment Data12.

[0139] At this time, the first scan line Gate1 is a continuous line, and there is a large overlapping area between the first scan line Gate1 and the gate 11 of the driving transistor 10. Even if the setting position of the first scan line Gate1 or the gate 11 of the driving transistor 10 deviates due to process errors, it can still be ensured that the first scan line Gate1 is in contact with the gate 11 of the driving transistor 10, and the connection reliability between the first scan line Gate1 and the gate 11 of the driving transistor 10 is relatively high.

[0140] In one implementation, in order to avoid an overload on the first scanning line Gate1, which would cause a large loss to the scanning signal, Fig.32 As shown, Fig.32 The schematic diagram of the dimensions of the first scan line Gate1 and the first data line Data1 provided in an embodiment of the present invention, the film thickness of the first scan line Gate1 on the plane perpendicular to the substrate 6 is X1, the line width of the first scan line Gate1 in the direction perpendicular to its extension is Z1, X1 and Z1 can satisfy: 2.5μm≤Z1≤9μm. To avoid excessive load on the first data line Data1 and large loss of data signal, the film thickness of the first data line Data1 on the plane perpendicular to the substrate 6 is X2, and the line width of the first data line Data1 in the direction perpendicular to its extension is Z2. X2 and Z2 can satisfy: 2.5μm≤Z2≤9μm.

[0141] In one embodiment, if Fig.33 As shown, Fig.33 This is a schematic diagram of the dimensions of the driving transistor 10 provided in an embodiment of the present invention. The active layer 15 of the driving transistor 10 is a U-shaped structure. The active layer 15 of the driving transistor 10 includes a first semiconductor portion 48, a second semiconductor portion 49 and a third semiconductor portion 50 that are connected in sequence.

[0142] In a direction perpendicular to the plane where the substrate 6 is located, the projection of the gate 11 of the driving transistor 10 overlaps with the projection of the first semiconductor portion 48 and the third semiconductor portion 50 respectively. The gate 11 of the driving transistor 10 includes a first side 51 and a second side 52 that are opposite to each other in the extension direction thereof. The minimum distance between the first side 51 and the first semiconductor portion 48 is greater than the minimum distance between the first side 51 and the third semiconductor portion 50. The distance between the projection edge of the first side 51 and the projection edge of the first semiconductor portion 48 is Q1, and the distance between the projection edge of the second side 52 and the projection edge of the third semiconductor portion 50 is Q2, 5μm≤Q1≤15μm, 5μm≤Q2≤15μm, so that the gate 11 of the driving transistor 10 has a sufficient length, ensuring that the gate 11 of the driving transistor 10 runs through the entire active layer 15 of the driving transistor 10, and is convenient for electrical connection with the first scanning line segment Gate11 and the second scanning line segment Gate12.

[0143] In one embodiment, if Fig.34 As shown, Fig.34 Another size schematic diagram of the driving transistor 10 provided in an embodiment of the present invention, the active layer 15 of the driving transistor 10 includes a connection island 53, the connection island 53 is electrically connected to the first electrode 12 of the driving transistor 10, in a direction perpendicular to the plane where the substrate 6 is located, the first electrode 12 of the driving transistor 10 covers the connection island 53, and the distance between the edge of the projection of the first electrode 12 of the driving transistor 10 and the edge of the projection of the connection island 53 is Y, 0≤Y≤1μm. At this time, the first electrode 12 of the driving transistor 10 is extended outside the connection island 53 of the active layer 15, and the first electrode 12 of the driving transistor 10 and the active layer 15 of the driving transistor 10 are more easily reliably electrically connected through vias.

[0144] In one embodiment, if Fig.35 and Fig.36 As shown, Fig.35 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Fig.36 The structural schematic diagram of the shading portion provided in an embodiment of the present invention, the display panel also includes a color film substrate 54 arranged opposite to the array substrate, the color film substrate 54 includes a shading layer 55, the shading layer 55 includes a plurality of shading portions 56 located in the first display area 1, in a direction perpendicular to the plane where the base substrate 6 is located, the projection of the shading portion 56 overlaps with the projection of the driving transistor 10 in the first sub-pixel area 3, and at least part of the edge of the shading portion 56 is a non-linear edge.

[0145] When the display panel is in camera mode, ambient light enters through the opening area of ​​the light shielding layer 55. If the light shielding layer 55 extends in a regular straight line, the ambient light enters through the gaps of the light shielding layer 55, and periodic interference is likely to occur, thereby generating diffraction fringes. By setting at least part of the edge of the light shielding portion 56 as a non-linear edge, the irregular edge of the light shielding portion 56 can be used to break the periodic interference of light, weaken the diffraction phenomenon, and thus reduce the impact of the diffraction fringes on the imaging quality.

[0146] Further, please see again Fig.36 The light shielding portion 56 includes at least one sub-light shielding portion 57, and the sub-light shielding portion 57 is circular or elliptical. For example, the light shielding portion 56 may include two circular sub-light shielding portions 57, thereby effectively covering the driving transistors 10 of different layout shapes.

[0147] In addition, if Fig.37 As shown, Fig.37 Schematic diagram of the size of the light shielding portion provided in an embodiment of the present invention. In a direction perpendicular to the plane where the substrate 6 is located, the light shielding portion 56 covers the gate 11 of the driving transistor 10, and the distance between the projected edge of the light shielding portion 56 and the projected edge of the gate 11 of the driving transistor 10 is E1, 0≤E1≤2.0μm; in a direction perpendicular to the plane where the substrate 6 is located, the light shielding portion 56 covers the first electrode 12 of the driving transistor 10, and the distance between the projected edge of the light shielding portion 56 and the projected edge of the first electrode 12 of the driving transistor 10 is E2, 0 ≤E2≤2.0μm; in a direction perpendicular to the plane where the substrate 6 is located, the shading portion 56 covers the second electrode 13 of the driving transistor 10, and the distance between the projected edge of the light shading portion 56 and the projected edge of the second electrode 13 of the driving transistor 10 is E3, 0≤E3≤2.0μm; in a direction perpendicular to the plane where the substrate 6 is located, the shading portion 56 covers the active layer 15 of the driving transistor 10, and the distance between the projected edge of the light shading portion 56 and the projected edge of the active layer 15 of the driving transistor 10 is E4, 0≤E4≤2.0μm.

[0148] At this time, the light shielding portion 56 completely covers the metal in the driving transistor 10, and the external ambient light will be absorbed by the light shielding portion 56 covering the driving transistor 10 after entering the first display area 1, so that it cannot be reflected by the metal in the driving transistor 10 to the human eye, thereby ensuring a good contrast. In addition, the light shielding portion 56 also completely covers the active layer 15 of the driving transistor 10, and the external ambient light or stray light cannot irradiate the active layer 15, thereby preventing the driving transistor 10 from generating leakage current, thereby improving the working stability of the driving transistor 10.

[0149] In one embodiment, if Fig.38 As shown, Fig.38This is a schematic diagram of the setting position of the touch layer provided in an embodiment of the present invention. The display panel also includes a touch layer 58 and a third passivation layer 60, wherein the touch layer 58 includes a touch signal line 59, the touch layer 58 is located between the first light-transmitting conductive layer 8 and the planarization layer 7, and the touch layer 58 is formed of a light-transmitting conductive material; the third passivation layer 60 is located between the touch layer 58 and the first light-transmitting conductive layer 8.

[0150] Since the touch layer 58 and the third passivation layer 60 are disposed on the side of the planarization layer 7 facing away from the base substrate 6, the touch layer 58 and the third passivation layer 60 can be used to further increase the distance between the first data line Data1 and the first scan line Gate1 and the liquid crystal molecules, thereby further reducing the influence of the voltage jump on the first data line Data1 and the first scan line Gate1 on the liquid crystal molecules. In addition, the touch layer 58 is also formed of a light-transmitting conductive material, which can reduce the shielding of the touch layer 58 on the first data line Data1 and the first scan line Gate1, and improve the light transmittance of the first display area 1.

[0151] Alternatively, in another embodiment, when the first data line Data1 and the first scan line Gate1 are located in the third light-transmitting metal layer, Fig.39 As shown, Fig.39 This is another schematic diagram of the setting position of the touch layer provided in an embodiment of the present invention. The display panel also includes a touch layer 58. The touch layer 58 includes a touch signal line 59. The touch signal line 59 extends in the same direction as the first data line Data1. The touch signal line 59 includes a first touch line segment 61, a second touch line segment 62 and a bridge 63. The bridge 63 is electrically connected between the first touch line segment 61 and the second touch line segment 62. In addition, in a direction perpendicular to the plane of the base substrate 6, the projection of the bridge 63 overlaps with the projection of the first scanning line Gate1. The first touch line segment 61 and the second touch line segment 62 are located in the third light-transmitting conductive layer 20. The bridge 63 and the third light-transmitting conductive layer 20 are arranged in different layers. For example, the bridge 63 can be located in the first metal layer 17, or in the second metal layer 19, or can be an additional metal layer.

[0152] In the above structure, the first touch line segment 61 and the second touch line segment 62 only need to be formed by the same patterning process as the first data line Data1 and the first scan line Gate1, without occupying additional film layer thickness. Moreover, the first touch line segment 61 and the second touch line segment 62 are electrically connected by a bridge 63, which can also prevent the first touch line segment 61 and the second touch line segment 62 from contacting the first scan line Gate1, thereby preventing crosstalk between touch signals and scan signals.

[0153] Alternatively, in another embodiment, when the first data line Data1 is located in the fourth light-transmitting metal layer and the first scan line Gate1 is located in the fifth light-transmitting metal layer, Fig.40 and Fig.41 As shown, Fig.40 A schematic diagram of another arrangement position of the touch layer provided in an embodiment of the present invention is shown. Fig.41 for Fig.40 In the cross-sectional view along the C1 - C2 direction, the display panel further includes a touch layer 58 . The touch layer 58 includes a touch signal line 59 . The touch signal line 59 extends in the same direction as the first data line Data1 , and the touch signal line 59 is located in the fourth light-transmissive conductive layer 46 .

[0154] In the above structure, the first data line Data1 and the first scan line Gate1 are arranged in different layers, and when the touch signal line 59 is located in the fourth light-transmitting conductive layer 46, it will not contact the first scan line Gate1, so the touch signal line 59 can be arranged as a continuous routing structure without setting a bridge, which simplifies the process of the touch signal line 59. Moreover, the touch signal line 59 does not need to occupy additional film layer space, and will not affect the overall thickness of the panel.

[0155] In addition, it should be noted that a light-blocking layer may also be provided on the side of the semiconductor layer 14 facing the base substrate 6. The light-blocking layer is located in the first display area 1 and is used to shield the active layer 15 of the driving transistor 10 to prevent the light emitted by the backlight into the panel from irradiating the active layer 15 and generating photogenerated carriers, thereby preventing the driving transistor 10 from generating leakage current.

[0156] In one embodiment, in combination Figure 3 ,like Fig.42 As shown, Fig.42 This is a structural schematic diagram of the second display area provided in an embodiment of the present invention. The display panel also includes a second display area 64 arranged adjacent to the first display area 1. The second display area 64 includes a second scan line Gate2 and a second data line Data2. The second scan line Gate2 and the second data line Data2 define a plurality of second sub-pixel areas 65. The second sub-pixel area 65 includes a second common electrode 66 and a second pixel electrode 67. The second scan line Gate2 is located in the first metal layer 17, the second data line Data2 is located in the second metal layer 19, the second scan line Gate2 is electrically connected to the first scan line Gate1 through a via, and the second data line Data2 is electrically connected to the first data line Data1 through a via.

[0157] Based on the same inventive concept, an embodiment of the present invention further provides a method for manufacturing a display panel, the manufacturing method is used to manufacture the above display panel, combined with Figure 3 and Figure 4 ,like Fig.43 As shown, Fig.43 The present invention provides a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. The method comprises:

[0158] Step S1: forming a first data line Data1 and / or a first scan line Gate1 in the first display area 1 of the base substrate 6, wherein the first data line Data1 and / or the first scan line Gate1 are formed of a light-transmitting conductive material.

[0159] Step S2 : forming a planarization layer 7 on a side of the first data line Data1 and / or the first scan line Gate1 facing away from the base substrate 6 .

[0160] Step S3 : forming a first light-transmitting conductive layer 8 on the side of the planarization layer 7 facing away from the base substrate 6 , wherein the first light-transmitting conductive layer 8 includes a first common electrode 4 .

[0161] Step S4 : forming a second light-transmitting conductive layer 9 on the side of the first light-transmitting conductive layer 8 facing away from the base substrate 6 , wherein the second light-transmitting conductive layer 9 includes the first pixel electrode 5 .

[0162] In the embodiment of the present invention, the first data line Data1 and / or the first scan line Gate1 are located on the side of the planarization layer 7 facing the base substrate 6. The first data line Data1 and the first scan line Gate1 are far away from the liquid crystal molecules. Even if the voltage on the first data line Data1 and the first scan line Gate1 jumps, it is difficult to affect the liquid crystal molecules, which effectively reduces the display abnormality of the first display area 1 caused by the jump of the data signal and the scan signal, and weakens or even eliminates the dark line phenomenon. On the other hand, the first common electrode 4 receives a fixed common voltage signal, and can also shield the interference electric field generated by the voltage jump on the first data line Data1 and the first scan line Gate1 below it from affecting the liquid crystal molecules, thereby reducing the risk of display abnormality in the first display area 1 to a greater extent.

[0163] In addition, in the embodiment of the present invention, the first data line Data1 and / or the first scan line Gate1 are first formed, and then the planarization layer 7 is formed. The first data line Data1 and the first scan line Gate1 do not need to be deposited on the planarization layer 7. Therefore, the problem of easy peeling of the first data line Data1 and the first scan line Gate1 caused by the poor adhesion between the resin material and the indium tin oxide material is avoided.

[0164] In one embodiment, see again Figure 3 and Figure 4 The display panel further includes a driving transistor 10 , a gate 11 of the driving transistor 10 is electrically connected to the first scan line Gate1 , a first electrode 12 of the driving transistor 10 is electrically connected to the first data line Data1 , and a second electrode 13 of the driving transistor 10 is electrically connected to the first pixel electrode 5 .

[0165] Based on this, Fig.44 As shown, Fig.44 Another flow chart of the method for manufacturing a display panel provided by an embodiment of the present invention, before forming the planarization layer 7, the manufacturing method further includes:

[0166] Step S01 : forming a semiconductor layer 14 on the base substrate 6 . The semiconductor layer 14 is located on a side of the planarization layer 7 facing the base substrate 6 . The semiconductor layer 14 includes an active layer 15 of the driving transistor 10 .

[0167] Step S02 : forming a first interlayer insulating layer 16 on the side of the semiconductor layer 14 facing away from the substrate 6 .

[0168] Step S03 : forming a first metal layer 17 on the side of the first interlayer insulating layer 16 facing away from the base substrate 6 , wherein the first metal layer 17 includes the gate 11 of the driving transistor 10 .

[0169] Step S04 : forming a second interlayer insulating layer 18 on the side of the first metal layer 17 facing away from the substrate 6 .

[0170] Step S05 : forming a second metal layer 19 on the side of the second interlayer insulating layer 18 facing away from the base substrate 6 , wherein the second metal layer 19 includes the first electrode 12 and the second electrode 13 of the driving transistor 10 .

[0171] In one embodiment, see again Fig.44 , step S1 may specifically include:

[0172] Step S11 : forming a first passivation layer 21 on the side of the second metal layer 19 facing away from the substrate 6 by using a first mask.

[0173] Step S12: forming a third light-transmitting conductive layer 20 on a side of the first passivation layer 21 facing away from the base substrate 6 , wherein the third light-transmitting conductive layer 20 includes a first data line Data1 and a first scanning line Gate1 .

[0174] In this configuration, the third light-transmitting conductive layer 20 will not change the original process flow of the driving transistor 10. It is only necessary to add the process flow of the third light-transmitting conductive layer 20 after forming the driving transistor 10, and the manufacturing process of the panel is simpler. In addition, the etching of light-transmitting conductive materials such as indium tin oxide mostly adopts a wet etching process. By adding a first passivation layer 21 between the third light-transmitting conductive layer 20 and the second metal layer 19, the first passivation layer 21 can be used to protect the second metal layer 19, so as to prevent the third light-transmitting conductive layer 20 from etching away the metal in the second metal layer 19 by the wet etching process, thereby improving the reliability of signal transmission in the second metal layer 19.

[0175] Furthermore, after forming the first light-transmitting conductive layer 8 and before forming the second light-transmitting conductive layer 9 , the manufacturing method further includes: forming a second passivation layer using a first mask.

[0176] When the first passivation layer 21 and the second passivation layer 80 are formed using the same mask, as shown in FIG. Fig.45 As shown, Fig.45 The schematic diagram of the structure of the first passivation layer 21 and the second passivation layer 80 provided in the embodiment of the present invention, the first passivation layer 21 includes the nineteenth via hole 70, the twentieth via hole 71 and the twenty-first via hole 72, the first data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 through the nineteenth via hole 70, and the first scan line Gate1 is electrically connected to the gate 11 of the driving transistor 10 through the twentieth via hole 71. The second passivation layer 80 includes the twenty-second via hole 73, the twenty-third via hole 74 and the twenty-fourth via hole 75, and the first pixel electrode 5 is electrically connected to the second electrode 13 of the driving transistor 10 through the twenty-fourth via hole 75 and the twenty-first via hole 72. In the direction perpendicular to the plane where the substrate 6 is located, the projection of the nineteenth via hole 70 coincides with the projection of the twenty-second via hole 73, the projection of the twentieth via hole 71 coincides with the projection of the twenty-third via hole 74, and the projection of the twenty-first via hole 72 coincides with the projection of the twenty-fourth via hole 75.

[0177] It should be noted that no conductive material is deposited in the twenty-second via hole 73 and the twenty-third via hole 74 in the second passivation layer 80 , and they are not used for electrical connection between conductive film layers.

[0178] By adopting the above manufacturing method, the first passivation layer 21 and the second passivation layer 80 are etched using the same mask plate, which reduces the number of masks required in the panel manufacturing process and reduces the process cost.

[0179] Alternatively, in another embodiment, after forming the first light-transmitting conductive layer 8 and before forming the second light-transmitting conductive layer 9 , the manufacturing method further includes: forming a second passivation layer 80 using a second mask.

[0180] When the first passivation layer 21 and the second passivation layer 80 are formed using different masks, such as Fig.46 As shown, Fig.46 Another structural schematic diagram of the first passivation layer 21 and the second passivation layer 80 provided in an embodiment of the present invention, the first passivation layer 21 includes the nineteenth via hole 70, the twentieth via hole 71 and the twenty-first via hole 72, the first data line Data1 is electrically connected to the first electrode 12 of the driving transistor 10 through the nineteenth via hole 70, and the first scan line Gate1 is electrically connected to the gate 11 of the driving transistor 10 through the twentieth via hole 71. The second passivation layer 80 includes only the twenty-fourth via hole 75, and the first pixel electrode 5 is electrically connected to the second electrode 13 of the driving transistor 10 through the twenty-fourth via hole 75, the twenty-first via hole 72 and the via hole in the planarization layer 7.

[0181] Using the above-mentioned manufacturing method, the first passivation layer 21 and the second passivation layer 80 are etched using different mask plates. There is no need to form idle twenty-second vias 73 and twenty-third vias 74 in the second passivation layer 80. The number of vias in the second passivation layer 80 is relatively small, and the second passivation layer 80 is easier to form a flat surface, which effectively improves the flatness of the film layer of the second passivation layer 80 and the uniformity of the box thickness of the panel.

[0182] Furthermore, if Fig.47 As shown, Fig.47 A schematic diagram of another structure of the first passivation layer 21 and the second passivation layer 80 provided in an embodiment of the present invention, the planarization layer 7 has a twenty-fifth via hole 76, in the direction perpendicular to the plane where the substrate 6 is located, the projection of the twenty-fifth via hole 76 covers the projection of the twenty-first via hole 72, and the aperture of the twenty-fifth via hole 76 is larger than the aperture of the twenty-first via hole 72, and the twenty-fifth via hole 76 and the twenty-first via hole 72 form a sleeve hole structure. At this time, for the nineteenth via hole 70, the twentieth via hole 71 and the twenty-first via hole 72 of the first passivation layer 21, compared with the nineteenth via hole 70 and the twenty-first via hole 71, the aperture of the twenty-first via hole 72 can be set smaller. Specifically, the aperture of the nineteenth via hole 70 is L1, 3.0 μm≤L1≤5.5 μm, the aperture of the twentieth via hole 71 is L2, 3.0 μm≤L2≤5.5 μm, and the aperture of the twenty-first via hole 72 is L3, 2.5 μm≤L3≤4.5 μm.

[0183] After the planarization layer 7 is formed on the first passivation layer 21, since the aperture of the twenty-first via hole 72 in the first passivation layer 21 is relatively small, in the process of forming the twenty-fifth via hole 76 on the planarization layer 7, the etching area corresponding to the twenty-fifth via hole 76 in the planarization layer 7 will cover the twenty-first via hole 72 and part of the first passivation layer 21 around the twenty-first via hole 72. Therefore, even if the etching process of the planarization layer 7 affects the first passivation layer 21, it will only affect the part of the first passivation layer 21 exposed in the twenty-fifth via hole 76, and will not make the aperture of the twenty-first via hole 72 become too large, thereby avoiding the situation where the aperture of the twenty-first via hole 72 is larger than the aperture of the twenty-fifth via hole 76, and then when the twenty-fourth via hole 75 of the second passivation layer 80 is subsequently formed, incomplete etching in the twenty-first via hole 72 is avoided, thereby improving the connection reliability between the first pixel electrode 5 and the second electrode 13 of the driving transistor 10.

[0184] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.48 As shown, Fig.481 is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. The specific structure and manufacturing method of the display panel 100 have been described in detail in the above-mentioned embodiment, and will not be repeated here. Fig.48 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0185] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A first display area, the first display area includes a first scan line and a first data line, the first scan line and the first data line define a plurality of first sub-pixel areas, the first sub-pixel areas include a first common electrode and a first pixel electrode, and the first display area is an optical component setting area; substrate substrate; A planarization layer, the planarization layer is located on the substrate; a first light-transmitting conductive layer, wherein the first light-transmitting conductive layer is located on a side of the planarization layer facing away from the base substrate, and the first common electrode is located on the first light-transmitting conductive layer; a second light-transmitting conductive layer, wherein the second light-transmitting conductive layer is located on a side of the first light-transmitting conductive layer facing away from the base substrate, and the first pixel electrode is located on the second light-transmitting conductive layer; Wherein, the first data line is formed of a light-transmitting conductive material, and the first data line is located on a side of the planarization layer facing the base substrate, and / or the first scan line is formed of a light-transmitting conductive material, and the first scan line is located on a side of the planarization layer facing the base substrate; The first sub-pixel region further includes a driving transistor, a gate of the driving transistor is electrically connected to the first scan line, a first electrode of the driving transistor is electrically connected to the first data line, and a second electrode of the driving transistor is electrically connected to the first pixel electrode in the first sub-pixel region; The display panel further includes: A semiconductor layer, the semiconductor layer is located on a side of the planarization layer facing the substrate, and the active layer of the driving transistor is located on the semiconductor layer; A first interlayer insulating layer, wherein the first interlayer insulating layer is located on a side of the semiconductor layer facing away from the substrate; A first metal layer, the first metal layer is located on a side of the first interlayer insulating layer facing away from the substrate, and the gate of the driving transistor is located on the first metal layer; a second interlayer insulating layer, wherein the second interlayer insulating layer is located on a side of the first metal layer facing away from the substrate; a second metal layer, wherein the second metal layer is located between the second interlayer insulating layer and the planarization layer, and the first electrode and the second electrode of the driving transistor are located in the second metal layer; A fourth light-transmitting conductive layer and a fifth light-transmitting conductive layer are arranged in different layers, the first data line is located in the fourth light-transmitting conductive layer, and the first scanning line is located in the fifth light-transmitting conductive layer.

2. The display panel according to claim 1, characterized in that: In a direction perpendicular to the plane where the base substrate is located, the fourth light-transmitting conductive layer is disposed adjacent to the second metal layer, and a projection of the first data line overlaps with a projection of the first electrode of the driving transistor; In a direction perpendicular to the plane where the base substrate is located, the fifth light-transmitting conductive layer is disposed adjacent to the first metal layer, and a projection of the first scanning line overlaps with a projection of the gate of the driving transistor.

3. The display panel according to claim 2, characterized in that: In a direction perpendicular to the plane where the substrate is located, a projection of the first data line overlaps with a projection of the first scan line, and the first data line and the first scan line are in a continuous wiring structure.

4. The display panel according to claim 2, characterized in that: The first scan line includes a first scan line segment and a second scan line segment, the gate of the driving transistor includes a first end and a second end, and in a direction perpendicular to the plane where the substrate is located, the projection of the first scan line segment overlaps with the projection of the first end, and the projection of the second scan line segment overlaps with the projection of the second end; in a direction perpendicular to the plane where the substrate is located, the projection of the first data line overlaps with the projection of the gate of the driving transistor.

5. The display panel according to claim 2, characterized in that: The first data line includes a first data line segment and a second data line segment, the first electrode of the driving transistor includes a third end and a fourth end, and in a direction perpendicular to the plane where the substrate is located, the projection of the first scan line overlaps with the projection of the first electrode of the driving transistor; in a direction perpendicular to the plane where the substrate is located, the projection of the third end overlaps with the projection of the first data line segment, and the projection of the fourth end overlaps with the projection of the second data line segment.

6. The display panel according to claim 1, characterized in that: The display panel further includes: A color film substrate is arranged opposite to the array substrate, the color film substrate includes a shading layer, the shading layer includes a plurality of shading portions located in the first display area, in a direction perpendicular to the plane where the base substrate is located, the projection of the shading portion overlaps with the projection of the driving transistor in the first sub-pixel area, and at least part of the edge of the shading portion is a non-linear edge.

7. The display panel according to claim 6, characterized in that: The light shielding portion includes at least one sub-light shielding portion, and the sub-light shielding portion is circular or elliptical in shape.

8. The display panel according to claim 1, characterized in that: The display panel further includes: A touch layer, the touch layer comprising a touch signal line, the touch layer being located between the first light-transmitting conductive layer and the planarization layer, and the touch layer being formed of a light-transmitting conductive material; A third passivation layer is located between the touch control layer and the first light-transmitting conductive layer.

9. The display panel according to claim 1, characterized in that: The display panel further includes: A touch layer, wherein the touch layer comprises a touch signal line, the touch signal line and the first data line extend in the same direction, and the touch signal line is located in the fourth light-transmissive conductive layer.

10. The display panel according to claim 1, characterized in that: The display panel further includes a second display area adjacent to the first display area, the second display area includes a second scan line and a second data line, the second scan line and the second data line define a plurality of second sub-pixel areas, the second sub-pixel areas include a second common electrode and a second pixel electrode; Wherein, the second scan line is located in the first metal layer, and the second data line is located in the second metal layer.

11. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 10.

Images