Data processing method, driving chip, system and display module

Abstract

Embodiments of the present invention provide a data processing method, a driving chip, a system, and a display module, which relate to the field of integrated circuit technologies. By executing the data processing method, the driving chip in the embodiments of the present invention can output a data signal SDO that is in the same phase as the data signal SDI, and can also generate a refresh clock signal whose rising edge is aligned with the data signal SDI and the data signal SDO internally. Therefore, each driving chip can perform data refreshing based on the refresh clock signal generated internally, which not only saves a clock signal line but also eliminates the refresh clock delay existing in the prior art, enabling the cascaded driving chips to synchronously refresh data.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a data processing method, a driving chip, a system, and a display module. Background Art

[0002] Display screens are currently widely used and can be used to play text information, animated advertisements, video images, etc.

[0003] In the display module of a display screen, it includes a control card and multiple cascaded driving chips. The control card sends a refresh clock signal CLK to the driving chips through a clock signal line and sends a data signal SDI to the driving chips through a data signal line. After receiving the data signal SDI, the driving chip outputs a data signal SDO and transmits it to the next cascaded driving chip through a data signal line. When all the driving chips have received the data signal SDI, data refreshing is performed based on the refresh clock signal CLK.

[0004] Among them, there are two ways for the driving chip to receive the refresh clock signal CLK:

[0005] One way is that the control card sends the refresh clock signal CLK to each driving chip in parallel through a clock signal line. However, this way has a relatively high driving power consumption, high requirements for the control card, and parallel wiring will occupy a relatively large chip area, so it is generally not adopted.

[0006] Another way is that the cascaded driving chips transmit the refresh clock signal CLK through a clock signal line between the driving chips. That is, after receiving the refresh clock signal CLK sent by the control card, the driving chip outputs the refresh clock signal CLK to the next cascaded driving chip through a clock signal line, and the next driving chip then sends the refresh clock signal CLK to the next lower driving chip, and so on, so that all the cascaded driving chips receive the refresh clock signal CLK. It can be seen that in this solution, at least two signal lines (clock signal line and data signal line) are required to connect between two adjacent cascaded driving chips, which is not conducive to saving the area of the driving chip. Summary of the Invention

[0007] Embodiments of the present invention provide a data processing method, a driving chip, a system, and a display module, which can reduce the at least one clock signal line and one data signal line currently used for data transmission to only one data signal line, reducing the number of ports required for the chip and the number of circuit board traces.

[0008] To solve the above problems, in a first aspect, embodiments of the present invention disclose a data processing method, and the method includes:

[0009] Receive a data signal SDI. The data signal SDI includes waveform one that can represent data 0 and waveform two that can represent data 1. In the same preset clock cycle, both waveform one and waveform two include a high-level segment and the durations of the high-level segments are not equal.

[0010] Based on the data signal SDI, generate a multi-phase clock signal. The multi-phase clock signal includes clock signal A that is delayed by the first phase compared to the data signal SDI, clock signal B that is delayed by the second phase, and clock signal C that is delayed by the third phase. Among them, the first phase, the second phase, and the third phase are all different, and the second phase is located between the first phase and the third phase.

[0011] According to the data signal SDI and clock signal B, generate a refresh clock signal and an edge selection signal. Among them, the rising edge of the refresh clock signal is aligned with the rising edge of the data signal SDI, the falling edge is aligned with the rising edge of the clock signal B, and the edge selection signal is obtained by sampling the data signal SDI through the rising edge of the clock signal B.

[0012] Based on the refresh clock signal, the edge selection signal, and the multi-phase clock signal, output a data signal SDO that is in phase with the data signal SDI. Among them, the rising edge of the data signal SDO is aligned with the rising edge of the refresh clock signal, and the falling edge of the data signal SDO is determined based on the edge selection signal and the multi-phase clock signal.

[0013] Furthermore, the time of delaying the first phase is equal to the duration of the high-level segment in waveform one, and the time of delaying the third phase is equal to the duration of the high-level segment in waveform two.

[0014] The falling edge of the data signal SDO is determined based on the edge selection signal and the multi-phase clock signal, including:

[0015] The falling edge of the data signal SDO is aligned with the rising edge of clock signal A or the rising edge of clock signal C based on the edge selection signal.

[0016] Furthermore, the falling edge of the data signal SDO is aligned with the rising edge of clock signal A or the rising edge of clock signal C based on the edge selection signal, including:

[0017] When the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of clock signal A; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of clock signal C; or

[0018] When the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of clock signal C; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of clock signal A.

[0019] Further, 0° < the first phase < 180°, 180° < the third phase < 360°; or,

[0020] 180° < the first phase < 360°, 0° < the third phase < 180°.

[0021] Optionally, the phase differences between the first phase, the second phase, and the third phase are all 90°.

[0022] Optionally, the first phase is 90°, the second phase is 180°, and the third phase is 270°; or

[0023] the first phase is 270°, the second phase is 180°, and the third phase is 90°.

[0024] In a second aspect, an embodiment of the present invention discloses a driving chip. The driving chip has an SDI input terminal and an SDO output terminal. The SDI input terminal is used to be connected to a control card or the previous cascaded driving chip through a data signal line, and the SDO output terminal is used to be connected to the next cascaded driving chip through a data signal line; wherein, in the case of not having a clock signal input terminal and a clock signal output terminal, the driving chip executes the data processing method of the first aspect of the embodiment of the present invention.

[0025] In a third aspect, an embodiment of the present invention discloses a driving system, including a control card and multiple cascaded driving chips. The driving chips are the driving chips of the second aspect of the embodiment of the present invention. The multiple cascaded driving chips are connected through a data signal line. The control card is connected to the first driving chip among the multiple cascaded driving chips through a data signal line. The data signal line is used to transmit the data signal SDI or the data signal SDO.

[0026] In a fourth aspect, an embodiment of the present invention discloses a display module, including a display end and the driving system of the third aspect of the embodiment of the present invention.

[0027] The embodiments of the present invention have the following advantages:

[0028] By executing the data processing method, the driving chip of the embodiment of the present invention can output a data signal SDO in the same phase as the data signal SDI, and at the same time can also generate a refresh clock signal with its rising edge aligned with the data signal SDI inside. Therefore, each driving chip can perform data refreshing based on the refresh clock signal generated inside itself. In this way, it is possible to achieve the refresh function that can only be achieved by using two signal lines (at least one clock signal line and one data signal line) in the prior art with only one data signal line. Compared with the prior art, for each driving chip, at least two pins can be saved, the wiring is simplified, and it is beneficial to save the chip area.

[0029] In addition, since the data signal SDO output in the embodiment of the present invention is in the same phase as the data signal SDI, that is, there is no phase delay between the output data signal SDO and the received data signal SDI. On this basis, since the rising edge of the generated refresh clock signal is aligned with the rising edges of both the data signal SDI and the data signal SDO, that is, the refresh clock signals generated by each driving chip based on the in-phase data signal SDI can also remain in the same phase, theoretically, the refresh clock delay existing in the prior art can be eliminated by 100%, enabling each cascaded driving chip to refresh data synchronously. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 is a schematic structural diagram of a driving chip according to an embodiment of the present invention;

[0032] Figure 2 is a flowchart of the steps of a data processing method according to an embodiment of the present invention;

[0033] Figure 3 (a) is a schematic diagram of waveform 1 and waveform 2 according to an embodiment of the present invention;

[0034] Figure 3 (b) is a schematic diagram of waveform 1 and waveform 2 according to another embodiment of the present invention;

[0035] Figure 4 is a schematic waveform diagram of a data signal SDI according to an example of the present invention;

[0036] FIG. 5(a) is an example schematic diagram of comparing clock signal A and clock signal C with data signal SDI according to an embodiment of the present invention;

[0037] FIG. 5(b) is another example schematic diagram of comparing clock signal A and clock signal C with data signal SDI according to an embodiment of the present invention;

[0038] FIG. 6(a) is an example schematic diagram of comparing clock signal A and clock signal C with data signal SDI according to another embodiment of the present invention;

[0039] FIG. 6(b) is another example schematic diagram of comparing clock signal A and clock signal C with data signal SDI according to another embodiment of the present invention;

[0040] Figure 7It is a schematic diagram of generating a refresh clock signal and an edge selection signal in an embodiment of the present invention;

[0041] Figure 8 It is a schematic diagram of outputting a data signal SDO in an embodiment of the present invention;

[0042] Figure 9 It is a schematic diagram of a driving system in an embodiment of the present invention. Detailed implementation manners

[0043] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0044] As described in the background art content, currently, between cascaded driving chips, a refresh clock signal CLK is transmitted through a clock signal line, and a data signal SDI or SDO is transmitted through a data signal line. In addition to the problem that at least two signal lines are required, which is not conducive to saving the area of the driving chip, the inventor found that for the same driving chip, there is an unknown delay t between the received refresh clock signal CLK (for convenience of description, denoted as CLK-in) and the output refresh clock signal (for convenience of description, denoted as CLK-out). Since the refresh clock signal CLK-out output by the previous driving chip is the refresh clock signal CLK-in input by the next driving chip, the more cascaded driving chips there are, the greater the delay of the refresh clock signal CLK-in obtained by the last driving chip (i.e., the refresh clock signal CLK-out output by the previous driving chip) compared to the refresh clock signal CLK-in obtained by the first cascaded driving chip, and the delay difference is almost (N - 1)t. Thus, when each driving chip outputs a signal to the display end based on the received refresh clock signal CLK for data refreshing, the displayed data refreshed by each driving chip will be out of sync.

[0045] In view of this, embodiments of the present invention provide a data processing method, a driving chip, a system, and a display module. The data processing method can be executed by the driving chip. Without using a clock signal line, after the driving chip receives the data signal SDI through only one data signal line, by executing this data processing method, it can output a data signal SDO in the same phase as the data signal SDI. In this implementation process, for each driving chip, not only is the clock signal line saved, the wiring is simplified, and the chip area is saved, but also the unknown delay between the input refresh clock signal CLK-in and the output refresh clock signal CLK-out is unexpectedly eliminated, improving the display effect.

[0046] Specifically, referring to Figure 1 , Figure 1 FIG. shows a schematic structural diagram of a driving chip according to an embodiment of the present invention. The driving chip has an SDI input terminal and an SDO output terminal. The SDI input terminal is used to connect to a control card or the previous cascaded driving chip through one data signal line, and the SDO output terminal is used to connect to the next cascaded driving chip through one data signal line.

[0047] From Figure 1 it can be seen that the driving chip does not have a clock signal input terminal and a clock signal output terminal, that is, the refresh clock signal cannot be transmitted through the clock signal line. In this case, after the driving chip receives the data signal SDI, it can execute the following data processing method to achieve the object of the present invention, that is, output a data signal SDO in the same phase as the data signal SDI, and at the same time eliminate the unknown delay between the input refresh clock signal CLK-in and the output refresh clock signal CLK-out, so that each driving chip can be refreshed synchronously.

[0048] Specifically, referring to Figure 2 , Figure 2 FIG. shows a flowchart of steps of a data processing method according to an embodiment of the present invention. The method may include:

[0049] Step S202, the driving chip receives the data signal SDI. The data signal SDI includes a waveform one that can represent data 0 and a waveform two that can represent data 1. In the same preset clock cycle, both the waveform one and the waveform two include a period of high level and the durations of the high levels are not equal.

[0050] In the related art, within one clock cycle, data 0 is generally represented by a low level and data 1 is represented by a high level. By distinguishing between the high and low levels, data 1 and data 0 can be identified. In the embodiments of the present invention, however, the waveforms of data 0 and data 1 are reset, that is, waveform one represents data 0 and waveform two represents data 1. Both waveform one and waveform two include a section of high level. Under the same preset clock cycle, the duration of the high level in waveform one is not equal to that in waveform two. Regarding the specific duration of the high level in waveform one and waveform two, the embodiments of the present invention do not limit this, as long as data 0 and data 1 can be distinguished within the same clock cycle.

[0051] Optionally, referring to Figure 3 (a), the duration of the high level in waveform one is 3 / 4 of the preset clock cycle, and the duration of the high level in waveform two is 1 / 4 of the preset clock cycle.

[0052] Optionally, referring to Figure 3 (b), the duration of the high level in waveform one is 1 / 4 of the preset clock cycle, and the duration of the high level in waveform two is 3 / 4 of the preset clock cycle.

[0053] When the duration difference of the high level between waveform one and waveform two is 1 / 2 of the preset time cycle, not only can the high level be effectively recognized, but also waveform one and waveform two can be effectively distinguished, and thus data 0 and data 1 can be distinguished. It should be noted that the preset time cycle shown in the present invention can be understood as a complete cycle of the system clock (a virtual clock), which is used to indicate that the discussion of the difference between waveform one and waveform two is based on the same clock cycle. Of course, the frequency of this preset time cycle also determines the sampling frequency of data 0 and data 1, and can affect the time process from receiving the data signal SDI to outputting the data signal SDO. In practice, it can be set according to needs.

[0054] In practice, the data represented by the data signal SDI is a string of binary values. Therefore, waveform one and waveform two in the data signal SDI are also arranged in sequence corresponding to the binary values. For example, if the value of the data signal SDI is 1001, its corresponding waveform is as Figure 4 shown.

[0055] In the embodiments of the present invention, when the driving chip is the first driving chip cascaded with the control card, the data signal SDI is sent by the control card to the SDI input end of the driving chip through a data signal line. When the driving chip is any one of the driving chips in the cascade except the first one, the data signal SDI is sent by the previous cascaded driving chip to the SDI input end of the driving chip through a data signal line.

[0056] Step S204: The driving chip generates a multi-phase clock signal based on the data signal SDI. The multi-phase clock signal includes a clock signal A that is delayed by a first phase relative to the data signal SDI, a clock signal B that is delayed by a second phase, and a clock signal C that is delayed by a third phase. Herein, the first phase, the second phase, and the third phase are all different, and the second phase is located between the first phase and the third phase.

[0057] In an embodiment of the present invention, the idea of generating a multi-phase clock signal based on the data signal SDI is as follows: It is necessary to generate a clock signal corresponding to data 0, a clock signal corresponding to data 1, and a clock signal that can identify the clock signals corresponding to data 0 and data 1. Therefore, the multi-phase clock signal generated by the driving chip based on the data signal SDI includes at least three clock signals, such as clock signal A, clock signal B, and clock signal C.

[0058] Among them, clock signal A and clock signal C are used to generate data 0 and data 1. Therefore, the first phase and the third phase correspond to data 0 and data 1 respectively. The time delay of the first phase is equal to the duration of the high level in waveform one, and the time delay of the third phase is equal to the duration of the high level in waveform two.

[0059] Among them, if the phase of clock signal B is the same as that of data signal SDI, the data signal SDI cannot be sampled. Therefore, clock signal B also needs to have a phase delay relative to data signal SDI. And clock signal B is required to identify data 0 and data 1. Therefore, the second phase needs to be located between the first phase and the third phase.

[0060] It should be noted that multi-phase clock signals such as clock signal A, clock signal B, and clock signal C have the same periodic frequency as data signal SDI within one frame time, but have a phase delay relative to data signal SDI.

[0061] In an embodiment, 0° < the first phase < 180°, 180° < the third phase < 360°. That is, the duration of the high level of data 0 corresponding to the first phase is between infinitely close to 0° and infinitely close to 180°, and the duration of the high level of data 1 corresponding to the third phase is between infinitely close to 180° and infinitely close to 360°. In this embodiment, referring to FIGS. 5(a)-5(b), an exemplary schematic diagram of clock signal A and clock signal C compared with data signal SDI is shown. Among them, FIG. 5(a) shows the case where the first phase is infinitely close to 0° and the third phase is infinitely close to 180°, and FIG. 5(b) shows the case where the first phase is infinitely close to 180° and the third phase is infinitely close to 360°.

[0062] In another embodiment, 180° < the first phase < 360°, and 0° < the third phase < 180°. That is, the high-level duration of the data 0 corresponding to the first phase is between infinitely close to 180 and infinitely close to 360°, and the high-level duration of the data 1 corresponding to the third phase is between infinitely close to 0° and infinitely close to 180°. In this embodiment, referring to FIGS. 6(a)-6(b), schematic diagrams of the clock signal A and the clock signal C compared with the data signal SDI are shown. Among them, FIG. 6(a) shows the case where the first phase is infinitely close to 180° and the third phase is infinitely close to 0°, and FIG. 6(b) shows the case where the first phase is infinitely close to 360° and the third phase is infinitely close to 180°.

[0063] It should be noted that FIGS. 5(a)-5(b) and FIGS. 6(a)-6(b) show relatively extreme cases, which are not preferred generally for easy identification. Although FIGS. 5(a)-5(b) and FIGS. 6(a)-6(b) do not show the second phase, it can be correspondingly understood that the second phase is located between the first phase and the third phase. It can also be seen from FIGS. 5 and 6 that between the first phase and the third phase, the levels of the data 0 and the data 1 are one high and one low, so that they can be effectively distinguished.

[0064] For the convenience of sampling and waveform generation, preferably, the phase differences between the first phase, the second phase, and the third phase are all 90°.

[0065] Further, in one example, the first phase is 90°, the second phase is 180°, and the third phase is 270°.

[0066] Further, in another example, the first phase is 270°, the second phase is 180°, and the third phase is 90°.

[0067] Step S206, the driving chip generates a refresh clock signal and an edge selection signal according to the data signal SDI and the clock signal B; wherein, the rising edge of the refresh clock signal is aligned with the rising edge of the data signal SDI, and the falling edge is aligned with the rising edge of the clock signal B. The edge selection signal is obtained by sampling the data signal SDI through the rising edge of the clock signal B.

[0068] Step S208, the driving chip outputs a data signal SDO in phase with the data signal SDI based on the refresh clock signal, the edge selection signal, and the multi-phase clock signal; wherein, the rising edge of the data signal SDO is aligned with the rising edge of the refresh clock signal, and the falling edge of the data signal SDO is determined based on the edge selection signal and the multi-phase clock signal.

[0069] In step S206, referring to Figure 7, in the embodiment of the present invention, a refresh clock signal is generated based on the data signal SDI and the clock signal B. Among them, the rising edge of the refresh clock signal is aligned with the rising edge of the data signal SDI. In this way, the rising edge of the data signal SDO can be generated based on the rising edge of the refresh clock signal, which can ensure that the data signal SDO output by the driving chip is in the same phase as the data signal SDI.

[0070] In step S206, continue to refer to Figure 7 , in the embodiment of the present invention, an edge selection signal is also generated based on the data signal SDI and the clock signal B. Since the edge selection signal is obtained by sampling the data signal SDI through the rising edge of the clock signal B, it can be considered that the essence of the edge selection signal is to restore the waveform of the data signal SDI. Through the state of the level in the waveform selection signal, that is, according to different levels in the waveform selection signal, data 0 or data 1 in the data signal SDO can be generated in combination with the multi-phase clock signal.

[0071] Based on the foregoing content, the delay time of the first phase is equal to the duration of the high level in waveform one, and the delay time of the third phase is equal to the duration of the high level in waveform two. Therefore, the falling edge of data 0 in the data signal SDO can be determined according to the clock signal A, and the falling edge of data 1 in the data signal SDO can be determined according to the clock signal C. Then, the falling edge of the data signal SDO can be realized through the following embodiments:

[0072] The falling edge of the data signal SDO is aligned with the rising edge of the clock signal A or the rising edge of the clock signal C based on the edge selection signal.

[0073] In this embodiment, the specific implementation manner can have the following examples:

[0074] One example, refer to Figure 8 , when the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal C. In this example, the low level of the edge selection signal represents data 0, and the high level represents data 1. Therefore, when the edge selection signal is at a low level, the falling edge of the data signal SDO can be selected to be aligned with the rising edge of the clock signal A that can generate data 0; similarly, when the edge selection signal is at a high level, the falling edge of the data signal SDO can be selected to be aligned with the rising edge of the clock signal C that can generate data 1.

[0075] In another example, when the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal C; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A. In this example, the low level of the edge selection signal represents data 1, and the high level represents data 0. Therefore, when the edge selection signal is at a low level, the falling edge of the data signal SDO can be selected to be aligned with the rising edge of the clock signal C that can generate data 1; similarly, when the edge selection signal is at a high level, the falling edge of the data signal SDO can be selected to be aligned with the rising edge of the clock signal A that can generate data 0.

[0076] In summary, the driving chip according to the embodiment of the present invention can output a data signal SDO in the same phase as the data signal SDI by executing the data processing method, and can also internally generate a refresh clock signal whose rising edge is aligned with the data signal SDI. Therefore, each driving chip can perform data refreshing based on the refresh clock signal generated internally. In this way, only one data signal line can be used to achieve the refresh function that can only be achieved by using two signal lines (at least one clock signal line and one data signal line) in the prior art. Compared with the prior art, for each driving chip, at least two pins can be saved, the wiring is simplified, and it is beneficial to save the chip area.

[0077] In addition, since the data signal SDO output according to the embodiment of the present invention is in the same phase as the data signal SDI, that is, there is no phase delay between the output data signal SDO and the received data signal SDI. On this basis, since the rising edge of the generated refresh clock signal is aligned with the rising edges of both the data signal SDI and the data signal SDO, that is, the refresh clock signals generated by each driving chip based on the in-phase data signal SDI can also remain in the same phase. Theoretically, the refresh clock delay existing in the prior art can be eliminated by 100%, that is, the unknown delay between the input refresh clock signal CLK-in and the output refresh clock signal CLK-out is eliminated, so that each cascaded driving chip can synchronously refresh data.

[0078] Based on the same inventive concept, the embodiment of the present invention also provides a driving system. Refer to Figure 9 , which shows a schematic diagram of a driving system according to an embodiment of the present invention, including a control card and multiple cascaded driving chips. The driving chips are the driving chips as described in the embodiment of the present invention. The multiple cascaded driving chips are connected by one data signal line. The control card is connected to the first driving chip among the multiple cascaded driving chips by one data signal line. The data signal line is used to transmit the data signal SDI or the data signal SDO.

[0079] The implementation principle of the embodiments of the present invention will not be elaborated here. It should be noted that the drive system of the embodiments of the present invention can not only implement the refresh function that can only be achieved by using two signal lines (at least one clock signal line and one data signal line) in the prior art with only one data signal line. Compared with the prior art, the wiring is simplified, which is conducive to saving the manufacturing cost of the drive system. At the same time, it can also eliminate the unknown delay between the input refresh clock signal CLK-in and the output refresh clock signal CLK-out of each drive chip, enabling each drive chip in the drive system to synchronously refresh data.

[0080] Based on the same inventive concept, the embodiments of the present invention also provide a display module, including a display end and the drive system as described in the embodiments of the present invention. For the principle and effect of the embodiments of the present invention, reference can be made to the foregoing description and will not be elaborated here.

[0081] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0082] The above has introduced in detail a data processing method, device, drive chip and drive system provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A data processing method, characterized in that, the method includes: receiving a data signal SDI, the data signal SDI includes a waveform one representing data 0 and a waveform two representing data 1, in the same preset clock cycle, both the waveform one and the waveform two include a period of high level and the durations of the high levels are not equal; generating a multi-phase clock signal based on the data signal SDI, the multi-phase clock signal includes a clock signal A delayed by a first phase, a clock signal B delayed by a second phase, and a clock signal C delayed by a third phase compared to the data signal SDI; wherein, the first phase, the second phase, and the third phase are all different, and the second phase is located between the first phase and the third phase; generating a refresh clock signal and an edge selection signal according to the data signal SDI and the clock signal B; wherein, the rising edge of the refresh clock signal is aligned with the rising edge of the data signal SDI, and the falling edge is aligned with the rising edge of the clock signal B, and the edge selection signal samples the data signal SDI through the rising edge of the clock signal B; outputting a data signal SDO in phase with the data signal SDI based on the refresh clock signal, the edge selection signal, and the multi-phase clock signal; wherein, the rising edge of the data signal SDO is aligned with the rising edge of the refresh clock signal, and the falling edge of the data signal SDO is determined based on the edge selection signal and the multi-phase clock signal.

2. The data processing method according to claim 1, characterized in that, wherein, the time of delaying the first phase is equal to the duration of the high level in the waveform one, and the time of delaying the third phase is equal to the duration of the high level in the waveform two; the falling edge of the data signal SDO is determined based on the edge selection signal and the multi-phase clock signal, including: the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A or the rising edge of the clock signal C based on the edge selection signal.

3. The data processing method according to claim 2, characterized in that, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A or the rising edge of the clock signal C based on the edge selection signal, including: when the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal C; or when the edge selection signal is at a low level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal C; when the edge selection signal is at a high level, the falling edge of the data signal SDO is aligned with the rising edge of the clock signal A.

4. The data processing method according to any one of claims 1-3, characterized in that, wherein, 0° < first phase < 180°, 180° < third phase < 360°; or, 180° < First phase < 360°, 0° < Third phase < 180°.

5. The data processing method according to claim 4, wherein, the phase differences between the first phase, the second phase, and the third phase are all 90°.

6. The data processing method according to claim 5, wherein, the first phase is 90°, the second phase is 180°, and the third phase is 270°; or the first phase is 270°, the second phase is 180°, and the third phase is 90°.

7. A driving chip, wherein, the driving chip has an SDI input terminal and an SDO output terminal. The SDI input terminal is used to connect to a control card or the previous cascaded driving chip through a data signal line, and the SDO output terminal is used to connect to the next cascaded driving chip through a data signal line. Among them, in the case where the driving chip does not have a clock signal input terminal and a clock signal output terminal, it executes the data processing method according to any one of claims 1-6.

8. A driving system, wherein, it includes a control card and multiple cascaded driving chips. The driving chips are the driving chips according to claim 7. The multiple cascaded driving chips are connected through a data signal line. The control card is connected to the first driving chip among the multiple cascaded driving chips through a data signal line. The data signal line is used to transmit the data signal SDI or the data signal SDO.

9. A display module, wherein, it includes a display end and the driving system according to claim 8.

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