Method and apparatus for failure recovery of memory

Abstract

Embodiments of the present disclosure provide a memory failure repair method and device, the method comprising: performing a failure test on a main array of a memory to obtain a first test result; determining first failure units that are adjacently distributed in the memory according to the first test result; for at least one error correction code block, determining, from the first failure units included in each error correction code block, part of the first failure units as second failure units of the error correction code block; and repairing the second failure units. The present disclosure can determine the first failure units that are adjacently distributed as more serious failure units, and repair part of the first failure units in each error correction code block, while leaving the remaining first failure units to error correction functions. In this way, the number of failure units repaired can be reduced through error correction, that is, the number of redundant units required for repair is reduced, so that more redundant unit numbers can be reserved for subsequent detection, which helps to improve yield and reduce failure rate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for repairing memory faults. Background Technology

[0002] As a common component of computing devices, the failure rate of memory directly affects the user experience. Memory can be DRAM (dynamic random access memory), NAND flash memory, etc. Memory can be composed of primary arrays and redundant arrays, both of which are made up of memory cells. When a memory cell in the primary array (called a primary cell) fails, the primary cell can be repaired using memory cells in the redundant array (called redundant cells). The number of primary cells is usually greater than the number of redundant cells.

[0003] In existing technologies, performance tests can be performed on the memory before it leaves the factory to detect faulty cells from the main cells. Then, redundant units can be used to repair all faulty cells, so that the yield of the memory leaving the factory reaches the expected level and the read and write performance of the memory is guaranteed to be normal.

[0004] However, due to the limited number of redundant units, the above method results in a high final failure rate and low yield of the memory. Summary of the Invention

[0005] This disclosure provides a method and apparatus for repairing memory faults, thereby reducing the memory failure rate and improving the memory yield.

[0006] In a first aspect, embodiments of this disclosure provide a method for repairing memory faults, the method comprising:

[0007] A fault test was performed on the main array of the memory to obtain the first test result;

[0008] Based on the first test result, determine the first faulty cell distributed adjacently in the memory;

[0009] For at least one error correction code block, a portion of the first fault units included in each error correction code block are determined as second fault units of the error correction code block.

[0010] Repair the second faulty unit.

[0011] In some implementations, determining a portion of the first fault units from each of the error-correcting code blocks as second fault units of the error-correcting code block includes:

[0012] Determine the maximum number of faults that the error correction codes in the error correction code block can correct;

[0013] From the first fault units included in each error correction code block, a portion of the first fault units are selected as second fault units, such that the number of remaining first fault units in the error correction code block is less than or equal to the maximum number of faults.

[0014] In some implementations, selecting a portion of the first fault units from each of the error-correcting code blocks as second fault units, such that the number of remaining first fault units in the error-correcting code block is less than or equal to the maximum number of faults, includes:

[0015] The number of the first fault units included in the error correction code block is determined as the total number of faults;

[0016] The target number is determined based on the difference between the total number of faults and the maximum number of faults, wherein the target number is greater than or equal to the difference.

[0017] From the first fault units included in each of the error correction code blocks, the target number of first fault units are selected as second fault units.

[0018] In some implementations, selecting the target number of first fault units as second fault units from the first fault units included in each of the error-correcting code blocks includes:

[0019] From the first fault units included in each of the error correction code blocks, the target number of first fault units are randomly selected as second fault units.

[0020] In some implementations, the number of storage units for valid data included in the error correction code block is 128, the number of storage units for error correction data included in the error correction code block is 8, and the maximum number of faults is 1.

[0021] In some embodiments, the step of performing a fault test on the main array of the memory to obtain a first test result includes:

[0022] The main array of the memory is tested for faults by performing at least two test items, and a first test result is obtained for each test item.

[0023] The step of determining the first faulty cell in the memory based on the first test result includes:

[0024] Based on the first test result corresponding to each of the test items, the first faulty unit distributed adjacently in the memory is determined.

[0025] In some embodiments, after determining the first faulty cells distributed adjacently in the memory based on the first test result corresponding to each of the test items, the method further includes:

[0026] The first test results of each of the aforementioned test items are combined to obtain a composite test result;

[0027] The first faulty cell in the memory is determined based on the composite test results, and the same memory cell corresponds to a test result mark in the composite test results.

[0028] In some implementations, the first test result is represented by a first fault bitmap, the size of which is the same as the number of memory cells included in the main array of the memory, and each test result marker in the first fault bitmap is used to indicate whether the memory cell at the corresponding location in the main array is faulty.

[0029] In some implementations, the composite test result is a composite fault bitmap, and the merging of the first test results of each of the test items to obtain the composite test result includes:

[0030] For each storage cell in the memory, if the test result mark of the storage cell in the first fault bitmap of at least one of the test items indicates that there is a fault, then the test result mark of the storage cell in the composite fault bitmap is set to indicate that there is a fault.

[0031] If the test result markers of the storage unit in the first fault bitmap of all the test items indicate that there is no fault, then the test result marker corresponding to the storage unit in the composite fault bitmap is set to indicate that there is no fault.

[0032] In some embodiments, after repairing the second faulty unit, the method further includes:

[0033] With the error correction function enabled, a fault test is performed on the main array of the memory to obtain a second test result;

[0034] The failure rate and / or yield of the memory are evaluated based on the results of the second test.

[0035] In some embodiments, the step of performing a fault test on the main array of the memory to obtain a first test result includes:

[0036] With the error correction function disabled, a fault test is performed on the main array of the memory to obtain the first test result.

[0037] Secondly, embodiments of this disclosure provide a memory fault repair apparatus, comprising:

[0038] The first test module is used to perform fault testing on the main array of the memory to obtain a first test result;

[0039] The first fault unit determination module is used to determine the first fault units distributed adjacently in the memory based on the test results.

[0040] The second fault unit determination module is used to determine, for at least one error correction code block, a portion of the first fault units included in each error correction code block as the second fault units of the error correction code block.

[0041] The second fault unit repair module is used to repair the second fault unit.

[0042] In some embodiments, the second fault unit determining module is further configured to:

[0043] Determine the maximum number of faults that the error correction codes in the error correction code block can correct;

[0044] From the first fault units included in each error correction code block, a portion of the first fault units are selected as second fault units, such that the number of remaining first fault units in the error correction code block is less than or equal to the maximum number of faults.

[0045] In some embodiments, the second fault unit determining module is further configured to:

[0046] The number of the first fault units included in the error correction code block is determined as the total number of faults;

[0047] The target number is determined based on the difference between the total number of faults and the maximum number of faults, wherein the target number is greater than or equal to the difference.

[0048] From the first fault units included in each of the error correction code blocks, the target number of first fault units are selected as second fault units.

[0049] In some embodiments, the second fault unit determining module is further configured to:

[0050] From the first fault units included in each of the error correction code blocks, the target number of first fault units are randomly selected as second fault units.

[0051] In some implementations, the number of storage units for valid data included in the error correction code block is 128, the number of storage units for error correction data included in the error correction code block is 8, and the maximum number of faults is 1.

[0052] In some implementations, the first test module is further configured to:

[0053] The main array of the memory is tested for faults by performing at least two test items, and a first test result is obtained for each test item.

[0054] The first fault unit determination module is also used for:

[0055] Based on the first test result corresponding to each of the test items, the first faulty unit distributed adjacently in the memory is determined.

[0056] In some embodiments, the apparatus further includes:

[0057] The composite test result determination module is used to merge the first test results of each test item after determining the first fault units distributed adjacently in the memory based on the first test result corresponding to each test item, to obtain a composite test result.

[0058] The first fault unit addition module is used to determine the first fault units distributed adjacently in the memory based on the composite test results. The same memory unit corresponds to a test result mark in the composite test results.

[0059] In some implementations, the first test result is represented by a first fault bitmap, the size of which is the same as the number of memory cells included in the main array of the memory, and each test result marker in the first fault bitmap is used to indicate whether the memory cell at the corresponding location in the main array is faulty.

[0060] In some implementations, the composite test result is a composite fault bitmap, and the composite test result determination module is further used for:

[0061] For each storage cell in the memory, if the test result mark of the storage cell in the first fault bitmap of at least one of the test items indicates that there is a fault, then the test result mark of the storage cell in the composite fault bitmap is set to indicate that there is a fault.

[0062] If the test result markers of the storage unit in the first fault bitmap of all the test items indicate that there is no fault, then the test result marker corresponding to the storage unit in the composite fault bitmap is set to indicate that there is no fault.

[0063] In some embodiments, the apparatus further includes:

[0064] The second test module is used to perform a fault test on the main array of the memory after the second fault unit is repaired, with the error correction function enabled, and to obtain a second test result.

[0065] The parameter evaluation module is used to evaluate the failure rate and / or yield of the memory based on the second test results.

[0066] In some implementations, the first test module is further configured to:

[0067] With the error correction function disabled, a fault test is performed on the main array of the memory to obtain the first test result.

[0068] Thirdly, embodiments of this disclosure also provide an electronic device, including: at least one processor and a memory;

[0069] The memory stores computer-executed instructions;

[0070] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the method described in the first aspect.

[0071] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method described in the first aspect.

[0072] Fifthly, embodiments of this disclosure also provide a computer program product for performing the method described in the first aspect.

[0073] The memory fault repair method and apparatus provided in this disclosure can identify adjacent distributed first fault units as more serious fault units, repair a portion of the first fault units in each error correction code block, and reserve the remaining first fault units for the error correction function. In this way, the number of fault units to be repaired can be reduced through error correction, which reduces the number of redundant units required for repair. This allows for the retention of more redundant units for subsequent detection, helping to improve yield and reduce failure rate. Attached Figure Description

[0074] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0075] Figure 1 This is a schematic diagram of the structure of a memory array provided in an embodiment of the present disclosure;

[0076] Figure 2This is a flowchart of the steps of a memory fault repair method provided in an embodiment of this disclosure;

[0077] Figure 3 This is a schematic diagram of the structure of a first fault bitmap provided in an embodiment of this disclosure;

[0078] Figure 4 This is a schematic diagram of the structure of another first fault bitmap provided in an embodiment of this disclosure;

[0079] Figure 5 This is a schematic diagram of the structure of the composite fault bitmap provided in the embodiments of this disclosure;

[0080] Figure 6 This is a schematic diagram of the structure of a memory fault repair device provided in an embodiment of this disclosure;

[0081] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure.

[0082] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0083] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.

[0084] The embodiments disclosed herein are used to repair faulty cells in a memory so that the memory's read and write performance is restored to normal. Figure 1 This is a schematic diagram of the structure of a memory array provided in an embodiment of this disclosure. The memory array can be a main array or a redundant array. (Refer to...) Figure 1 As shown, the storage array 100 may include 81 storage cells 101 in 9 rows and 9 columns.

[0085] To ensure proper internal storage functionality, faulty cells in the main array of the memory must be inspected before shipment, and these faulty cells are repaired using redundant cells. However, since faulty cell inspection and repair are typically performed multiple times, and the faulty cells corresponding to different inspections may differ, if the redundant cells are exhausted during the repair of previously inspected faulty cells, subsequent inspected faulty cells will be unable to be repaired, leading to low memory yield and high failure rate. Furthermore, if severe faults are found in subsequently inspected faulty cells, the read / write accuracy of the memory will significantly decrease.

[0086] To address the aforementioned issues, embodiments of this disclosure can identify adjacently distributed first faulty units as more severe faulty units, and repair a portion of the first faulty units in each error correction code block, while reserving the remaining first faulty units for the error correction function. In this way, the number of faulty units requiring repair can be reduced through error correction, thus reducing the number of redundant units needed for repair. This allows for the retention of more redundant units for subsequent detection, contributing to improved yield and reduced failure rate. Furthermore, since redundant units prioritize repairing severely adjacently distributed first faulty units, the number of severely faulty units can be minimized, mitigating the decrease in read / write accuracy caused by severely faulty units.

[0087] The aforementioned error correction code function can be implemented using ECC (error correcting code) or ECS (error check and scrub). On-chip ECC / ECS is an advanced function used for error correction. During writing, not only valid data but also error-correcting data needs to be written. During reading, not only valid data but also error-correcting data needs to be read to correct errors in the valid data and improve data accuracy.

[0088] Figure 2 This is a flowchart illustrating the steps of a memory fault repair method provided in an embodiment of this disclosure. Please refer to... Figure 2 The fault repair methods for the aforementioned memory include:

[0089] S201: Perform a fault test on the main array of the memory to obtain the first test result.

[0090] The first test result indicates whether each memory cell has failed. The first test result may include multiple test result markers, each corresponding to a memory cell. For example, a test result marker of 1 for a memory cell indicates a failure, while a test result marker of 0 indicates no failure.

[0091] The order of the test result markers can be consistent with the order of the storage units in the memory, so that one storage unit corresponds to the test result markers at the same location.

[0092] In one implementation, the test result tags of all storage cells are arranged sequentially to form a sequence. For example, the sequence corresponding to 10 storage cells can be 1000000100. The first and eighth test results are marked as 1, indicating that the first and eighth storage cells are faulty. The remaining test results are marked as 0, indicating that the remaining storage cells are not faulty.

[0093] In another implementation, the first test result can be represented by a first fault bitmap. Each main array of the memory corresponds to one first fault bitmap to indicate whether a fault exists in each memory cell within the main array. Thus, the size of each first fault bitmap is the same as the number of memory cells included in a main array of the memory, and each test result marker in the first fault bitmap indicates whether a fault exists in the corresponding memory cell within the main array. For example, when the main array of the memory has I rows and J columns of memory cells, the first fault bitmap can also be I rows and J columns, and the i-th row and j-th column of the first fault bitmap stores the test result marker of the memory cell in the i-th row and j-th column. Here, I and J are integers greater than or equal to 1, i is an integer greater than or equal to 1 and less than or equal to 1, and j is an integer greater than or equal to 1 and less than or equal to J.

[0094] Figure 3 This is a schematic diagram of the structure of a first fault bitmap provided in an embodiment of this disclosure. (Refer to...) Figure 3 As shown, the first fault bitmap 102 includes 81 test result markers 103 in 9 rows and 9 columns, which are related to... Figure 1 correspond. Figure 3 The test result in row 3, column 1 is marked as 1, indicating a fault in the memory cell in row 3, column 1. Furthermore, Figure 3 The remaining test results marked 103 are all 0, indicating that there are no faults in the remaining storage units.

[0095] It should be noted that performing L fault tests will yield L first test results, where L is greater than or equal to 1. Each fault test corresponds to one first test result, and each first test result can be... Figure 3 The diagram shows a first fault bitmap, where each test result marker in the first fault bitmap is used to indicate whether each memory cell has failed.

[0096] The aforementioned L fault tests can correspond to L test items. Therefore, when L is greater than or equal to 2, the main array of the memory can be tested for faults using at least two test items, yielding a first test result for each test item. This first test result for each test item can be a first fault bitmap corresponding to that test item. Each test item is used to test at least one fault mode, and each test result marker in the first fault bitmap is used to indicate whether the corresponding memory cell has at least one fault.

[0097] In some implementations, the first test result mentioned above can be obtained by performing a fault test on the main array of the memory with the error correction function disabled. The error correction function corrects data errors caused by faulty cells on a block-by-block basis, preventing data errors. Therefore, even with the error correction function disabled, all faulty cells in the memory can be detected as much as possible, including those that may be corrected by the error correction codes. This allows for the selection of adjacent first faulty cells from all faulty cells, avoiding the omission of truly adjacent first faulty cells and contributing to further improvement in yield.

[0098] S202: Determine the first faulty cell in the adjacent distribution of the memory based on the first test result.

[0099] The first faulty cell is a faulty cell in the main array of the memory. The process of determining the first faulty cell may include: firstly, determining all corresponding faulty cells based on the first test results, and then determining the first faulty cell with adjacent distribution from all faulty cells.

[0100] The first fault unit in the adjacent distribution includes at least one of the following: adjacent fault units in the same row, adjacent fault units in the same column, and adjacent fault units in a block consisting of multiple rows and columns. The aforementioned adjacent fault units in the same row and adjacent fault units in the same column can be collectively referred to as linear trend fault units.

[0101] Understandably, the first faulty unit identified in S202 can be distributed within the same error correction code block or across different error correction code blocks. However, since DRAM error correction is performed on a unit basis (error correction code block), we need to select the second faulty unit to be repaired on a unit basis (error correction code block).

[0102] When S201 performs fault testing using multiple test items, multiple first test results can be obtained, each first test result corresponding to a test item. Therefore, for each test item's corresponding first test result, the first faulty cell in the memory, distributed adjacently, can be determined.

[0103] In some implementations, after determining the first faulty units in adjacent distributions based on the first test results of each test item, the first test results of each test item can be merged to obtain a composite test result, so as to determine the first faulty units in adjacent distributions in the memory based on the composite test result, and the same memory unit corresponds to a test result tag in the composite test result.

[0104] As can be seen, the test result marker in the above composite test results is used to represent the result obtained from multiple test items. When at least one test item indicates a fault in the corresponding storage unit, the test result marker indicates that the storage unit is faulty. When all test items indicate that the corresponding storage unit is not faulty, the test result marker indicates that the storage unit is not faulty.

[0105] In summary, on the one hand, fault testing can be performed using multiple test items, and the first test result of each test item can be used to identify the first faulty unit in an adjacent distribution, thereby detecting as many first faulty units as possible. On the other hand, the first test results of multiple test items can be combined. In this way, the combined composite test result may detect more first faulty units in an adjacent distribution, thus allowing these severely faulty units to be repaired, reducing the memory failure rate and improving the yield.

[0106] In some implementations, the first test result can be a first fault bitmap, and correspondingly, the composite test result is a composite fault bitmap. The size of the composite fault bitmap is the same as the size of the first fault bitmap of the first test result. The composite fault bitmap can be obtained through the following process: for each memory cell in the memory, if the test result mark of the memory cell in the first fault bitmap of at least one test item indicates the presence of a fault, then the test result mark of the memory cell in the composite fault bitmap is set to indicate the presence of a fault. If the test result mark of the memory cell in the first fault bitmap of all the test items indicates the absence of a fault, then the test result mark of the memory cell in the composite fault bitmap is set to indicate the absence of a fault.

[0107] When the above test result is marked as 1, it indicates that the corresponding memory unit is faulty. When the above test result is marked as 0, it indicates that the corresponding memory unit is not faulty. In this case, the composite fault bitmap can be the OR result of the first fault bitmaps of multiple test items. That is, the corresponding positions of multiple first fault bitmaps are ORed, and the result is used as the test result mark of the corresponding position in the composite fault bitmap.

[0108] Figure 4 This is a schematic diagram of another first fault bitmap provided in an embodiment of this disclosure. Figure 4 The first fault bitmap shown and Figure 3 The first fault bitmap shown can be understood as the first fault bitmap corresponding to each of the two test items. (Refer to...) Figure 4 As shown, the following test results in the first fault bitmap 102 are marked as 1: the test result mark in row 2, column 1; the test result marks in rows 3, columns 4 to 6; the test result mark in row 4, column 1; the test result marks in rows 5 to 7, columns 6; row 8, column 2; row 8, column 3; row 9, column 2; and row 9, column 3. In other words, the memory cell corresponding to the same location as the above test result mark 1 is faulty, while the other memory cells are not faulty.

[0109] The first fault unit in the linear trend includes: the storage units in rows 3, columns 4 to 6 are adjacent first fault units in the same row, and the storage units in rows 5 to 7, columns 6 are adjacent first fault units in the same column. The storage units in rows 8, columns 2, 8, 8, 9, and 9, columns 2 and 3 are adjacent first fault units in the same block.

[0110] Figure 5 This is a schematic diagram of the structure of the composite fault bitmap provided in an embodiment of this disclosure. Figure 5 The composite fault bitmap shown is Figure 3 and Figure 4 The two first fault bitmaps were obtained. (Refer to...) Figure 3 As shown, Figure 3 The test result in the 3rd row and 1st column is marked as 1. There are no adjacent test results marked as 1, therefore the storage unit in the 3rd row and 1st column is an independent fault unit. Figure 3 It will not be identified as the first fault cell in the adjacent distribution. Similarly, Figure 4 The storage unit in the second row and first column and Figure 4 The storage cell in row 4, column 1 is also an independent fault cell. And... Figure 3 and Figure 4 merged into Figure 5 after, Figure 5 The test results in the first column of row 2 to the first column of row 4 are marked as 1, according to... Figure 5 The storage cells in the first column of the second row to the first column of the fourth row are identified as the first fault cells in the adjacent distribution within the same column.

[0111] It should be noted that the correspondence between the test result markers and faults can be flexibly set. For example, a test result marker of 0 can represent a fault in the corresponding memory unit, while a test result marker of 1 can represent a fault-free memory unit. In this case, the composite fault bitmap can be the AND result of the first fault bitmaps of multiple test items. That is, the corresponding positions of multiple first fault bitmaps are ANDed, and the result is used as the test result marker for the corresponding position in the composite fault bitmap.

[0112] The embodiments of this disclosure can represent test results using a first fault bitmap, thereby converting the complex logical judgment of generating a composite fault bitmap into a logic gate implementation, which helps to reduce computational complexity.

[0113] S203: For at least one error-correcting code block, determine a portion of the first fault units from the first fault units included in each error-correcting code block as the second fault units of the error-correcting code block.

[0114] Each error-correcting code block includes two types of storage units. The first type stores valid data, and the second type stores error-correcting data. Error-correcting data can also be understood as redundant data. It is used to correct errors in the valid data, thereby reducing the error rate of the valid data and improving the read / write accuracy of the DRAM. For example, if the valid data is M bits and the error-correcting data is N bits, these N bits of error-correcting data can correct errors in the M bits of valid data.

[0115] In practical applications, the first type of storage unit is located in the main array, and the second type of storage unit is located in the error correction array. The main array and the error correction array are located in different regions of the memory.

[0116] In some implementations, the second fault unit is randomly selected from the first fault units. The remaining first fault units in each error-correcting code block are not repaired, but rather corrected by the error-correcting function of the error-correcting code block itself. As the number of selected second fault units increases, the number of remaining first fault units for the error-correcting code block to correct decreases, increasing the data storage accuracy of the storage units in the error-correcting code block. Therefore, to minimize the number of redundant units required to repair the second fault units and to ensure the data storage accuracy of the storage units as much as possible, the second fault unit can be selected based on the maximum number of faults that the error-correcting code block can correct.

[0117] In one embodiment, the selection process of the second fault unit may include: first, determining the maximum number of faults that the error correction code can correct in the error correction code block; then, selecting a portion of the first fault units from the first fault units included in each error correction code block as the second fault unit, so that the number of the remaining first fault units in the error correction code block is less than or equal to the maximum number of faults.

[0118] The maximum number of faults is determined by the number of storage units for valid data and the number of storage units for error-correcting data in the error-correcting code block. The maximum number of faults represents the error-correcting capability of the error-correcting code block; generally, it decreases as the number of storage units for valid data increases, and increases as the number of storage units for valid data increases.

[0119] In some implementations, a portion of the first fault units included in each error-correcting code block are selected as second fault units, so that the remaining first fault units in the error-correcting code block are within the error-correcting capability of the code block. Specifically, this can be achieved through the following process: First, determine the number of first fault units included in the error-correcting code block as the total number of faults; then, determine a target number based on the difference between the total number of faults and the maximum number of faults, where the target number is greater than or equal to the difference; finally, select the target number of first fault units from the first fault units included in each error-correcting code block as second fault units.

[0120] It is understandable that, since the first fault unit determined by S202 can be distributed in the same error correction code block or in different error correction code blocks, the number of the first fault unit in each error correction code block is greater than or equal to 0 and less than or equal to the number of the first fault unit determined by S202.

[0121] The target number in this embodiment is greater than or equal to the difference between the total number of faults and the maximum number of faults. As a result, the number of remaining first fault units in each error correction code block is less than or equal to the maximum number of faults that the error correction code block can correct. This ensures the accuracy of data storage in the storage units of each error correction code block and helps to maximize the yield of DRAM and reduce the failure rate.

[0122] The following example illustrates the relationship between the total number of faults, the maximum number of faults, and the target number for an error-correcting code block. For instance, the number of storage units for valid data in the error-correcting code block can be 128, and the number of storage units for error-correcting data can be 8. In this case, the maximum number of faults can be 1. When the total number of faults is 4, the target number can be the total number of faults 4 minus the maximum number of faults 1, which equals 3. That is, the number of second fault units that need to be repaired in this error-correcting code block is 3.

[0123] In some implementations, a target number of first fault units can be randomly selected as second fault units from the first fault units included in each error-correcting code block. Since the first fault units are all relatively severe fault units, the randomly selected second fault units can ensure that the more severe fault units are repaired. In addition, this random selection method can effectively reduce the complexity of selecting second fault units, helping to save repair time and improve repair efficiency.

[0124] S204: Repair the second faulty unit.

[0125] It is understandable that before repairing the second faulty unit, redundant units need to be allocated to each second faulty unit, that is, a one-to-one correspondence needs to be established between the second faulty unit and the redundant units. The redundant units of the second faulty unit can be randomly allocated or allocated according to a preset rule, where the preset rule can be based on the corresponding position. This embodiment of the disclosure does not limit the allocation rule of the redundant units.

[0126] In some implementations, after repairing the second faulty unit, a fault test can be performed on the main array of the memory with the error correction function enabled to obtain a second test result, which can then be used to evaluate the memory's failure rate and / or yield. This provides that, after executing the method of the embodiments of this disclosure, the memory's failure rate and / or yield is a performance parameter of the memory.

[0127] The fault test corresponding to the second test result and the fault test corresponding to the first test result may be the same or different. The sum of the above-mentioned failure rate and yield is usually 1. The failure rate is the proportion of the remaining faulty memory cells in all memory cells after the second faulty cell is repaired. The yield is the proportion of normal memory cells in all memory cells after the second faulty cell is repaired. Here, normal memory cells include the normal memory cells represented by the first test result and the repaired second faulty cell.

[0128] Error correction codes in this disclosure correct errors on a block-by-block basis. The number of correctable fault cells in the memory is the product of the number of error correction blocks in the memory and the maximum number of faults that each error correction block can correct. For example, for a memory capable of storing 8 Gb (gigabit) of valid data, it may include 2... 33 =8589934592. When the effective data quantity M of the error correction code block is 128 and the error correction data quantity is 8, the maximum number of faults that the error correction code block can correct is 1, and the number of error correction code blocks is 8589934592 / 128 = 67108864. Therefore, the number of faulty units that can be corrected on the memory is 67108864.

[0129] With error correction disabled, the failure rate (CFR) of the aforementioned 8Gb memory can be obtained using a Poisson distribution:

[0130]

[0131] Where p is the failure rate of a single storage unit on the user side.

[0132] Based on the above formula (1), it can be seen that when the error correction function is turned off, and the allowable failure rate of the memory is 100 to 1000 dppm (parts per million), the value of p can be 1.16 × 10⁻⁶. -14 Up to 1.16×10 -13 .

[0133] With error correction enabled, the memory failure rate can be obtained from a binomial distribution:

[0134]

[0135] Where Nc is the total number of error correction code blocks included in the memory, M is the number of storage units in an error correction code block that store valid data, and N is the number of storage units in an error correction code block that store error correction data.

[0136] Based on the above formula (2), it can be seen that when the error correction function is enabled, and when M=128 and N=8, the memory failure rate is between 100 and 1000 dppm, and the value of p can be 1.28 × 10⁻⁶. -8 Up to 4.03×10 -8 Correspondingly, each memory unit can tolerate between 110 and 346 faulty cells.

[0137] It can be seen that the value of p is greater when the error correction function is enabled than when the error correction function is disabled. In other words, the error correction function has a higher fault tolerance rate for a single faulty unit when it is enabled, which is improved by 5 to 6 orders.

[0138] Formulas (1) and (2) above are the failure rate analysis of conventional memory implementing error correction coding. The fault tolerance performance of the memory after implementing the fault repair method in the embodiments of this disclosure is given below. The following description takes M=128 and N=8 as an example, where one error correction code block can correct one faulty unit.

[0139] When the error correction function is enabled, the number of faulty cells in the memory that have been corrected in the test is denoted as Np. Therefore, the failure rate of the memory can be expressed by the following formula:

[0140] CFR≈Np×(M+N-1)×p (3)

[0141] When M = 128 and N = 8, it can be seen from the above formula (3) that, in the case of a memory failure rate of 100 to 1000 dppm, in order to provide users with protection against a failure rate of more than one hundred times that of a single memory cell (the value of p is approximately 10), -11 Each memory module can tolerate 70Kb (kilobits) to 700Kb of faulty cells. With 9Kb of redundant cells, the actual fault tolerance is improved by 80 to 800 times compared to relying solely on redundant cells.

[0142] When M=128 and N=8, the error-correcting code block can correct a maximum of 1 fault unit. Therefore, in order to ensure that each error-correcting code block contains no more than one fault unit, the number of random fault units Nrep that must be corrected can be expressed by the following formula:

[0143]

[0144] Where pd is the random unit failure rate before repair, and when M = 128, N = 8, Np = Nc × (1 - (1 - pd)). 136 With a value of 70Kb to 700Kb, the number of faulty units that need to be repaired is 36 to 3649. Considering that 9Kb of redundant units are needed to repair the remaining faults, and not just SBF (single bit failure), the number of single bit faulty units that must be repaired is within an acceptable range.

[0145] Corresponding to the above method embodiments, Figure 6 This is a schematic diagram of a memory fault repair device provided in an embodiment of this disclosure. Please refer to... Figure 6 The aforementioned memory fault repair device 400 includes:

[0146] The first test module 401 is used to perform fault testing on the main array of the memory to obtain a first test result.

[0147] The first fault unit determination module 402 is used to determine the first fault units distributed adjacent to each other in the memory based on the test results.

[0148] The second fault unit determination module 403 is configured to, for at least one error correction code block, determine a portion of the first fault units included in each error correction code block as second fault units of the error correction code block.

[0149] The second fault unit repair module 404 is used to repair the second fault unit.

[0150] In some embodiments, the second fault unit determining module 403 is further configured to:

[0151] Determine the maximum number of faults that the error correction codes in the error correction code block can correct.

[0152] From the first fault units included in each error correction code block, a portion of the first fault units are selected as second fault units, such that the number of remaining first fault units in the error correction code block is less than or equal to the maximum number of faults.

[0153] In some embodiments, the second fault unit determining module 403 is further configured to:

[0154] The number of the first fault units included in the error correction code block is determined as the total number of faults.

[0155] The target number is determined based on the difference between the total number of faults and the maximum number of faults, wherein the target number is greater than or equal to the difference.

[0156] From the first fault units included in each of the error correction code blocks, the target number of first fault units are selected as second fault units.

[0157] In some embodiments, the second fault unit determining module 403 is further configured to:

[0158] From the first fault units included in each error correction code block, a target number of the first fault units are randomly selected as second fault units.

[0159] In some implementations, the number of storage units for valid data included in the error correction code block is 128, the number of storage units for error correction data included in the error correction code block is 8, and the maximum number of faults is 1.

[0160] In some implementations, the first test module 401 is further configured to:

[0161] The main array of the memory is tested for faults by performing at least two test items, and a first test result is obtained for each test item.

[0162] The first fault unit determination module 402 is also used for:

[0163] Based on the first test result corresponding to each of the test items, the first faulty unit distributed adjacently in the memory is determined.

[0164] In some embodiments, the apparatus further includes:

[0165] The composite test result determination module is used to merge the first test results of each test item to obtain a composite test result after determining the first fault units distributed adjacently in the memory based on the first test result corresponding to each test item.

[0166] The first fault unit addition module is used to determine the first fault units distributed adjacently in the memory based on the composite test results. The same memory unit corresponds to a test result mark in the composite test results.

[0167] In some implementations, the first test result is represented by a first fault bitmap, the size of which is the same as the number of memory cells included in the main array of the memory, and each test result marker in the first fault bitmap is used to indicate whether the memory cell at the corresponding location in the main array is faulty.

[0168] In some implementations, the composite test result is a composite fault bitmap, and the composite test result determination module is further used for:

[0169] For each storage cell in the memory, if the test result mark of the storage cell in the first fault bitmap of at least one of the test items indicates that there is a fault, then the test result mark of the storage cell in the composite fault bitmap is set to indicate that there is a fault.

[0170] If the test result markers of the storage unit in the first fault bitmap of all the test items indicate that there is no fault, then the test result marker corresponding to the storage unit in the composite fault bitmap is set to indicate that there is no fault.

[0171] In some embodiments, the apparatus further includes:

[0172] The second test module is used to perform a fault test on the main array of the memory after the second faulty unit is repaired, with the error correction function enabled, and to obtain a second test result.

[0173] The parameter evaluation module is used to evaluate the failure rate and / or yield of the memory based on the second test results.

[0174] In some implementations, the first test module 401 is further configured to:

[0175] With the error correction function disabled, a fault test is performed on the main array of the memory to obtain the first test result.

[0176] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.

[0177] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 600 includes a memory 602 and at least one processor 601.

[0178] Among them, memory 602 stores computer-executed instructions.

[0179] At least one processor 601 executes computer execution instructions stored in memory 602, causing electronic device 601 to implement the aforementioned memory fault repair method.

[0180] In addition, the electronic device may also include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send information to other devices or equipment.

[0181] This disclosure also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, enable the computing device to implement a memory fault repair method.

[0182] This disclosure also provides a computer program product for executing the above-described memory fault repair method.

[0183] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0184] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0185] The above are merely preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.

Claims

1. A method for repairing memory faults, characterized in that, The method includes: A fault test was performed on the main array of the memory to obtain the first test result; Based on the first test result, determine the first faulty cell distributed adjacently in the memory; For at least one error correction code block, a portion of the first fault units included in each error correction code block are determined as second fault units of the error correction code block. Repairing the second fault unit; determining a portion of the first fault units from the first fault units included in each error correction code block as the second fault units of the error correction code block includes: Determine the maximum number of faults that the error correction codes in the error correction code block can correct; From the first fault units included in each error correction code block, a portion of the first fault units are selected as second fault units, such that the number of remaining first fault units in the error correction code block is less than or equal to the maximum number of faults.

2. The method according to claim 1, characterized in that, The step of selecting a portion of the first fault units from the first fault units included in each error-correcting code block as second fault units, such that the number of remaining first fault units in the error-correcting code block is less than or equal to the maximum number of faults, includes: The number of the first fault units included in the error correction code block is determined as the total number of faults; The target number is determined based on the difference between the total number of faults and the maximum number of faults, wherein the target number is greater than or equal to the difference. From the first fault units included in each of the error correction code blocks, the target number of first fault units are selected as second fault units.

3. The method according to claim 2, characterized in that, Selecting the target number of first fault units as second fault units from the first fault units included in each of the error correction code blocks includes: From the first fault units included in each error correction code block, a target number of the first fault units are randomly selected as second fault units.

4. The method according to claim 2 or 3, characterized in that, The number of storage units for valid data included in the error correction code block is 128, the number of storage units for error correction data included in the error correction code block is 8, and the maximum number of faults is 1.

5. The method according to any one of claims 1 to 3, characterized in that, The first test result obtained by performing a fault test on the main array of the memory includes: The main array of the memory is tested for faults by performing at least two test items, and a first test result is obtained for each test item. The step of determining the first faulty cell in the memory, which is distributed adjacently, based on the first test result includes: Based on the first test result corresponding to each of the test items, the first faulty unit distributed adjacently in the memory is determined.

6. The method according to claim 5, characterized in that, After determining the first faulty units distributed adjacently in the memory based on the first test result corresponding to each of the test items, the method further includes: The first test results of each of the aforementioned test items are combined to obtain a composite test result; The first faulty cell in the memory is determined based on the composite test results, and the same memory cell corresponds to a test result mark in the composite test results.

7. The method according to claim 6, characterized in that, The first test result is represented by a first fault bitmap, the size of which is the same as the number of storage cells included in the main array of the memory. Each test result marker in the first fault bitmap is used to indicate whether the storage cell at the corresponding position in the main array is faulty.

8. The method according to claim 7, characterized in that, The composite test result is a composite fault bitmap. The first test results of each of the test items are merged to obtain the composite test result, including: For each storage cell in the memory, if the test result mark of the storage cell in the first fault bitmap of at least one of the test items indicates that there is a fault, then the test result mark of the storage cell in the composite fault bitmap is set to indicate that there is a fault. If the test result markers of the storage unit in the first fault bitmap of all the test items indicate that there is no fault, then the test result marker corresponding to the storage unit in the composite fault bitmap is set to indicate that there is no fault.

9. The method according to any one of claims 1 to 3, characterized in that, After repairing the second faulty unit, the method further includes: With the error correction function enabled, a fault test is performed on the main array of the memory to obtain a second test result; The failure rate and / or yield of the memory are evaluated based on the results of the second test.

10. The method according to any one of claims 1 to 3, characterized in that, The first test result obtained by performing a fault test on the main array of the memory includes: With the error correction function disabled, a fault test is performed on the main array of the memory to obtain the first test result.

11. A fault repair device for a memory, characterized in that, include: The first test module is used to perform fault testing on the main array of the memory to obtain a first test result; The first fault unit determination module is used to determine the first fault units distributed adjacently in the memory based on the first test result. The second fault unit determination module is used to determine, for at least one error correction code block, a portion of the first fault units included in each error correction code block as the second fault units of the error correction code block. The second fault unit repair module is used to repair the second fault unit.

12. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method as described in any one of claims 1 to 10.

14. A computer program product, characterized in that, The computer program product is used to perform the method according to any one of claims 1 to 10.

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